1 ;*****************************************************************************
2 ;* x86inc.asm: x264asm abstraction layer
3 ;*****************************************************************************
4 ;* Copyright (C) 2005-2017 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Anton Mitrofanov <BugMaster@narod.ru>
8 ;* Fiona Glaser <fiona@x264.com>
9 ;* Henrik Gramner <henrik@gramner.com>
11 ;* Permission to use, copy, modify, and/or distribute this software for any
12 ;* purpose with or without fee is hereby granted, provided that the above
13 ;* copyright notice and this permission notice appear in all copies.
15 ;* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16 ;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17 ;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18 ;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19 ;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20 ;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21 ;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 ;*****************************************************************************
24 ; This is a header file for the x264ASM assembly language, which uses
25 ; NASM/YASM syntax combined with a large number of macros to provide easy
26 ; abstraction between different calling conventions (x86_32, win64, linux64).
27 ; It also has various other useful features to simplify writing the kind of
28 ; DSP functions that are most often used in x264.
30 ; Unlike the rest of x264, this file is available under an ISC license, as it
31 ; has significant usefulness outside of x264 and we want it to be available
32 ; to the largest audience possible. Of course, if you modify it for your own
33 ; purposes to add a new feature, we strongly encourage contributing a patch
34 ; as this feature might be useful for others as well. Send patches or ideas
35 ; to x264-devel@videolan.org .
37 %ifndef private_prefix
38 %define private_prefix x264
42 %define public_prefix private_prefix
45 %if HAVE_ALIGNED_STACK
46 %define STACK_ALIGNMENT 16
48 %ifndef STACK_ALIGNMENT
50 %define STACK_ALIGNMENT 16
52 %define STACK_ALIGNMENT 4
59 %ifidn __OUTPUT_FORMAT__,win32
61 %elifidn __OUTPUT_FORMAT__,win64
63 %elifidn __OUTPUT_FORMAT__,x64
71 %ifidn __OUTPUT_FORMAT__,elf
73 %elifidn __OUTPUT_FORMAT__,elf32
75 %elifidn __OUTPUT_FORMAT__,elf64
80 %define mangle(x) _ %+ x
85 ; aout does not support align=
86 ; NOTE: This section is out of sync with x264, in order to
87 ; keep supporting OS/2.
88 %macro SECTION_RODATA 0-1 16
89 %ifidn __OUTPUT_FORMAT__,aout
91 %elifidn __OUTPUT_FORMAT__,coff
94 SECTION .rodata align=%1
100 %elif ARCH_X86_64 == 0
101 ; x86_32 doesn't require PIC.
102 ; Some distros prefer shared objects to be PIC, but nothing breaks if
103 ; the code contains a few textrels, so we'll skip that complexity.
116 ; Macros to eliminate most code duplication between x86_32 and x86_64:
117 ; Currently this works only for leaf functions which load all their arguments
118 ; into registers at the start, and make no other use of the stack. Luckily that
119 ; covers most of x264's asm.
122 ; %1 = number of arguments. loads them from stack if needed.
123 ; %2 = number of registers used. pushes callee-saved regs if needed.
124 ; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.
125 ; %4 = (optional) stack size to be allocated. The stack will be aligned before
126 ; allocating the specified stack size. If the required stack alignment is
127 ; larger than the known stack alignment the stack will be manually aligned
128 ; and an extra register will be allocated to hold the original stack
129 ; pointer (to not invalidate r0m etc.). To prevent the use of an extra
130 ; register as stack pointer, request a negative stack size.
131 ; %4+/%5+ = list of names to define to registers
132 ; PROLOGUE can also be invoked by adding the same options to cglobal
135 ; cglobal foo, 2,3,7,0x40, dst, src, tmp
136 ; declares a function (foo) that automatically loads two arguments (dst and
137 ; src) into registers, uses one additional register (tmp) plus 7 vector
138 ; registers (m0-m6) and allocates 0x40 bytes of stack space.
140 ; TODO Some functions can use some args directly from the stack. If they're the
141 ; last args then you can just not declare them, but if they're in the middle
142 ; we need more flexible macro.
145 ; Pops anything that was pushed by PROLOGUE, and returns.
148 ; Use this instead of RET if it's a branch target.
151 ; rN and rNq are the native-size register holding function argument N
152 ; rNd, rNw, rNb are dword, word, and byte size
153 ; rNh is the high 8 bits of the word size
154 ; rNm is the original location of arg N (a register or on the stack), dword
155 ; rNmp is native size
157 %macro DECLARE_REG 2-3
167 %elif ARCH_X86_64 ; memory
168 %define r%1m [rstk + stack_offset + %3]
169 %define r%1mp qword r %+ %1 %+ m
171 %define r%1m [rstk + stack_offset + %3]
172 %define r%1mp dword r %+ %1 %+ m
177 %macro DECLARE_REG_SIZE 3
193 DECLARE_REG_SIZE ax, al, ah
194 DECLARE_REG_SIZE bx, bl, bh
195 DECLARE_REG_SIZE cx, cl, ch
196 DECLARE_REG_SIZE dx, dl, dh
197 DECLARE_REG_SIZE si, sil, null
198 DECLARE_REG_SIZE di, dil, null
199 DECLARE_REG_SIZE bp, bpl, null
201 ; t# defines for when per-arch register allocation is more complex than just function arguments
203 %macro DECLARE_REG_TMP 1-*
206 CAT_XDEFINE t, %%i, r%1
212 %macro DECLARE_REG_TMP_SIZE 0-*
214 %define t%1q t%1 %+ q
215 %define t%1d t%1 %+ d
216 %define t%1w t%1 %+ w
217 %define t%1h t%1 %+ h
218 %define t%1b t%1 %+ b
223 DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
234 %assign stack_offset stack_offset+gprsize
241 %assign stack_offset stack_offset-gprsize
245 %macro PUSH_IF_USED 1-*
254 %macro POP_IF_USED 1-*
263 %macro LOAD_IF_USED 1-*
266 mov r%1, r %+ %1 %+ mp
275 %assign stack_offset stack_offset+(%2)
282 %assign stack_offset stack_offset-(%2)
292 %macro movsxdifnidn 2
300 %error assertion ``%1'' failed
304 %macro DEFINE_ARGS 0-*
308 CAT_UNDEF arg_name %+ %%i, q
309 CAT_UNDEF arg_name %+ %%i, d
310 CAT_UNDEF arg_name %+ %%i, w
311 CAT_UNDEF arg_name %+ %%i, h
312 CAT_UNDEF arg_name %+ %%i, b
313 CAT_UNDEF arg_name %+ %%i, m
314 CAT_UNDEF arg_name %+ %%i, mp
315 CAT_UNDEF arg_name, %%i
320 %xdefine %%stack_offset stack_offset
321 %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine
324 %xdefine %1q r %+ %%i %+ q
325 %xdefine %1d r %+ %%i %+ d
326 %xdefine %1w r %+ %%i %+ w
327 %xdefine %1h r %+ %%i %+ h
328 %xdefine %1b r %+ %%i %+ b
329 %xdefine %1m r %+ %%i %+ m
330 %xdefine %1mp r %+ %%i %+ mp
331 CAT_XDEFINE arg_name, %%i, %1
335 %xdefine stack_offset %%stack_offset
336 %assign n_arg_names %0
339 %define required_stack_alignment ((mmsize + 15) & ~15)
341 %macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)
345 %assign stack_size %1
347 %assign stack_size -stack_size
350 %assign %%pad %%pad + 32 ; shadow space
352 %assign xmm_regs_used %2
353 %if xmm_regs_used > 8
354 %assign %%pad %%pad + (xmm_regs_used-8)*16 ; callee-saved xmm registers
358 %if required_stack_alignment <= STACK_ALIGNMENT
359 ; maintain the current stack alignment
360 %assign stack_size_padded stack_size + %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
361 SUB rsp, stack_size_padded
363 %assign %%reg_num (regs_used - 1)
364 %xdefine rstk r %+ %%reg_num
365 ; align stack, and save original stack location directly above
366 ; it, i.e. in [rsp+stack_size_padded], so we can restore the
367 ; stack in a single instruction (i.e. mov rsp, rstk or mov
368 ; rsp, [rsp+stack_size_padded])
369 %if %1 < 0 ; need to store rsp on stack
370 %xdefine rstkm [rsp + stack_size + %%pad]
371 %assign %%pad %%pad + gprsize
372 %else ; can keep rsp in rstk during whole function
375 %assign stack_size_padded stack_size + ((%%pad + required_stack_alignment-1) & ~(required_stack_alignment-1))
377 and rsp, ~(required_stack_alignment-1)
378 sub rsp, stack_size_padded
379 movifnidn rstkm, rstk
386 %macro SETUP_STACK_POINTER 1
388 %if %1 != 0 && required_stack_alignment > STACK_ALIGNMENT
390 ; Reserve an additional register for storing the original stack pointer, but avoid using
391 ; eax/rax for this purpose since it can potentially get overwritten as a return value.
392 %assign regs_used (regs_used + 1)
393 %if ARCH_X86_64 && regs_used == 7
395 %elif ARCH_X86_64 == 0 && regs_used == 1
399 %if ARCH_X86_64 && regs_used < 5 + UNIX64 * 3
400 ; Ensure that we don't clobber any registers containing arguments. For UNIX64 we also preserve r6 (rax)
401 ; since it's used as a hidden argument in vararg functions to specify the number of vector registers used.
402 %assign regs_used 5 + UNIX64 * 3
408 %macro DEFINE_ARGS_INTERNAL 3+
418 %if WIN64 ; Windows x64 ;=================================================
424 DECLARE_REG 4, R10, 40
425 DECLARE_REG 5, R11, 48
426 DECLARE_REG 6, rax, 56
427 DECLARE_REG 7, rdi, 64
428 DECLARE_REG 8, rsi, 72
429 DECLARE_REG 9, rbx, 80
430 DECLARE_REG 10, rbp, 88
431 DECLARE_REG 11, R14, 96
432 DECLARE_REG 12, R15, 104
433 DECLARE_REG 13, R12, 112
434 DECLARE_REG 14, R13, 120
436 %macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
439 ASSERT regs_used >= num_args
440 SETUP_STACK_POINTER %4
441 ASSERT regs_used <= 15
442 PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14
444 %if mmsize != 8 && stack_size == 0
447 LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
448 DEFINE_ARGS_INTERNAL %0, %4, %5
451 %macro WIN64_PUSH_XMM 0
452 ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.
453 %if xmm_regs_used > 6
454 movaps [rstk + stack_offset + 8], xmm6
456 %if xmm_regs_used > 7
457 movaps [rstk + stack_offset + 24], xmm7
459 %if xmm_regs_used > 8
462 movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i
468 %macro WIN64_SPILL_XMM 1
469 %assign xmm_regs_used %1
470 ASSERT xmm_regs_used <= 16
471 %if xmm_regs_used > 8
472 ; Allocate stack space for callee-saved xmm registers plus shadow space and align the stack.
473 %assign %%pad (xmm_regs_used-8)*16 + 32
474 %assign stack_size_padded %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
475 SUB rsp, stack_size_padded
480 %macro WIN64_RESTORE_XMM_INTERNAL 0
482 %if xmm_regs_used > 8
483 %assign %%i xmm_regs_used
486 movaps xmm %+ %%i, [rsp + (%%i-8)*16 + stack_size + 32]
489 %if stack_size_padded > 0
490 %if stack_size > 0 && required_stack_alignment > STACK_ALIGNMENT
493 add rsp, stack_size_padded
494 %assign %%pad_size stack_size_padded
497 %if xmm_regs_used > 7
498 movaps xmm7, [rsp + stack_offset - %%pad_size + 24]
500 %if xmm_regs_used > 6
501 movaps xmm6, [rsp + stack_offset - %%pad_size + 8]
505 %macro WIN64_RESTORE_XMM 0
506 WIN64_RESTORE_XMM_INTERNAL
507 %assign stack_offset (stack_offset-stack_size_padded)
508 %assign stack_size_padded 0
509 %assign xmm_regs_used 0
512 %define has_epilogue regs_used > 7 || xmm_regs_used > 6 || mmsize == 32 || stack_size > 0
515 WIN64_RESTORE_XMM_INTERNAL
516 POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7
523 %elif ARCH_X86_64 ; *nix x64 ;=============================================
531 DECLARE_REG 6, rax, 8
532 DECLARE_REG 7, R10, 16
533 DECLARE_REG 8, R11, 24
534 DECLARE_REG 9, rbx, 32
535 DECLARE_REG 10, rbp, 40
536 DECLARE_REG 11, R14, 48
537 DECLARE_REG 12, R15, 56
538 DECLARE_REG 13, R12, 64
539 DECLARE_REG 14, R13, 72
541 %macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
544 ASSERT regs_used >= num_args
545 SETUP_STACK_POINTER %4
546 ASSERT regs_used <= 15
547 PUSH_IF_USED 9, 10, 11, 12, 13, 14
549 LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14
550 DEFINE_ARGS_INTERNAL %0, %4, %5
553 %define has_epilogue regs_used > 9 || mmsize == 32 || stack_size > 0
556 %if stack_size_padded > 0
557 %if required_stack_alignment > STACK_ALIGNMENT
560 add rsp, stack_size_padded
563 POP_IF_USED 14, 13, 12, 11, 10, 9
570 %else ; X86_32 ;==============================================================
572 DECLARE_REG 0, eax, 4
573 DECLARE_REG 1, ecx, 8
574 DECLARE_REG 2, edx, 12
575 DECLARE_REG 3, ebx, 16
576 DECLARE_REG 4, esi, 20
577 DECLARE_REG 5, edi, 24
578 DECLARE_REG 6, ebp, 28
581 %macro DECLARE_ARG 1-*
583 %define r%1m [rstk + stack_offset + 4*%1 + 4]
584 %define r%1mp dword r%1m
589 DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
591 %macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
594 ASSERT regs_used >= num_args
601 SETUP_STACK_POINTER %4
602 ASSERT regs_used <= 7
603 PUSH_IF_USED 3, 4, 5, 6
605 LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6
606 DEFINE_ARGS_INTERNAL %0, %4, %5
609 %define has_epilogue regs_used > 3 || mmsize == 32 || stack_size > 0
612 %if stack_size_padded > 0
613 %if required_stack_alignment > STACK_ALIGNMENT
616 add rsp, stack_size_padded
619 POP_IF_USED 6, 5, 4, 3
626 %endif ;======================================================================
629 %macro WIN64_SPILL_XMM 1
631 %macro WIN64_RESTORE_XMM 0
633 %macro WIN64_PUSH_XMM 0
637 ; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either
638 ; a branch or a branch target. So switch to a 2-byte form of ret in that case.
639 ; We can automatically detect "follows a branch", but not a branch target.
640 ; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)
642 %if has_epilogue || cpuflag(ssse3)
647 annotate_function_size
650 %define last_branch_adr $$
651 %macro AUTO_REP_RET 0
652 %if notcpuflag(ssse3)
653 times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ == last_branch_adr.
656 annotate_function_size
659 %macro BRANCH_INSTR 0-*
663 %if notcpuflag(ssse3)
665 %xdefine last_branch_adr %%branch_instr
672 BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp
674 %macro TAIL_CALL 2 ; callee, is_nonadjacent
681 annotate_function_size
684 ;=============================================================================
685 ; arch-independent part
686 ;=============================================================================
688 %assign function_align 16
691 ; Applies any symbol mangling needed for C linkage, and sets up a define such that
692 ; subsequent uses of the function name automatically refer to the mangled version.
693 ; Appends cpuflags to the function name if cpuflags has been specified.
694 ; The "" empty default parameter is a workaround for nasm, which fails if SUFFIX
695 ; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).
696 %macro cglobal 1-2+ "" ; name, [PROLOGUE args]
697 cglobal_internal 1, %1 %+ SUFFIX, %2
699 %macro cvisible 1-2+ "" ; name, [PROLOGUE args]
700 cglobal_internal 0, %1 %+ SUFFIX, %2
702 %macro cglobal_internal 2-3+
703 annotate_function_size
705 %xdefine %%FUNCTION_PREFIX private_prefix
706 %xdefine %%VISIBILITY hidden
708 %xdefine %%FUNCTION_PREFIX public_prefix
709 %xdefine %%VISIBILITY
712 %xdefine %2 mangle(%%FUNCTION_PREFIX %+ _ %+ %2)
713 %xdefine %2.skip_prologue %2 %+ .skip_prologue
714 CAT_XDEFINE cglobaled_, %2, 1
716 %xdefine current_function %2
717 %xdefine current_function_section __SECT__
719 global %2:function %%VISIBILITY
725 RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer
726 %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required
727 %assign stack_offset 0 ; stack pointer offset relative to the return address
728 %assign stack_size 0 ; amount of stack space that can be freely used inside a function
729 %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding
730 %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64
737 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
738 CAT_XDEFINE cglobaled_, %1, 1
742 ; like cextern, but without the prefix
743 %macro cextern_naked 1
745 %xdefine %1 mangle(%1)
747 CAT_XDEFINE cglobaled_, %1, 1
752 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
754 global %1:data hidden
761 ; This is needed for ELF, otherwise the GNU linker assumes the stack is executable by default.
763 [SECTION .note.GNU-stack noalloc noexec nowrite progbits]
766 ; Tell debuggers how large the function was.
767 ; This may be invoked multiple times per function; we rely on later instances overriding earlier ones.
768 ; This is invoked by RET and similar macros, and also cglobal does it for the previous function,
769 ; but if the last function in a source file doesn't use any of the standard macros for its epilogue,
770 ; then its size might be unspecified.
771 %macro annotate_function_size 0
773 %ifdef current_function
775 current_function_section
777 size current_function %%ecf - current_function
786 %assign cpuflags_mmx (1<<0)
787 %assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
788 %assign cpuflags_3dnow (1<<2) | cpuflags_mmx
789 %assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow
790 %assign cpuflags_sse (1<<4) | cpuflags_mmx2
791 %assign cpuflags_sse2 (1<<5) | cpuflags_sse
792 %assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
793 %assign cpuflags_lzcnt (1<<7) | cpuflags_sse2
794 %assign cpuflags_sse3 (1<<8) | cpuflags_sse2
795 %assign cpuflags_ssse3 (1<<9) | cpuflags_sse3
796 %assign cpuflags_sse4 (1<<10)| cpuflags_ssse3
797 %assign cpuflags_sse42 (1<<11)| cpuflags_sse4
798 %assign cpuflags_aesni (1<<12)| cpuflags_sse42
799 %assign cpuflags_avx (1<<13)| cpuflags_sse42
800 %assign cpuflags_xop (1<<14)| cpuflags_avx
801 %assign cpuflags_fma4 (1<<15)| cpuflags_avx
802 %assign cpuflags_fma3 (1<<16)| cpuflags_avx
803 %assign cpuflags_bmi1 (1<<17)| cpuflags_avx|cpuflags_lzcnt
804 %assign cpuflags_bmi2 (1<<18)| cpuflags_bmi1
805 %assign cpuflags_avx2 (1<<19)| cpuflags_fma3|cpuflags_bmi2
807 %assign cpuflags_cache32 (1<<20)
808 %assign cpuflags_cache64 (1<<21)
809 %assign cpuflags_slowctz (1<<22)
810 %assign cpuflags_aligned (1<<23) ; not a cpu feature, but a function variant
811 %assign cpuflags_atom (1<<24)
813 ; Returns a boolean value expressing whether or not the specified cpuflag is enabled.
814 %define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1)
815 %define notcpuflag(x) (cpuflag(x) ^ 1)
817 ; Takes an arbitrary number of cpuflags from the above list.
818 ; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.
819 ; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.
820 %macro INIT_CPUFLAGS 0-*
828 %xdefine cpuname cpuname %+ _%1
832 %assign cpuflags cpuflags | cpuflags_%1
835 %xdefine SUFFIX _ %+ cpuname
838 %assign avx_enabled 1
840 %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))
843 %define movnta movntps
847 %elif cpuflag(sse3) && notcpuflag(ssse3)
852 %if ARCH_X86_64 || cpuflag(sse2)
860 ; m# is a simd register of the currently selected size
861 ; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#
862 ; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#
863 ; (All 3 remain in sync through SWAP.)
874 %assign avx_enabled 0
875 %define RESET_MM_PERMUTATION INIT_MMX %1
881 %define movnta movntq
884 CAT_XDEFINE m, %%i, mm %+ %%i
885 CAT_XDEFINE nnmm, %%i, %%i
897 %assign avx_enabled 0
898 %define RESET_MM_PERMUTATION INIT_XMM %1
902 %define num_mmregs 16
907 %define movnta movntdq
910 CAT_XDEFINE m, %%i, xmm %+ %%i
911 CAT_XDEFINE nnxmm, %%i, %%i
918 %assign avx_enabled 1
919 %define RESET_MM_PERMUTATION INIT_YMM %1
923 %define num_mmregs 16
928 %define movnta movntdq
931 CAT_XDEFINE m, %%i, ymm %+ %%i
932 CAT_XDEFINE nnymm, %%i, %%i
940 %macro DECLARE_MMCAST 1
945 %define xmmxmm%1 xmm%1
946 %define xmmymm%1 xmm%1
948 %define ymmxmm%1 xmm%1
949 %define ymmymm%1 ymm%1
950 %define xm%1 xmm %+ m%1
951 %define ym%1 ymm %+ m%1
960 ; I often want to use macros that permute their arguments. e.g. there's no
961 ; efficient way to implement butterfly or transpose or dct without swapping some
964 ; I would like to not have to manually keep track of the permutations:
965 ; If I insert a permutation in the middle of a function, it should automatically
966 ; change everything that follows. For more complex macros I may also have multiple
967 ; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.
969 ; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that
970 ; permutes its arguments. It's equivalent to exchanging the contents of the
971 ; registers, except that this way you exchange the register names instead, so it
972 ; doesn't cost any cycles.
974 %macro PERMUTE 2-* ; takes a list of pairs to swap
981 CAT_XDEFINE nn, m%1, %1
986 %macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)
987 %ifnum %1 ; SWAP 0, 1, ...
988 SWAP_INTERNAL_NUM %1, %2
989 %else ; SWAP m0, m1, ...
990 SWAP_INTERNAL_NAME %1, %2
994 %macro SWAP_INTERNAL_NUM 2-*
999 CAT_XDEFINE nn, m%1, %1
1000 CAT_XDEFINE nn, m%2, %2
1005 %macro SWAP_INTERNAL_NAME 2-*
1006 %xdefine %%args nn %+ %1
1008 %xdefine %%args %%args, nn %+ %2
1011 SWAP_INTERNAL_NUM %%args
1014 ; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
1015 ; calls to that function will automatically load the permutation, so values can
1016 ; be returned in mmregs.
1017 %macro SAVE_MM_PERMUTATION 0-1
1021 %xdefine %%f current_function %+ _m
1025 CAT_XDEFINE %%f, %%i, m %+ %%i
1030 %macro LOAD_MM_PERMUTATION 1 ; name to load from
1034 CAT_XDEFINE m, %%i, %1_m %+ %%i
1035 CAT_XDEFINE nn, m %+ %%i, %%i
1041 ; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't
1044 call_internal %1 %+ SUFFIX, %1
1049 %macro call_internal 2
1051 %ifndef cglobaled_%2
1057 LOAD_MM_PERMUTATION %%i
1060 ; Substitutions that reduce instruction size but are functionally equivalent
1085 ;=============================================================================
1086 ; AVX abstraction layer
1087 ;=============================================================================
1092 CAT_XDEFINE sizeofmm, i, 8
1094 CAT_XDEFINE sizeofxmm, i, 16
1095 CAT_XDEFINE sizeofymm, i, 32
1100 %macro CHECK_AVX_INSTR_EMU 3-*
1101 %xdefine %%opcode %1
1105 %error non-avx emulation of ``%%opcode'' is not supported
1112 ;%2 == minimal instruction set
1113 ;%3 == 1 if float, 0 if int
1114 ;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)
1115 ;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1117 %macro RUN_AVX_INSTR 6-9+
1119 %assign __sizeofreg sizeof%7
1121 %assign __sizeofreg sizeof%6
1123 %assign __sizeofreg mmsize
1125 %assign __emulate_avx 0
1126 %if avx_enabled && __sizeofreg >= 16
1127 %xdefine __instr v%1
1131 %assign __emulate_avx 1
1137 %error use of ``%1'' %2 instruction in cpuname function: current_function
1138 %elif cpuflags_%2 < cpuflags_sse && notcpuflag(sse2) && __sizeofreg > 8
1139 %error use of ``%1'' sse2 instruction in cpuname function: current_function
1153 ; 3-operand AVX instructions with a memory arg can only have it in src2,
1154 ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).
1155 ; So, if the instruction is commutative with a memory arg, swap them.
1163 CHECK_AVX_INSTR_EMU {%1 %6, %7, %8, %9}, %6, __src2, %9
1165 CHECK_AVX_INSTR_EMU {%1 %6, %7, %8}, %6, __src2
1167 %if __sizeofreg == 8
1181 __instr %6, %7, %8, %9
1192 ;%2 == minimal instruction set
1193 ;%3 == 1 if float, 0 if int
1194 ;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)
1195 ;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1196 %macro AVX_INSTR 1-5 fnord, 0, 255, 0
1197 %macro %1 1-10 fnord, fnord, fnord, fnord, %1, %2, %3, %4, %5
1199 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1
1201 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2
1203 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3
1205 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4
1207 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4, %5
1212 ; Instructions with both VEX and non-VEX encodings
1213 ; Non-destructive instructions are written without parameters
1214 AVX_INSTR addpd, sse2, 1, 0, 1
1215 AVX_INSTR addps, sse, 1, 0, 1
1216 AVX_INSTR addsd, sse2, 1, 0, 0
1217 AVX_INSTR addss, sse, 1, 0, 0
1218 AVX_INSTR addsubpd, sse3, 1, 0, 0
1219 AVX_INSTR addsubps, sse3, 1, 0, 0
1220 AVX_INSTR aesdec, aesni, 0, 0, 0
1221 AVX_INSTR aesdeclast, aesni, 0, 0, 0
1222 AVX_INSTR aesenc, aesni, 0, 0, 0
1223 AVX_INSTR aesenclast, aesni, 0, 0, 0
1224 AVX_INSTR aesimc, aesni
1225 AVX_INSTR aeskeygenassist, aesni
1226 AVX_INSTR andnpd, sse2, 1, 0, 0
1227 AVX_INSTR andnps, sse, 1, 0, 0
1228 AVX_INSTR andpd, sse2, 1, 0, 1
1229 AVX_INSTR andps, sse, 1, 0, 1
1230 AVX_INSTR blendpd, sse4, 1, 1, 0
1231 AVX_INSTR blendps, sse4, 1, 1, 0
1232 AVX_INSTR blendvpd, sse4 ; can't be emulated
1233 AVX_INSTR blendvps, sse4 ; can't be emulated
1234 AVX_INSTR cmppd, sse2, 1, 1, 0
1235 AVX_INSTR cmpps, sse, 1, 1, 0
1236 AVX_INSTR cmpsd, sse2, 1, 1, 0
1237 AVX_INSTR cmpss, sse, 1, 1, 0
1238 AVX_INSTR comisd, sse2
1239 AVX_INSTR comiss, sse
1240 AVX_INSTR cvtdq2pd, sse2
1241 AVX_INSTR cvtdq2ps, sse2
1242 AVX_INSTR cvtpd2dq, sse2
1243 AVX_INSTR cvtpd2ps, sse2
1244 AVX_INSTR cvtps2dq, sse2
1245 AVX_INSTR cvtps2pd, sse2
1246 AVX_INSTR cvtsd2si, sse2
1247 AVX_INSTR cvtsd2ss, sse2, 1, 0, 0
1248 AVX_INSTR cvtsi2sd, sse2, 1, 0, 0
1249 AVX_INSTR cvtsi2ss, sse, 1, 0, 0
1250 AVX_INSTR cvtss2sd, sse2, 1, 0, 0
1251 AVX_INSTR cvtss2si, sse
1252 AVX_INSTR cvttpd2dq, sse2
1253 AVX_INSTR cvttps2dq, sse2
1254 AVX_INSTR cvttsd2si, sse2
1255 AVX_INSTR cvttss2si, sse
1256 AVX_INSTR divpd, sse2, 1, 0, 0
1257 AVX_INSTR divps, sse, 1, 0, 0
1258 AVX_INSTR divsd, sse2, 1, 0, 0
1259 AVX_INSTR divss, sse, 1, 0, 0
1260 AVX_INSTR dppd, sse4, 1, 1, 0
1261 AVX_INSTR dpps, sse4, 1, 1, 0
1262 AVX_INSTR extractps, sse4
1263 AVX_INSTR haddpd, sse3, 1, 0, 0
1264 AVX_INSTR haddps, sse3, 1, 0, 0
1265 AVX_INSTR hsubpd, sse3, 1, 0, 0
1266 AVX_INSTR hsubps, sse3, 1, 0, 0
1267 AVX_INSTR insertps, sse4, 1, 1, 0
1268 AVX_INSTR lddqu, sse3
1269 AVX_INSTR ldmxcsr, sse
1270 AVX_INSTR maskmovdqu, sse2
1271 AVX_INSTR maxpd, sse2, 1, 0, 1
1272 AVX_INSTR maxps, sse, 1, 0, 1
1273 AVX_INSTR maxsd, sse2, 1, 0, 0
1274 AVX_INSTR maxss, sse, 1, 0, 0
1275 AVX_INSTR minpd, sse2, 1, 0, 1
1276 AVX_INSTR minps, sse, 1, 0, 1
1277 AVX_INSTR minsd, sse2, 1, 0, 0
1278 AVX_INSTR minss, sse, 1, 0, 0
1279 AVX_INSTR movapd, sse2
1280 AVX_INSTR movaps, sse
1282 AVX_INSTR movddup, sse3
1283 AVX_INSTR movdqa, sse2
1284 AVX_INSTR movdqu, sse2
1285 AVX_INSTR movhlps, sse, 1, 0, 0
1286 AVX_INSTR movhpd, sse2, 1, 0, 0
1287 AVX_INSTR movhps, sse, 1, 0, 0
1288 AVX_INSTR movlhps, sse, 1, 0, 0
1289 AVX_INSTR movlpd, sse2, 1, 0, 0
1290 AVX_INSTR movlps, sse, 1, 0, 0
1291 AVX_INSTR movmskpd, sse2
1292 AVX_INSTR movmskps, sse
1293 AVX_INSTR movntdq, sse2
1294 AVX_INSTR movntdqa, sse4
1295 AVX_INSTR movntpd, sse2
1296 AVX_INSTR movntps, sse
1298 AVX_INSTR movsd, sse2, 1, 0, 0
1299 AVX_INSTR movshdup, sse3
1300 AVX_INSTR movsldup, sse3
1301 AVX_INSTR movss, sse, 1, 0, 0
1302 AVX_INSTR movupd, sse2
1303 AVX_INSTR movups, sse
1304 AVX_INSTR mpsadbw, sse4, 0, 1, 0
1305 AVX_INSTR mulpd, sse2, 1, 0, 1
1306 AVX_INSTR mulps, sse, 1, 0, 1
1307 AVX_INSTR mulsd, sse2, 1, 0, 0
1308 AVX_INSTR mulss, sse, 1, 0, 0
1309 AVX_INSTR orpd, sse2, 1, 0, 1
1310 AVX_INSTR orps, sse, 1, 0, 1
1311 AVX_INSTR pabsb, ssse3
1312 AVX_INSTR pabsd, ssse3
1313 AVX_INSTR pabsw, ssse3
1314 AVX_INSTR packsswb, mmx, 0, 0, 0
1315 AVX_INSTR packssdw, mmx, 0, 0, 0
1316 AVX_INSTR packuswb, mmx, 0, 0, 0
1317 AVX_INSTR packusdw, sse4, 0, 0, 0
1318 AVX_INSTR paddb, mmx, 0, 0, 1
1319 AVX_INSTR paddw, mmx, 0, 0, 1
1320 AVX_INSTR paddd, mmx, 0, 0, 1
1321 AVX_INSTR paddq, sse2, 0, 0, 1
1322 AVX_INSTR paddsb, mmx, 0, 0, 1
1323 AVX_INSTR paddsw, mmx, 0, 0, 1
1324 AVX_INSTR paddusb, mmx, 0, 0, 1
1325 AVX_INSTR paddusw, mmx, 0, 0, 1
1326 AVX_INSTR palignr, ssse3, 0, 1, 0
1327 AVX_INSTR pand, mmx, 0, 0, 1
1328 AVX_INSTR pandn, mmx, 0, 0, 0
1329 AVX_INSTR pavgb, mmx2, 0, 0, 1
1330 AVX_INSTR pavgw, mmx2, 0, 0, 1
1331 AVX_INSTR pblendvb, sse4 ; can't be emulated
1332 AVX_INSTR pblendw, sse4, 0, 1, 0
1333 AVX_INSTR pclmulqdq, fnord, 0, 1, 0
1334 AVX_INSTR pclmulhqhqdq, fnord, 0, 0, 0
1335 AVX_INSTR pclmulhqlqdq, fnord, 0, 0, 0
1336 AVX_INSTR pclmullqhqdq, fnord, 0, 0, 0
1337 AVX_INSTR pclmullqlqdq, fnord, 0, 0, 0
1338 AVX_INSTR pcmpestri, sse42
1339 AVX_INSTR pcmpestrm, sse42
1340 AVX_INSTR pcmpistri, sse42
1341 AVX_INSTR pcmpistrm, sse42
1342 AVX_INSTR pcmpeqb, mmx, 0, 0, 1
1343 AVX_INSTR pcmpeqw, mmx, 0, 0, 1
1344 AVX_INSTR pcmpeqd, mmx, 0, 0, 1
1345 AVX_INSTR pcmpeqq, sse4, 0, 0, 1
1346 AVX_INSTR pcmpgtb, mmx, 0, 0, 0
1347 AVX_INSTR pcmpgtw, mmx, 0, 0, 0
1348 AVX_INSTR pcmpgtd, mmx, 0, 0, 0
1349 AVX_INSTR pcmpgtq, sse42, 0, 0, 0
1350 AVX_INSTR pextrb, sse4
1351 AVX_INSTR pextrd, sse4
1352 AVX_INSTR pextrq, sse4
1353 AVX_INSTR pextrw, mmx2
1354 AVX_INSTR phaddw, ssse3, 0, 0, 0
1355 AVX_INSTR phaddd, ssse3, 0, 0, 0
1356 AVX_INSTR phaddsw, ssse3, 0, 0, 0
1357 AVX_INSTR phminposuw, sse4
1358 AVX_INSTR phsubw, ssse3, 0, 0, 0
1359 AVX_INSTR phsubd, ssse3, 0, 0, 0
1360 AVX_INSTR phsubsw, ssse3, 0, 0, 0
1361 AVX_INSTR pinsrb, sse4, 0, 1, 0
1362 AVX_INSTR pinsrd, sse4, 0, 1, 0
1363 AVX_INSTR pinsrq, sse4, 0, 1, 0
1364 AVX_INSTR pinsrw, mmx2, 0, 1, 0
1365 AVX_INSTR pmaddwd, mmx, 0, 0, 1
1366 AVX_INSTR pmaddubsw, ssse3, 0, 0, 0
1367 AVX_INSTR pmaxsb, sse4, 0, 0, 1
1368 AVX_INSTR pmaxsw, mmx2, 0, 0, 1
1369 AVX_INSTR pmaxsd, sse4, 0, 0, 1
1370 AVX_INSTR pmaxub, mmx2, 0, 0, 1
1371 AVX_INSTR pmaxuw, sse4, 0, 0, 1
1372 AVX_INSTR pmaxud, sse4, 0, 0, 1
1373 AVX_INSTR pminsb, sse4, 0, 0, 1
1374 AVX_INSTR pminsw, mmx2, 0, 0, 1
1375 AVX_INSTR pminsd, sse4, 0, 0, 1
1376 AVX_INSTR pminub, mmx2, 0, 0, 1
1377 AVX_INSTR pminuw, sse4, 0, 0, 1
1378 AVX_INSTR pminud, sse4, 0, 0, 1
1379 AVX_INSTR pmovmskb, mmx2
1380 AVX_INSTR pmovsxbw, sse4
1381 AVX_INSTR pmovsxbd, sse4
1382 AVX_INSTR pmovsxbq, sse4
1383 AVX_INSTR pmovsxwd, sse4
1384 AVX_INSTR pmovsxwq, sse4
1385 AVX_INSTR pmovsxdq, sse4
1386 AVX_INSTR pmovzxbw, sse4
1387 AVX_INSTR pmovzxbd, sse4
1388 AVX_INSTR pmovzxbq, sse4
1389 AVX_INSTR pmovzxwd, sse4
1390 AVX_INSTR pmovzxwq, sse4
1391 AVX_INSTR pmovzxdq, sse4
1392 AVX_INSTR pmuldq, sse4, 0, 0, 1
1393 AVX_INSTR pmulhrsw, ssse3, 0, 0, 1
1394 AVX_INSTR pmulhuw, mmx2, 0, 0, 1
1395 AVX_INSTR pmulhw, mmx, 0, 0, 1
1396 AVX_INSTR pmullw, mmx, 0, 0, 1
1397 AVX_INSTR pmulld, sse4, 0, 0, 1
1398 AVX_INSTR pmuludq, sse2, 0, 0, 1
1399 AVX_INSTR por, mmx, 0, 0, 1
1400 AVX_INSTR psadbw, mmx2, 0, 0, 1
1401 AVX_INSTR pshufb, ssse3, 0, 0, 0
1402 AVX_INSTR pshufd, sse2
1403 AVX_INSTR pshufhw, sse2
1404 AVX_INSTR pshuflw, sse2
1405 AVX_INSTR psignb, ssse3, 0, 0, 0
1406 AVX_INSTR psignw, ssse3, 0, 0, 0
1407 AVX_INSTR psignd, ssse3, 0, 0, 0
1408 AVX_INSTR psllw, mmx, 0, 0, 0
1409 AVX_INSTR pslld, mmx, 0, 0, 0
1410 AVX_INSTR psllq, mmx, 0, 0, 0
1411 AVX_INSTR pslldq, sse2, 0, 0, 0
1412 AVX_INSTR psraw, mmx, 0, 0, 0
1413 AVX_INSTR psrad, mmx, 0, 0, 0
1414 AVX_INSTR psrlw, mmx, 0, 0, 0
1415 AVX_INSTR psrld, mmx, 0, 0, 0
1416 AVX_INSTR psrlq, mmx, 0, 0, 0
1417 AVX_INSTR psrldq, sse2, 0, 0, 0
1418 AVX_INSTR psubb, mmx, 0, 0, 0
1419 AVX_INSTR psubw, mmx, 0, 0, 0
1420 AVX_INSTR psubd, mmx, 0, 0, 0
1421 AVX_INSTR psubq, sse2, 0, 0, 0
1422 AVX_INSTR psubsb, mmx, 0, 0, 0
1423 AVX_INSTR psubsw, mmx, 0, 0, 0
1424 AVX_INSTR psubusb, mmx, 0, 0, 0
1425 AVX_INSTR psubusw, mmx, 0, 0, 0
1426 AVX_INSTR ptest, sse4
1427 AVX_INSTR punpckhbw, mmx, 0, 0, 0
1428 AVX_INSTR punpckhwd, mmx, 0, 0, 0
1429 AVX_INSTR punpckhdq, mmx, 0, 0, 0
1430 AVX_INSTR punpckhqdq, sse2, 0, 0, 0
1431 AVX_INSTR punpcklbw, mmx, 0, 0, 0
1432 AVX_INSTR punpcklwd, mmx, 0, 0, 0
1433 AVX_INSTR punpckldq, mmx, 0, 0, 0
1434 AVX_INSTR punpcklqdq, sse2, 0, 0, 0
1435 AVX_INSTR pxor, mmx, 0, 0, 1
1436 AVX_INSTR rcpps, sse
1437 AVX_INSTR rcpss, sse, 1, 0, 0
1438 AVX_INSTR roundpd, sse4
1439 AVX_INSTR roundps, sse4
1440 AVX_INSTR roundsd, sse4, 1, 1, 0
1441 AVX_INSTR roundss, sse4, 1, 1, 0
1442 AVX_INSTR rsqrtps, sse
1443 AVX_INSTR rsqrtss, sse, 1, 0, 0
1444 AVX_INSTR shufpd, sse2, 1, 1, 0
1445 AVX_INSTR shufps, sse, 1, 1, 0
1446 AVX_INSTR sqrtpd, sse2
1447 AVX_INSTR sqrtps, sse
1448 AVX_INSTR sqrtsd, sse2, 1, 0, 0
1449 AVX_INSTR sqrtss, sse, 1, 0, 0
1450 AVX_INSTR stmxcsr, sse
1451 AVX_INSTR subpd, sse2, 1, 0, 0
1452 AVX_INSTR subps, sse, 1, 0, 0
1453 AVX_INSTR subsd, sse2, 1, 0, 0
1454 AVX_INSTR subss, sse, 1, 0, 0
1455 AVX_INSTR ucomisd, sse2
1456 AVX_INSTR ucomiss, sse
1457 AVX_INSTR unpckhpd, sse2, 1, 0, 0
1458 AVX_INSTR unpckhps, sse, 1, 0, 0
1459 AVX_INSTR unpcklpd, sse2, 1, 0, 0
1460 AVX_INSTR unpcklps, sse, 1, 0, 0
1461 AVX_INSTR xorpd, sse2, 1, 0, 1
1462 AVX_INSTR xorps, sse, 1, 0, 1
1464 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN
1465 AVX_INSTR pfadd, 3dnow, 1, 0, 1
1466 AVX_INSTR pfsub, 3dnow, 1, 0, 0
1467 AVX_INSTR pfmul, 3dnow, 1, 0, 1
1469 ; base-4 constants for shuffles
1472 %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)
1474 CAT_XDEFINE q000, j, i
1476 CAT_XDEFINE q00, j, i
1478 CAT_XDEFINE q0, j, i
1488 %macro %1 4-7 %1, %2, %3
1495 %error non-xop emulation of ``%5 %1, %2, %3, %4'' is not supported
1500 FMA_INSTR pmacsww, pmullw, paddw
1501 FMA_INSTR pmacsdd, pmulld, paddd ; sse4 emulation
1502 FMA_INSTR pmacsdql, pmuldq, paddq ; sse4 emulation
1503 FMA_INSTR pmadcswd, pmaddwd, paddd
1505 ; tzcnt is equivalent to "rep bsf" and is backwards-compatible with bsf.
1506 ; This lets us use tzcnt without bumping the yasm version requirement yet.
1507 %define tzcnt rep bsf
1509 ; Macros for consolidating FMA3 and FMA4 using 4-operand (dst, src1, src2, src3) syntax.
1510 ; FMA3 is only possible if dst is the same as one of the src registers.
1511 ; Either src2 or src3 can be a memory operand.
1512 %macro FMA4_INSTR 2-*
1514 %xdefine %$prefix %1
1516 %macro %$prefix%2 4-6 %$prefix, %2
1517 %if notcpuflag(fma3) && notcpuflag(fma4)
1518 %error use of ``%5%6'' fma instruction in cpuname function: current_function
1520 v%5%6 %1, %2, %3, %4
1522 ; If %3 or %4 is a memory operand it needs to be encoded as the last operand.
1524 v%{5}213%6 %2, %3, %4
1526 v%{5}132%6 %2, %4, %3
1529 v%{5}213%6 %3, %2, %4
1531 v%{5}231%6 %4, %2, %3
1533 %error fma3 emulation of ``%5%6 %1, %2, %3, %4'' is not supported
1541 FMA4_INSTR fmadd, pd, ps, sd, ss
1542 FMA4_INSTR fmaddsub, pd, ps
1543 FMA4_INSTR fmsub, pd, ps, sd, ss
1544 FMA4_INSTR fmsubadd, pd, ps
1545 FMA4_INSTR fnmadd, pd, ps, sd, ss
1546 FMA4_INSTR fnmsub, pd, ps, sd, ss
1548 ; workaround: vpbroadcastq is broken in x86_32 due to a yasm bug (fixed in 1.3.0)
1550 %if __YASM_VERSION_ID__ < 0x01030000 && ARCH_X86_64 == 0
1551 %macro vpbroadcastq 2