1 ;*****************************************************************************
2 ;* x86inc.asm: x264asm abstraction layer
3 ;*****************************************************************************
4 ;* Copyright (C) 2005-2017 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Anton Mitrofanov <BugMaster@narod.ru>
8 ;* Fiona Glaser <fiona@x264.com>
9 ;* Henrik Gramner <henrik@gramner.com>
11 ;* Permission to use, copy, modify, and/or distribute this software for any
12 ;* purpose with or without fee is hereby granted, provided that the above
13 ;* copyright notice and this permission notice appear in all copies.
15 ;* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16 ;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17 ;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18 ;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19 ;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20 ;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21 ;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 ;*****************************************************************************
24 ; This is a header file for the x264ASM assembly language, which uses
25 ; NASM/YASM syntax combined with a large number of macros to provide easy
26 ; abstraction between different calling conventions (x86_32, win64, linux64).
27 ; It also has various other useful features to simplify writing the kind of
28 ; DSP functions that are most often used in x264.
30 ; Unlike the rest of x264, this file is available under an ISC license, as it
31 ; has significant usefulness outside of x264 and we want it to be available
32 ; to the largest audience possible. Of course, if you modify it for your own
33 ; purposes to add a new feature, we strongly encourage contributing a patch
34 ; as this feature might be useful for others as well. Send patches or ideas
35 ; to x264-devel@videolan.org .
37 %ifndef private_prefix
38 %define private_prefix x264
42 %define public_prefix private_prefix
45 %if HAVE_ALIGNED_STACK
46 %define STACK_ALIGNMENT 16
48 %ifndef STACK_ALIGNMENT
50 %define STACK_ALIGNMENT 16
52 %define STACK_ALIGNMENT 4
59 %ifidn __OUTPUT_FORMAT__,win32
61 %elifidn __OUTPUT_FORMAT__,win64
63 %elifidn __OUTPUT_FORMAT__,x64
71 %ifidn __OUTPUT_FORMAT__,elf
73 %elifidn __OUTPUT_FORMAT__,elf32
75 %elifidn __OUTPUT_FORMAT__,elf64
80 %define mangle(x) _ %+ x
85 ; aout does not support align=
86 ; NOTE: This section is out of sync with x264, in order to
87 ; keep supporting OS/2.
88 %macro SECTION_RODATA 0-1 16
89 %ifidn __OUTPUT_FORMAT__,aout
91 %elifidn __OUTPUT_FORMAT__,coff
94 SECTION .rodata align=%1
100 %elif ARCH_X86_64 == 0
101 ; x86_32 doesn't require PIC.
102 ; Some distros prefer shared objects to be PIC, but nothing breaks if
103 ; the code contains a few textrels, so we'll skip that complexity.
116 ; Macros to eliminate most code duplication between x86_32 and x86_64:
117 ; Currently this works only for leaf functions which load all their arguments
118 ; into registers at the start, and make no other use of the stack. Luckily that
119 ; covers most of x264's asm.
122 ; %1 = number of arguments. loads them from stack if needed.
123 ; %2 = number of registers used. pushes callee-saved regs if needed.
124 ; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.
125 ; %4 = (optional) stack size to be allocated. The stack will be aligned before
126 ; allocating the specified stack size. If the required stack alignment is
127 ; larger than the known stack alignment the stack will be manually aligned
128 ; and an extra register will be allocated to hold the original stack
129 ; pointer (to not invalidate r0m etc.). To prevent the use of an extra
130 ; register as stack pointer, request a negative stack size.
131 ; %4+/%5+ = list of names to define to registers
132 ; PROLOGUE can also be invoked by adding the same options to cglobal
135 ; cglobal foo, 2,3,7,0x40, dst, src, tmp
136 ; declares a function (foo) that automatically loads two arguments (dst and
137 ; src) into registers, uses one additional register (tmp) plus 7 vector
138 ; registers (m0-m6) and allocates 0x40 bytes of stack space.
140 ; TODO Some functions can use some args directly from the stack. If they're the
141 ; last args then you can just not declare them, but if they're in the middle
142 ; we need more flexible macro.
145 ; Pops anything that was pushed by PROLOGUE, and returns.
148 ; Use this instead of RET if it's a branch target.
151 ; rN and rNq are the native-size register holding function argument N
152 ; rNd, rNw, rNb are dword, word, and byte size
153 ; rNh is the high 8 bits of the word size
154 ; rNm is the original location of arg N (a register or on the stack), dword
155 ; rNmp is native size
157 %macro DECLARE_REG 2-3
167 %elif ARCH_X86_64 ; memory
168 %define r%1m [rstk + stack_offset + %3]
169 %define r%1mp qword r %+ %1 %+ m
171 %define r%1m [rstk + stack_offset + %3]
172 %define r%1mp dword r %+ %1 %+ m
177 %macro DECLARE_REG_SIZE 3
193 DECLARE_REG_SIZE ax, al, ah
194 DECLARE_REG_SIZE bx, bl, bh
195 DECLARE_REG_SIZE cx, cl, ch
196 DECLARE_REG_SIZE dx, dl, dh
197 DECLARE_REG_SIZE si, sil, null
198 DECLARE_REG_SIZE di, dil, null
199 DECLARE_REG_SIZE bp, bpl, null
201 ; t# defines for when per-arch register allocation is more complex than just function arguments
203 %macro DECLARE_REG_TMP 1-*
206 CAT_XDEFINE t, %%i, r%1
212 %macro DECLARE_REG_TMP_SIZE 0-*
214 %define t%1q t%1 %+ q
215 %define t%1d t%1 %+ d
216 %define t%1w t%1 %+ w
217 %define t%1h t%1 %+ h
218 %define t%1b t%1 %+ b
223 DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
234 %assign stack_offset stack_offset+gprsize
241 %assign stack_offset stack_offset-gprsize
245 %macro PUSH_IF_USED 1-*
254 %macro POP_IF_USED 1-*
263 %macro LOAD_IF_USED 1-*
266 mov r%1, r %+ %1 %+ mp
275 %assign stack_offset stack_offset+(%2)
282 %assign stack_offset stack_offset-(%2)
292 %macro movsxdifnidn 2
300 %error assertion ``%1'' failed
304 %macro DEFINE_ARGS 0-*
308 CAT_UNDEF arg_name %+ %%i, q
309 CAT_UNDEF arg_name %+ %%i, d
310 CAT_UNDEF arg_name %+ %%i, w
311 CAT_UNDEF arg_name %+ %%i, h
312 CAT_UNDEF arg_name %+ %%i, b
313 CAT_UNDEF arg_name %+ %%i, m
314 CAT_UNDEF arg_name %+ %%i, mp
315 CAT_UNDEF arg_name, %%i
320 %xdefine %%stack_offset stack_offset
321 %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine
324 %xdefine %1q r %+ %%i %+ q
325 %xdefine %1d r %+ %%i %+ d
326 %xdefine %1w r %+ %%i %+ w
327 %xdefine %1h r %+ %%i %+ h
328 %xdefine %1b r %+ %%i %+ b
329 %xdefine %1m r %+ %%i %+ m
330 %xdefine %1mp r %+ %%i %+ mp
331 CAT_XDEFINE arg_name, %%i, %1
335 %xdefine stack_offset %%stack_offset
336 %assign n_arg_names %0
339 %define required_stack_alignment ((mmsize + 15) & ~15)
340 %define vzeroupper_required (mmsize > 16 && (ARCH_X86_64 == 0 || xmm_regs_used > 16 || notcpuflag(avx512)))
341 %define high_mm_regs (16*cpuflag(avx512))
343 %macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)
347 %assign stack_size %1
349 %assign stack_size -stack_size
352 %assign %%pad %%pad + 32 ; shadow space
354 %assign xmm_regs_used %2
355 %if xmm_regs_used > 8
356 %assign %%pad %%pad + (xmm_regs_used-8)*16 ; callee-saved xmm registers
360 %if required_stack_alignment <= STACK_ALIGNMENT
361 ; maintain the current stack alignment
362 %assign stack_size_padded stack_size + %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
363 SUB rsp, stack_size_padded
365 %assign %%reg_num (regs_used - 1)
366 %xdefine rstk r %+ %%reg_num
367 ; align stack, and save original stack location directly above
368 ; it, i.e. in [rsp+stack_size_padded], so we can restore the
369 ; stack in a single instruction (i.e. mov rsp, rstk or mov
370 ; rsp, [rsp+stack_size_padded])
371 %if %1 < 0 ; need to store rsp on stack
372 %xdefine rstkm [rsp + stack_size + %%pad]
373 %assign %%pad %%pad + gprsize
374 %else ; can keep rsp in rstk during whole function
377 %assign stack_size_padded stack_size + ((%%pad + required_stack_alignment-1) & ~(required_stack_alignment-1))
379 and rsp, ~(required_stack_alignment-1)
380 sub rsp, stack_size_padded
381 movifnidn rstkm, rstk
388 %macro SETUP_STACK_POINTER 1
390 %if %1 != 0 && required_stack_alignment > STACK_ALIGNMENT
392 ; Reserve an additional register for storing the original stack pointer, but avoid using
393 ; eax/rax for this purpose since it can potentially get overwritten as a return value.
394 %assign regs_used (regs_used + 1)
395 %if ARCH_X86_64 && regs_used == 7
397 %elif ARCH_X86_64 == 0 && regs_used == 1
401 %if ARCH_X86_64 && regs_used < 5 + UNIX64 * 3
402 ; Ensure that we don't clobber any registers containing arguments. For UNIX64 we also preserve r6 (rax)
403 ; since it's used as a hidden argument in vararg functions to specify the number of vector registers used.
404 %assign regs_used 5 + UNIX64 * 3
410 %macro DEFINE_ARGS_INTERNAL 3+
420 %if WIN64 ; Windows x64 ;=================================================
426 DECLARE_REG 4, R10, 40
427 DECLARE_REG 5, R11, 48
428 DECLARE_REG 6, rax, 56
429 DECLARE_REG 7, rdi, 64
430 DECLARE_REG 8, rsi, 72
431 DECLARE_REG 9, rbx, 80
432 DECLARE_REG 10, rbp, 88
433 DECLARE_REG 11, R14, 96
434 DECLARE_REG 12, R15, 104
435 DECLARE_REG 13, R12, 112
436 DECLARE_REG 14, R13, 120
438 %macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
441 ASSERT regs_used >= num_args
442 SETUP_STACK_POINTER %4
443 ASSERT regs_used <= 15
444 PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14
446 %if mmsize != 8 && stack_size == 0
449 LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
450 DEFINE_ARGS_INTERNAL %0, %4, %5
453 %macro WIN64_PUSH_XMM 0
454 ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.
455 %if xmm_regs_used > 6 + high_mm_regs
456 movaps [rstk + stack_offset + 8], xmm6
458 %if xmm_regs_used > 7 + high_mm_regs
459 movaps [rstk + stack_offset + 24], xmm7
461 %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8
462 %if %%xmm_regs_on_stack > 0
464 %rep %%xmm_regs_on_stack
465 movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i
471 %macro WIN64_SPILL_XMM 1
472 %assign xmm_regs_used %1
473 ASSERT xmm_regs_used <= 16 + high_mm_regs
474 %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8
475 %if %%xmm_regs_on_stack > 0
476 ; Allocate stack space for callee-saved xmm registers plus shadow space and align the stack.
477 %assign %%pad %%xmm_regs_on_stack*16 + 32
478 %assign stack_size_padded %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
479 SUB rsp, stack_size_padded
484 %macro WIN64_RESTORE_XMM_INTERNAL 0
486 %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8
487 %if %%xmm_regs_on_stack > 0
488 %assign %%i xmm_regs_used - high_mm_regs
489 %rep %%xmm_regs_on_stack
491 movaps xmm %+ %%i, [rsp + (%%i-8)*16 + stack_size + 32]
494 %if stack_size_padded > 0
495 %if stack_size > 0 && required_stack_alignment > STACK_ALIGNMENT
498 add rsp, stack_size_padded
499 %assign %%pad_size stack_size_padded
502 %if xmm_regs_used > 7 + high_mm_regs
503 movaps xmm7, [rsp + stack_offset - %%pad_size + 24]
505 %if xmm_regs_used > 6 + high_mm_regs
506 movaps xmm6, [rsp + stack_offset - %%pad_size + 8]
510 %macro WIN64_RESTORE_XMM 0
511 WIN64_RESTORE_XMM_INTERNAL
512 %assign stack_offset (stack_offset-stack_size_padded)
513 %assign stack_size_padded 0
514 %assign xmm_regs_used 0
517 %define has_epilogue regs_used > 7 || stack_size > 0 || vzeroupper_required || xmm_regs_used > 6+high_mm_regs
520 WIN64_RESTORE_XMM_INTERNAL
521 POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7
522 %if vzeroupper_required
528 %elif ARCH_X86_64 ; *nix x64 ;=============================================
536 DECLARE_REG 6, rax, 8
537 DECLARE_REG 7, R10, 16
538 DECLARE_REG 8, R11, 24
539 DECLARE_REG 9, rbx, 32
540 DECLARE_REG 10, rbp, 40
541 DECLARE_REG 11, R14, 48
542 DECLARE_REG 12, R15, 56
543 DECLARE_REG 13, R12, 64
544 DECLARE_REG 14, R13, 72
546 %macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
549 %assign xmm_regs_used %3
550 ASSERT regs_used >= num_args
551 SETUP_STACK_POINTER %4
552 ASSERT regs_used <= 15
553 PUSH_IF_USED 9, 10, 11, 12, 13, 14
555 LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14
556 DEFINE_ARGS_INTERNAL %0, %4, %5
559 %define has_epilogue regs_used > 9 || stack_size > 0 || vzeroupper_required
562 %if stack_size_padded > 0
563 %if required_stack_alignment > STACK_ALIGNMENT
566 add rsp, stack_size_padded
569 POP_IF_USED 14, 13, 12, 11, 10, 9
570 %if vzeroupper_required
576 %else ; X86_32 ;==============================================================
578 DECLARE_REG 0, eax, 4
579 DECLARE_REG 1, ecx, 8
580 DECLARE_REG 2, edx, 12
581 DECLARE_REG 3, ebx, 16
582 DECLARE_REG 4, esi, 20
583 DECLARE_REG 5, edi, 24
584 DECLARE_REG 6, ebp, 28
587 %macro DECLARE_ARG 1-*
589 %define r%1m [rstk + stack_offset + 4*%1 + 4]
590 %define r%1mp dword r%1m
595 DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
597 %macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
600 ASSERT regs_used >= num_args
607 SETUP_STACK_POINTER %4
608 ASSERT regs_used <= 7
609 PUSH_IF_USED 3, 4, 5, 6
611 LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6
612 DEFINE_ARGS_INTERNAL %0, %4, %5
615 %define has_epilogue regs_used > 3 || stack_size > 0 || vzeroupper_required
618 %if stack_size_padded > 0
619 %if required_stack_alignment > STACK_ALIGNMENT
622 add rsp, stack_size_padded
625 POP_IF_USED 6, 5, 4, 3
626 %if vzeroupper_required
632 %endif ;======================================================================
635 %macro WIN64_SPILL_XMM 1
637 %macro WIN64_RESTORE_XMM 0
639 %macro WIN64_PUSH_XMM 0
643 ; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either
644 ; a branch or a branch target. So switch to a 2-byte form of ret in that case.
645 ; We can automatically detect "follows a branch", but not a branch target.
646 ; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)
648 %if has_epilogue || cpuflag(ssse3)
653 annotate_function_size
656 %define last_branch_adr $$
657 %macro AUTO_REP_RET 0
658 %if notcpuflag(ssse3)
659 times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ == last_branch_adr.
662 annotate_function_size
665 %macro BRANCH_INSTR 0-*
669 %if notcpuflag(ssse3)
671 %xdefine last_branch_adr %%branch_instr
678 BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp
680 %macro TAIL_CALL 2 ; callee, is_nonadjacent
687 annotate_function_size
690 ;=============================================================================
691 ; arch-independent part
692 ;=============================================================================
694 %assign function_align 16
697 ; Applies any symbol mangling needed for C linkage, and sets up a define such that
698 ; subsequent uses of the function name automatically refer to the mangled version.
699 ; Appends cpuflags to the function name if cpuflags has been specified.
700 ; The "" empty default parameter is a workaround for nasm, which fails if SUFFIX
701 ; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).
702 %macro cglobal 1-2+ "" ; name, [PROLOGUE args]
703 cglobal_internal 1, %1 %+ SUFFIX, %2
705 %macro cvisible 1-2+ "" ; name, [PROLOGUE args]
706 cglobal_internal 0, %1 %+ SUFFIX, %2
708 %macro cglobal_internal 2-3+
709 annotate_function_size
711 %xdefine %%FUNCTION_PREFIX private_prefix
712 %xdefine %%VISIBILITY hidden
714 %xdefine %%FUNCTION_PREFIX public_prefix
715 %xdefine %%VISIBILITY
718 %xdefine %2 mangle(%%FUNCTION_PREFIX %+ _ %+ %2)
719 %xdefine %2.skip_prologue %2 %+ .skip_prologue
720 CAT_XDEFINE cglobaled_, %2, 1
722 %xdefine current_function %2
723 %xdefine current_function_section __SECT__
725 global %2:function %%VISIBILITY
731 RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer
732 %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required
733 %assign stack_offset 0 ; stack pointer offset relative to the return address
734 %assign stack_size 0 ; amount of stack space that can be freely used inside a function
735 %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding
736 %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64 and vzeroupper
743 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
744 CAT_XDEFINE cglobaled_, %1, 1
748 ; like cextern, but without the prefix
749 %macro cextern_naked 1
751 %xdefine %1 mangle(%1)
753 CAT_XDEFINE cglobaled_, %1, 1
758 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
760 global %1:data hidden
767 ; This is needed for ELF, otherwise the GNU linker assumes the stack is executable by default.
769 [SECTION .note.GNU-stack noalloc noexec nowrite progbits]
772 ; Tell debuggers how large the function was.
773 ; This may be invoked multiple times per function; we rely on later instances overriding earlier ones.
774 ; This is invoked by RET and similar macros, and also cglobal does it for the previous function,
775 ; but if the last function in a source file doesn't use any of the standard macros for its epilogue,
776 ; then its size might be unspecified.
777 %macro annotate_function_size 0
779 %ifdef current_function
781 current_function_section
783 size current_function %%ecf - current_function
792 %assign cpuflags_mmx (1<<0)
793 %assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
794 %assign cpuflags_3dnow (1<<2) | cpuflags_mmx
795 %assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow
796 %assign cpuflags_sse (1<<4) | cpuflags_mmx2
797 %assign cpuflags_sse2 (1<<5) | cpuflags_sse
798 %assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
799 %assign cpuflags_lzcnt (1<<7) | cpuflags_sse2
800 %assign cpuflags_sse3 (1<<8) | cpuflags_sse2
801 %assign cpuflags_ssse3 (1<<9) | cpuflags_sse3
802 %assign cpuflags_sse4 (1<<10)| cpuflags_ssse3
803 %assign cpuflags_sse42 (1<<11)| cpuflags_sse4
804 %assign cpuflags_aesni (1<<12)| cpuflags_sse42
805 %assign cpuflags_avx (1<<13)| cpuflags_sse42
806 %assign cpuflags_xop (1<<14)| cpuflags_avx
807 %assign cpuflags_fma4 (1<<15)| cpuflags_avx
808 %assign cpuflags_fma3 (1<<16)| cpuflags_avx
809 %assign cpuflags_bmi1 (1<<17)| cpuflags_avx|cpuflags_lzcnt
810 %assign cpuflags_bmi2 (1<<18)| cpuflags_bmi1
811 %assign cpuflags_avx2 (1<<19)| cpuflags_fma3|cpuflags_bmi2
812 %assign cpuflags_avx512 (1<<20)| cpuflags_avx2 ; F, CD, BW, DQ, VL
814 %assign cpuflags_cache32 (1<<21)
815 %assign cpuflags_cache64 (1<<22)
816 %assign cpuflags_slowctz (1<<23)
817 %assign cpuflags_aligned (1<<24) ; not a cpu feature, but a function variant
818 %assign cpuflags_atom (1<<25)
820 ; Returns a boolean value expressing whether or not the specified cpuflag is enabled.
821 %define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1)
822 %define notcpuflag(x) (cpuflag(x) ^ 1)
824 ; Takes an arbitrary number of cpuflags from the above list.
825 ; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.
826 ; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.
827 %macro INIT_CPUFLAGS 0-*
835 %xdefine cpuname cpuname %+ _%1
839 %assign cpuflags cpuflags | cpuflags_%1
842 %xdefine SUFFIX _ %+ cpuname
845 %assign avx_enabled 1
847 %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))
850 %define movnta movntps
854 %elif cpuflag(sse3) && notcpuflag(ssse3)
859 %if ARCH_X86_64 || cpuflag(sse2)
866 ; Merge mmx, sse*, and avx*
867 ; m# is a simd register of the currently selected size
868 ; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#
869 ; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#
870 ; zm# is the corresponding zmm register if mmsize >= 64, otherwise the same as m#
871 ; (All 4 remain in sync through SWAP.)
881 ; Prefer registers 16-31 over 0-15 to avoid having to use vzeroupper
882 %macro AVX512_MM_PERMUTATION 0-1 0 ; start_reg
883 %if ARCH_X86_64 && cpuflag(avx512)
886 %assign %%i_high %%i+16
894 %assign avx_enabled 0
895 %define RESET_MM_PERMUTATION INIT_MMX %1
901 %define movnta movntq
904 CAT_XDEFINE m, %%i, mm %+ %%i
905 CAT_XDEFINE nnmm, %%i, %%i
917 %assign avx_enabled 0
918 %define RESET_MM_PERMUTATION INIT_XMM %1
922 %define num_mmregs 32
927 %define movnta movntdq
930 CAT_XDEFINE m, %%i, xmm %+ %%i
931 CAT_XDEFINE nnxmm, %%i, %%i
936 ; Swap callee-saved registers with volatile registers
937 AVX512_MM_PERMUTATION 6
942 %assign avx_enabled 1
943 %define RESET_MM_PERMUTATION INIT_YMM %1
947 %define num_mmregs 32
952 %define movnta movntdq
955 CAT_XDEFINE m, %%i, ymm %+ %%i
956 CAT_XDEFINE nnymm, %%i, %%i
960 AVX512_MM_PERMUTATION
964 %assign avx_enabled 1
965 %define RESET_MM_PERMUTATION INIT_ZMM %1
969 %define num_mmregs 32
974 %define movnta movntdq
977 CAT_XDEFINE m, %%i, zmm %+ %%i
978 CAT_XDEFINE nnzmm, %%i, %%i
982 AVX512_MM_PERMUTATION
987 %macro DECLARE_MMCAST 1
993 %define xmmxmm%1 xmm%1
994 %define xmmymm%1 xmm%1
995 %define xmmzmm%1 xmm%1
997 %define ymmxmm%1 xmm%1
998 %define ymmymm%1 ymm%1
999 %define ymmzmm%1 ymm%1
1000 %define zmmmm%1 mm%1
1001 %define zmmxmm%1 xmm%1
1002 %define zmmymm%1 ymm%1
1003 %define zmmzmm%1 zmm%1
1004 %define xm%1 xmm %+ m%1
1005 %define ym%1 ymm %+ m%1
1006 %define zm%1 zmm %+ m%1
1015 ; I often want to use macros that permute their arguments. e.g. there's no
1016 ; efficient way to implement butterfly or transpose or dct without swapping some
1019 ; I would like to not have to manually keep track of the permutations:
1020 ; If I insert a permutation in the middle of a function, it should automatically
1021 ; change everything that follows. For more complex macros I may also have multiple
1022 ; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.
1024 ; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that
1025 ; permutes its arguments. It's equivalent to exchanging the contents of the
1026 ; registers, except that this way you exchange the register names instead, so it
1027 ; doesn't cost any cycles.
1029 %macro PERMUTE 2-* ; takes a list of pairs to swap
1031 %xdefine %%tmp%2 m%2
1035 %xdefine m%1 %%tmp%2
1036 CAT_XDEFINE nn, m%1, %1
1041 %macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)
1042 %ifnum %1 ; SWAP 0, 1, ...
1043 SWAP_INTERNAL_NUM %1, %2
1044 %else ; SWAP m0, m1, ...
1045 SWAP_INTERNAL_NAME %1, %2
1049 %macro SWAP_INTERNAL_NUM 2-*
1054 CAT_XDEFINE nn, m%1, %1
1055 CAT_XDEFINE nn, m%2, %2
1060 %macro SWAP_INTERNAL_NAME 2-*
1061 %xdefine %%args nn %+ %1
1063 %xdefine %%args %%args, nn %+ %2
1066 SWAP_INTERNAL_NUM %%args
1069 ; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
1070 ; calls to that function will automatically load the permutation, so values can
1071 ; be returned in mmregs.
1072 %macro SAVE_MM_PERMUTATION 0-1
1076 %xdefine %%f current_function %+ _m
1080 CAT_XDEFINE %%f, %%i, m %+ %%i
1085 %macro LOAD_MM_PERMUTATION 1 ; name to load from
1089 CAT_XDEFINE m, %%i, %1_m %+ %%i
1090 CAT_XDEFINE nn, m %+ %%i, %%i
1096 ; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't
1099 call_internal %1 %+ SUFFIX, %1
1104 %macro call_internal 2
1106 %ifndef cglobaled_%2
1112 LOAD_MM_PERMUTATION %%i
1115 ; Substitutions that reduce instruction size but are functionally equivalent
1140 ;=============================================================================
1141 ; AVX abstraction layer
1142 ;=============================================================================
1147 CAT_XDEFINE sizeofmm, i, 8
1148 CAT_XDEFINE regnumofmm, i, i
1150 CAT_XDEFINE sizeofxmm, i, 16
1151 CAT_XDEFINE sizeofymm, i, 32
1152 CAT_XDEFINE sizeofzmm, i, 64
1153 CAT_XDEFINE regnumofxmm, i, i
1154 CAT_XDEFINE regnumofymm, i, i
1155 CAT_XDEFINE regnumofzmm, i, i
1160 %macro CHECK_AVX_INSTR_EMU 3-*
1161 %xdefine %%opcode %1
1165 %error non-avx emulation of ``%%opcode'' is not supported
1172 ;%2 == minimal instruction set
1173 ;%3 == 1 if float, 0 if int
1174 ;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)
1175 ;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1177 %macro RUN_AVX_INSTR 6-9+
1179 %assign __sizeofreg sizeof%7
1181 %assign __sizeofreg sizeof%6
1183 %assign __sizeofreg mmsize
1185 %assign __emulate_avx 0
1186 %if avx_enabled && __sizeofreg >= 16
1187 %xdefine __instr v%1
1191 %assign __emulate_avx 1
1197 %error use of ``%1'' %2 instruction in cpuname function: current_function
1198 %elif cpuflags_%2 < cpuflags_sse && notcpuflag(sse2) && __sizeofreg > 8
1199 %error use of ``%1'' sse2 instruction in cpuname function: current_function
1213 ; 3-operand AVX instructions with a memory arg can only have it in src2,
1214 ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).
1215 ; So, if the instruction is commutative with a memory arg, swap them.
1223 CHECK_AVX_INSTR_EMU {%1 %6, %7, %8, %9}, %6, __src2, %9
1225 CHECK_AVX_INSTR_EMU {%1 %6, %7, %8}, %6, __src2
1227 %if __sizeofreg == 8
1241 __instr %6, %7, %8, %9
1252 ;%2 == minimal instruction set
1253 ;%3 == 1 if float, 0 if int
1254 ;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)
1255 ;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1256 %macro AVX_INSTR 1-5 fnord, 0, 255, 0
1257 %macro %1 1-10 fnord, fnord, fnord, fnord, %1, %2, %3, %4, %5
1259 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1
1261 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2
1263 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3
1265 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4
1267 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4, %5
1272 ; Instructions with both VEX/EVEX and legacy encodings
1273 ; Non-destructive instructions are written without parameters
1274 AVX_INSTR addpd, sse2, 1, 0, 1
1275 AVX_INSTR addps, sse, 1, 0, 1
1276 AVX_INSTR addsd, sse2, 1, 0, 0
1277 AVX_INSTR addss, sse, 1, 0, 0
1278 AVX_INSTR addsubpd, sse3, 1, 0, 0
1279 AVX_INSTR addsubps, sse3, 1, 0, 0
1280 AVX_INSTR aesdec, aesni, 0, 0, 0
1281 AVX_INSTR aesdeclast, aesni, 0, 0, 0
1282 AVX_INSTR aesenc, aesni, 0, 0, 0
1283 AVX_INSTR aesenclast, aesni, 0, 0, 0
1284 AVX_INSTR aesimc, aesni
1285 AVX_INSTR aeskeygenassist, aesni
1286 AVX_INSTR andnpd, sse2, 1, 0, 0
1287 AVX_INSTR andnps, sse, 1, 0, 0
1288 AVX_INSTR andpd, sse2, 1, 0, 1
1289 AVX_INSTR andps, sse, 1, 0, 1
1290 AVX_INSTR blendpd, sse4, 1, 1, 0
1291 AVX_INSTR blendps, sse4, 1, 1, 0
1292 AVX_INSTR blendvpd, sse4 ; can't be emulated
1293 AVX_INSTR blendvps, sse4 ; can't be emulated
1294 AVX_INSTR cmppd, sse2, 1, 1, 0
1295 AVX_INSTR cmpps, sse, 1, 1, 0
1296 AVX_INSTR cmpsd, sse2, 1, 1, 0
1297 AVX_INSTR cmpss, sse, 1, 1, 0
1298 AVX_INSTR comisd, sse2
1299 AVX_INSTR comiss, sse
1300 AVX_INSTR cvtdq2pd, sse2
1301 AVX_INSTR cvtdq2ps, sse2
1302 AVX_INSTR cvtpd2dq, sse2
1303 AVX_INSTR cvtpd2ps, sse2
1304 AVX_INSTR cvtps2dq, sse2
1305 AVX_INSTR cvtps2pd, sse2
1306 AVX_INSTR cvtsd2si, sse2
1307 AVX_INSTR cvtsd2ss, sse2, 1, 0, 0
1308 AVX_INSTR cvtsi2sd, sse2, 1, 0, 0
1309 AVX_INSTR cvtsi2ss, sse, 1, 0, 0
1310 AVX_INSTR cvtss2sd, sse2, 1, 0, 0
1311 AVX_INSTR cvtss2si, sse
1312 AVX_INSTR cvttpd2dq, sse2
1313 AVX_INSTR cvttps2dq, sse2
1314 AVX_INSTR cvttsd2si, sse2
1315 AVX_INSTR cvttss2si, sse
1316 AVX_INSTR divpd, sse2, 1, 0, 0
1317 AVX_INSTR divps, sse, 1, 0, 0
1318 AVX_INSTR divsd, sse2, 1, 0, 0
1319 AVX_INSTR divss, sse, 1, 0, 0
1320 AVX_INSTR dppd, sse4, 1, 1, 0
1321 AVX_INSTR dpps, sse4, 1, 1, 0
1322 AVX_INSTR extractps, sse4
1323 AVX_INSTR haddpd, sse3, 1, 0, 0
1324 AVX_INSTR haddps, sse3, 1, 0, 0
1325 AVX_INSTR hsubpd, sse3, 1, 0, 0
1326 AVX_INSTR hsubps, sse3, 1, 0, 0
1327 AVX_INSTR insertps, sse4, 1, 1, 0
1328 AVX_INSTR lddqu, sse3
1329 AVX_INSTR ldmxcsr, sse
1330 AVX_INSTR maskmovdqu, sse2
1331 AVX_INSTR maxpd, sse2, 1, 0, 1
1332 AVX_INSTR maxps, sse, 1, 0, 1
1333 AVX_INSTR maxsd, sse2, 1, 0, 0
1334 AVX_INSTR maxss, sse, 1, 0, 0
1335 AVX_INSTR minpd, sse2, 1, 0, 1
1336 AVX_INSTR minps, sse, 1, 0, 1
1337 AVX_INSTR minsd, sse2, 1, 0, 0
1338 AVX_INSTR minss, sse, 1, 0, 0
1339 AVX_INSTR movapd, sse2
1340 AVX_INSTR movaps, sse
1342 AVX_INSTR movddup, sse3
1343 AVX_INSTR movdqa, sse2
1344 AVX_INSTR movdqu, sse2
1345 AVX_INSTR movhlps, sse, 1, 0, 0
1346 AVX_INSTR movhpd, sse2, 1, 0, 0
1347 AVX_INSTR movhps, sse, 1, 0, 0
1348 AVX_INSTR movlhps, sse, 1, 0, 0
1349 AVX_INSTR movlpd, sse2, 1, 0, 0
1350 AVX_INSTR movlps, sse, 1, 0, 0
1351 AVX_INSTR movmskpd, sse2
1352 AVX_INSTR movmskps, sse
1353 AVX_INSTR movntdq, sse2
1354 AVX_INSTR movntdqa, sse4
1355 AVX_INSTR movntpd, sse2
1356 AVX_INSTR movntps, sse
1358 AVX_INSTR movsd, sse2, 1, 0, 0
1359 AVX_INSTR movshdup, sse3
1360 AVX_INSTR movsldup, sse3
1361 AVX_INSTR movss, sse, 1, 0, 0
1362 AVX_INSTR movupd, sse2
1363 AVX_INSTR movups, sse
1364 AVX_INSTR mpsadbw, sse4, 0, 1, 0
1365 AVX_INSTR mulpd, sse2, 1, 0, 1
1366 AVX_INSTR mulps, sse, 1, 0, 1
1367 AVX_INSTR mulsd, sse2, 1, 0, 0
1368 AVX_INSTR mulss, sse, 1, 0, 0
1369 AVX_INSTR orpd, sse2, 1, 0, 1
1370 AVX_INSTR orps, sse, 1, 0, 1
1371 AVX_INSTR pabsb, ssse3
1372 AVX_INSTR pabsd, ssse3
1373 AVX_INSTR pabsw, ssse3
1374 AVX_INSTR packsswb, mmx, 0, 0, 0
1375 AVX_INSTR packssdw, mmx, 0, 0, 0
1376 AVX_INSTR packuswb, mmx, 0, 0, 0
1377 AVX_INSTR packusdw, sse4, 0, 0, 0
1378 AVX_INSTR paddb, mmx, 0, 0, 1
1379 AVX_INSTR paddw, mmx, 0, 0, 1
1380 AVX_INSTR paddd, mmx, 0, 0, 1
1381 AVX_INSTR paddq, sse2, 0, 0, 1
1382 AVX_INSTR paddsb, mmx, 0, 0, 1
1383 AVX_INSTR paddsw, mmx, 0, 0, 1
1384 AVX_INSTR paddusb, mmx, 0, 0, 1
1385 AVX_INSTR paddusw, mmx, 0, 0, 1
1386 AVX_INSTR palignr, ssse3, 0, 1, 0
1387 AVX_INSTR pand, mmx, 0, 0, 1
1388 AVX_INSTR pandn, mmx, 0, 0, 0
1389 AVX_INSTR pavgb, mmx2, 0, 0, 1
1390 AVX_INSTR pavgw, mmx2, 0, 0, 1
1391 AVX_INSTR pblendvb, sse4 ; can't be emulated
1392 AVX_INSTR pblendw, sse4, 0, 1, 0
1393 AVX_INSTR pclmulqdq, fnord, 0, 1, 0
1394 AVX_INSTR pclmulhqhqdq, fnord, 0, 0, 0
1395 AVX_INSTR pclmulhqlqdq, fnord, 0, 0, 0
1396 AVX_INSTR pclmullqhqdq, fnord, 0, 0, 0
1397 AVX_INSTR pclmullqlqdq, fnord, 0, 0, 0
1398 AVX_INSTR pcmpestri, sse42
1399 AVX_INSTR pcmpestrm, sse42
1400 AVX_INSTR pcmpistri, sse42
1401 AVX_INSTR pcmpistrm, sse42
1402 AVX_INSTR pcmpeqb, mmx, 0, 0, 1
1403 AVX_INSTR pcmpeqw, mmx, 0, 0, 1
1404 AVX_INSTR pcmpeqd, mmx, 0, 0, 1
1405 AVX_INSTR pcmpeqq, sse4, 0, 0, 1
1406 AVX_INSTR pcmpgtb, mmx, 0, 0, 0
1407 AVX_INSTR pcmpgtw, mmx, 0, 0, 0
1408 AVX_INSTR pcmpgtd, mmx, 0, 0, 0
1409 AVX_INSTR pcmpgtq, sse42, 0, 0, 0
1410 AVX_INSTR pextrb, sse4
1411 AVX_INSTR pextrd, sse4
1412 AVX_INSTR pextrq, sse4
1413 AVX_INSTR pextrw, mmx2
1414 AVX_INSTR phaddw, ssse3, 0, 0, 0
1415 AVX_INSTR phaddd, ssse3, 0, 0, 0
1416 AVX_INSTR phaddsw, ssse3, 0, 0, 0
1417 AVX_INSTR phminposuw, sse4
1418 AVX_INSTR phsubw, ssse3, 0, 0, 0
1419 AVX_INSTR phsubd, ssse3, 0, 0, 0
1420 AVX_INSTR phsubsw, ssse3, 0, 0, 0
1421 AVX_INSTR pinsrb, sse4, 0, 1, 0
1422 AVX_INSTR pinsrd, sse4, 0, 1, 0
1423 AVX_INSTR pinsrq, sse4, 0, 1, 0
1424 AVX_INSTR pinsrw, mmx2, 0, 1, 0
1425 AVX_INSTR pmaddwd, mmx, 0, 0, 1
1426 AVX_INSTR pmaddubsw, ssse3, 0, 0, 0
1427 AVX_INSTR pmaxsb, sse4, 0, 0, 1
1428 AVX_INSTR pmaxsw, mmx2, 0, 0, 1
1429 AVX_INSTR pmaxsd, sse4, 0, 0, 1
1430 AVX_INSTR pmaxub, mmx2, 0, 0, 1
1431 AVX_INSTR pmaxuw, sse4, 0, 0, 1
1432 AVX_INSTR pmaxud, sse4, 0, 0, 1
1433 AVX_INSTR pminsb, sse4, 0, 0, 1
1434 AVX_INSTR pminsw, mmx2, 0, 0, 1
1435 AVX_INSTR pminsd, sse4, 0, 0, 1
1436 AVX_INSTR pminub, mmx2, 0, 0, 1
1437 AVX_INSTR pminuw, sse4, 0, 0, 1
1438 AVX_INSTR pminud, sse4, 0, 0, 1
1439 AVX_INSTR pmovmskb, mmx2
1440 AVX_INSTR pmovsxbw, sse4
1441 AVX_INSTR pmovsxbd, sse4
1442 AVX_INSTR pmovsxbq, sse4
1443 AVX_INSTR pmovsxwd, sse4
1444 AVX_INSTR pmovsxwq, sse4
1445 AVX_INSTR pmovsxdq, sse4
1446 AVX_INSTR pmovzxbw, sse4
1447 AVX_INSTR pmovzxbd, sse4
1448 AVX_INSTR pmovzxbq, sse4
1449 AVX_INSTR pmovzxwd, sse4
1450 AVX_INSTR pmovzxwq, sse4
1451 AVX_INSTR pmovzxdq, sse4
1452 AVX_INSTR pmuldq, sse4, 0, 0, 1
1453 AVX_INSTR pmulhrsw, ssse3, 0, 0, 1
1454 AVX_INSTR pmulhuw, mmx2, 0, 0, 1
1455 AVX_INSTR pmulhw, mmx, 0, 0, 1
1456 AVX_INSTR pmullw, mmx, 0, 0, 1
1457 AVX_INSTR pmulld, sse4, 0, 0, 1
1458 AVX_INSTR pmuludq, sse2, 0, 0, 1
1459 AVX_INSTR por, mmx, 0, 0, 1
1460 AVX_INSTR psadbw, mmx2, 0, 0, 1
1461 AVX_INSTR pshufb, ssse3, 0, 0, 0
1462 AVX_INSTR pshufd, sse2
1463 AVX_INSTR pshufhw, sse2
1464 AVX_INSTR pshuflw, sse2
1465 AVX_INSTR psignb, ssse3, 0, 0, 0
1466 AVX_INSTR psignw, ssse3, 0, 0, 0
1467 AVX_INSTR psignd, ssse3, 0, 0, 0
1468 AVX_INSTR psllw, mmx, 0, 0, 0
1469 AVX_INSTR pslld, mmx, 0, 0, 0
1470 AVX_INSTR psllq, mmx, 0, 0, 0
1471 AVX_INSTR pslldq, sse2, 0, 0, 0
1472 AVX_INSTR psraw, mmx, 0, 0, 0
1473 AVX_INSTR psrad, mmx, 0, 0, 0
1474 AVX_INSTR psrlw, mmx, 0, 0, 0
1475 AVX_INSTR psrld, mmx, 0, 0, 0
1476 AVX_INSTR psrlq, mmx, 0, 0, 0
1477 AVX_INSTR psrldq, sse2, 0, 0, 0
1478 AVX_INSTR psubb, mmx, 0, 0, 0
1479 AVX_INSTR psubw, mmx, 0, 0, 0
1480 AVX_INSTR psubd, mmx, 0, 0, 0
1481 AVX_INSTR psubq, sse2, 0, 0, 0
1482 AVX_INSTR psubsb, mmx, 0, 0, 0
1483 AVX_INSTR psubsw, mmx, 0, 0, 0
1484 AVX_INSTR psubusb, mmx, 0, 0, 0
1485 AVX_INSTR psubusw, mmx, 0, 0, 0
1486 AVX_INSTR ptest, sse4
1487 AVX_INSTR punpckhbw, mmx, 0, 0, 0
1488 AVX_INSTR punpckhwd, mmx, 0, 0, 0
1489 AVX_INSTR punpckhdq, mmx, 0, 0, 0
1490 AVX_INSTR punpckhqdq, sse2, 0, 0, 0
1491 AVX_INSTR punpcklbw, mmx, 0, 0, 0
1492 AVX_INSTR punpcklwd, mmx, 0, 0, 0
1493 AVX_INSTR punpckldq, mmx, 0, 0, 0
1494 AVX_INSTR punpcklqdq, sse2, 0, 0, 0
1495 AVX_INSTR pxor, mmx, 0, 0, 1
1496 AVX_INSTR rcpps, sse
1497 AVX_INSTR rcpss, sse, 1, 0, 0
1498 AVX_INSTR roundpd, sse4
1499 AVX_INSTR roundps, sse4
1500 AVX_INSTR roundsd, sse4, 1, 1, 0
1501 AVX_INSTR roundss, sse4, 1, 1, 0
1502 AVX_INSTR rsqrtps, sse
1503 AVX_INSTR rsqrtss, sse, 1, 0, 0
1504 AVX_INSTR shufpd, sse2, 1, 1, 0
1505 AVX_INSTR shufps, sse, 1, 1, 0
1506 AVX_INSTR sqrtpd, sse2
1507 AVX_INSTR sqrtps, sse
1508 AVX_INSTR sqrtsd, sse2, 1, 0, 0
1509 AVX_INSTR sqrtss, sse, 1, 0, 0
1510 AVX_INSTR stmxcsr, sse
1511 AVX_INSTR subpd, sse2, 1, 0, 0
1512 AVX_INSTR subps, sse, 1, 0, 0
1513 AVX_INSTR subsd, sse2, 1, 0, 0
1514 AVX_INSTR subss, sse, 1, 0, 0
1515 AVX_INSTR ucomisd, sse2
1516 AVX_INSTR ucomiss, sse
1517 AVX_INSTR unpckhpd, sse2, 1, 0, 0
1518 AVX_INSTR unpckhps, sse, 1, 0, 0
1519 AVX_INSTR unpcklpd, sse2, 1, 0, 0
1520 AVX_INSTR unpcklps, sse, 1, 0, 0
1521 AVX_INSTR xorpd, sse2, 1, 0, 1
1522 AVX_INSTR xorps, sse, 1, 0, 1
1524 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN
1525 AVX_INSTR pfadd, 3dnow, 1, 0, 1
1526 AVX_INSTR pfsub, 3dnow, 1, 0, 0
1527 AVX_INSTR pfmul, 3dnow, 1, 0, 1
1529 ; base-4 constants for shuffles
1532 %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)
1534 CAT_XDEFINE q000, j, i
1536 CAT_XDEFINE q00, j, i
1538 CAT_XDEFINE q0, j, i
1548 %macro %1 4-7 %1, %2, %3
1555 %error non-xop emulation of ``%5 %1, %2, %3, %4'' is not supported
1560 FMA_INSTR pmacsww, pmullw, paddw
1561 FMA_INSTR pmacsdd, pmulld, paddd ; sse4 emulation
1562 FMA_INSTR pmacsdql, pmuldq, paddq ; sse4 emulation
1563 FMA_INSTR pmadcswd, pmaddwd, paddd
1565 ; tzcnt is equivalent to "rep bsf" and is backwards-compatible with bsf.
1566 ; This lets us use tzcnt without bumping the yasm version requirement yet.
1567 %define tzcnt rep bsf
1569 ; Macros for consolidating FMA3 and FMA4 using 4-operand (dst, src1, src2, src3) syntax.
1570 ; FMA3 is only possible if dst is the same as one of the src registers.
1571 ; Either src2 or src3 can be a memory operand.
1572 %macro FMA4_INSTR 2-*
1574 %xdefine %$prefix %1
1576 %macro %$prefix%2 4-6 %$prefix, %2
1577 %if notcpuflag(fma3) && notcpuflag(fma4)
1578 %error use of ``%5%6'' fma instruction in cpuname function: current_function
1580 v%5%6 %1, %2, %3, %4
1582 ; If %3 or %4 is a memory operand it needs to be encoded as the last operand.
1584 v%{5}213%6 %2, %3, %4
1586 v%{5}132%6 %2, %4, %3
1589 v%{5}213%6 %3, %2, %4
1591 v%{5}231%6 %4, %2, %3
1593 %error fma3 emulation of ``%5%6 %1, %2, %3, %4'' is not supported
1601 FMA4_INSTR fmadd, pd, ps, sd, ss
1602 FMA4_INSTR fmaddsub, pd, ps
1603 FMA4_INSTR fmsub, pd, ps, sd, ss
1604 FMA4_INSTR fmsubadd, pd, ps
1605 FMA4_INSTR fnmadd, pd, ps, sd, ss
1606 FMA4_INSTR fnmsub, pd, ps, sd, ss
1608 ; Macros for converting VEX instructions to equivalent EVEX ones.
1609 %macro EVEX_INSTR 2-3 0 ; vex, evex, prefer_evex
1610 %macro %1 2-7 fnord, fnord, %1, %2, %3
1612 %define %%args %1, %2
1614 %define %%args %1, %2, %3
1616 %define %%args %1, %2, %3, %4
1618 %assign %%evex_required cpuflag(avx512) & %7
1620 %if regnumof%1 >= 16 || sizeof%1 > 32
1621 %assign %%evex_required 1
1625 %if regnumof%2 >= 16 || sizeof%2 > 32
1626 %assign %%evex_required 1
1632 %5 %%args ; Prefer VEX over EVEX due to shorter instruction length
1637 EVEX_INSTR vbroadcastf128, vbroadcastf32x4
1638 EVEX_INSTR vbroadcasti128, vbroadcasti32x4
1639 EVEX_INSTR vextractf128, vextractf32x4
1640 EVEX_INSTR vextracti128, vextracti32x4
1641 EVEX_INSTR vinsertf128, vinsertf32x4
1642 EVEX_INSTR vinserti128, vinserti32x4
1643 EVEX_INSTR vmovdqa, vmovdqa32
1644 EVEX_INSTR vmovdqu, vmovdqu32
1645 EVEX_INSTR vpand, vpandd
1646 EVEX_INSTR vpandn, vpandnd
1647 EVEX_INSTR vpor, vpord
1648 EVEX_INSTR vpxor, vpxord
1649 EVEX_INSTR vrcpps, vrcp14ps, 1 ; EVEX versions have higher precision
1650 EVEX_INSTR vrcpss, vrcp14ss, 1
1651 EVEX_INSTR vrsqrtps, vrsqrt14ps, 1
1652 EVEX_INSTR vrsqrtss, vrsqrt14ss, 1
1654 ; workaround: vpbroadcastq is broken in x86_32 due to a yasm bug (fixed in 1.3.0)
1656 %if __YASM_VERSION_ID__ < 0x01030000 && ARCH_X86_64 == 0
1657 %macro vpbroadcastq 2