1 // SPDX-License-Identifier: MIT
3 #include "pistorm-dev.h"
4 #include "pistorm-dev-enums.h"
7 #define DEBUG_PISTORM_DEVICE
9 #ifdef DEBUG_PISTORM_DEVICE
12 #define PIDEV_SWREV 0x0105
14 static const char *op_type_names[4] = {
24 extern uint32_t pistorm_dev_base;
25 extern uint32_t do_reset;
27 extern uint8_t rtg_enabled, rtg_on, pinet_enabled, piscsi_enabled;
29 void handle_pistorm_dev_write(uint32_t addr, uint32_t val, uint8_t type) {
30 switch((addr & 0xFFFF)) {
32 DEBUG("[PISTORM-DEV] System reset called through PiStorm interaction device, code %d\n", (val & 0xFFFF));
36 DEBUG("[PISTORM-DEV] WARN: Unhandled %s register write to %.4X: %d\n", op_type_names[type], addr - pistorm_dev_base, val);
41 uint32_t handle_pistorm_dev_read(uint32_t addr, uint8_t type) {
42 switch((addr & 0xFFFF)) {
44 // Probably replace this with some read from the CPLD to get a simple hardware revision.
45 DEBUG("[PISTORM-DEV] %s Read from HWREV\n", op_type_names[type]);
49 DEBUG("[PISTORM-DEV] %s Read from SWREV\n", op_type_names[type]);
52 case PI_CMD_RTGSTATUS:
53 DEBUG("[PISTORM-DEV] %s Read from RTGSTATUS\n", op_type_names[type]);
54 return (rtg_on << 1) | rtg_enabled;
56 case PI_CMD_NETSTATUS:
57 DEBUG("[PISTORM-DEV] %s Read from NETSTATUS\n", op_type_names[type]);
60 case PI_CMD_PISCSI_CTRL:
61 DEBUG("[PISTORM-DEV] %s Read from PISCSI_CTRL\n", op_type_names[type]);
62 return piscsi_enabled;
65 DEBUG("[PISTORM-DEV] WARN: Unhandled %s register read from %.4X\n", op_type_names[type], addr - pistorm_dev_base);