1 // SPDX-License-Identifier: MIT
9 #include "config_file/config_file.h"
10 #include "gpio/ps_protocol.h"
11 #include "platforms/amiga/rtg/irtg_structs.h"
16 void rtg_p2c_ex(int16_t sx, int16_t sy, int16_t dx, int16_t dy, int16_t w, int16_t h, uint8_t minterm, struct BitMap *bm, uint8_t mask, uint16_t dst_pitch, uint16_t src_pitch);
19 uint16_t rtg_x[8], rtg_y[8];
22 uint32_t rtg_address[8];
23 uint32_t rtg_address_adj[8];
26 static uint8_t display_enabled = 0xFF;
28 uint16_t rtg_display_width, rtg_display_height;
29 uint16_t rtg_display_format;
30 uint16_t rtg_pitch, rtg_total_rows;
31 uint16_t rtg_offset_x, rtg_offset_y;
33 uint8_t *rtg_mem; // FIXME
35 uint32_t framebuffer_addr = 0;
36 uint32_t framebuffer_addr_adj = 0;
38 static void handle_rtg_command(uint32_t cmd);
39 static void handle_irtg_command(uint32_t cmd);
41 uint8_t realtime_graphics_debug = 0;
42 extern int cpu_emulation_running;
43 extern struct emulator_config *cfg;
44 extern uint8_t rtg_on;
49 /*static const char *op_type_names[OP_TYPE_NUM] = {
56 /*static const char *rtg_format_names[RTGFMT_NUM] = {
67 int init_rtg_data(struct emulator_config *cfg_) {
68 rtg_mem = calloc(1, 40 * SIZE_MEGA);
70 printf("Failed to allocate RTG video memory.\n");
74 m68k_add_ram_range(PIGFX_RTG_BASE + PIGFX_REG_SIZE, 32 * SIZE_MEGA - PIGFX_REG_SIZE, rtg_mem);
75 add_mapping(cfg_, MAPTYPE_RAM_NOALLOC, PIGFX_RTG_BASE + PIGFX_REG_SIZE, 40 * SIZE_MEGA - PIGFX_REG_SIZE, -1, (char *)rtg_mem, "rtg_mem", 0);
80 printf("[RTG] Shutting down RTG.\n");
91 unsigned int rtg_get_fb() {
92 return PIGFX_RTG_BASE + PIGFX_REG_SIZE + framebuffer_addr_adj;
95 unsigned int rtg_read(uint32_t address, uint8_t mode) {
96 //printf("%s read from RTG: %.8X\n", op_type_names[mode], address);
97 if (address == RTG_COMMAND) {
100 if (address >= PIGFX_REG_SIZE) {
101 if (rtg_mem && (address - PIGFX_REG_SIZE) < PIGFX_UPPER) {
104 return (rtg_mem[address - PIGFX_REG_SIZE]);
107 return be16toh(*(( uint16_t *) (&rtg_mem[address - PIGFX_REG_SIZE])));
109 case OP_TYPE_LONGWORD:
110 return be32toh(*(( uint32_t *) (&rtg_mem[address - PIGFX_REG_SIZE])));
121 struct timespec diff(struct timespec start, struct timespec end)
123 struct timespec temp;
124 if ((end.tv_nsec-start.tv_nsec)<0) {
125 temp.tv_sec = end.tv_sec-start.tv_sec-1;
126 temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
128 temp.tv_sec = end.tv_sec-start.tv_sec;
129 temp.tv_nsec = end.tv_nsec-start.tv_nsec;
134 #define CHKREG(a, b) case a: b = value; break;
136 void rtg_write(uint32_t address, uint32_t value, uint8_t mode) {
137 //printf("%s write to RTG: %.8X (%.8X)\n", op_type_names[mode], address, value);
138 if (address >= PIGFX_REG_SIZE) {
139 /*if ((address - PIGFX_REG_SIZE) < framebuffer_addr) {// || (address - PIGFX_REG_SIZE) > framebuffer_addr + ((rtg_display_width << rtg_display_format) * rtg_display_height)) {
140 printf("Write to RTG memory outside frame buffer %.8X (%.8X).\n", (address - PIGFX_REG_SIZE), framebuffer_addr);
142 if (rtg_mem && (address - PIGFX_REG_SIZE) < PIGFX_UPPER) {
145 rtg_mem[address - PIGFX_REG_SIZE] = value;
148 *(( uint16_t *) (&rtg_mem[address - PIGFX_REG_SIZE])) = htobe16(value);
150 case OP_TYPE_LONGWORD:
151 *(( uint32_t *) (&rtg_mem[address - PIGFX_REG_SIZE])) = htobe32(value);
157 } else if (address == RTG_DEBUGME) {
158 printf("RTG DEBUGME WRITE: %d.\n", value);
163 CHKREG(RTG_U81, rtg_u8[0]);
164 CHKREG(RTG_U82, rtg_u8[1]);
165 CHKREG(RTG_U83, rtg_u8[2]);
166 CHKREG(RTG_U84, rtg_u8[3]);
171 CHKREG(RTG_X1, rtg_x[0]);
172 CHKREG(RTG_X2, rtg_x[1]);
173 CHKREG(RTG_X3, rtg_x[2]);
174 CHKREG(RTG_X4, rtg_x[3]);
175 CHKREG(RTG_X5, rtg_x[4]);
176 CHKREG(RTG_Y1, rtg_y[0]);
177 CHKREG(RTG_Y2, rtg_y[1]);
178 CHKREG(RTG_Y3, rtg_y[2]);
179 CHKREG(RTG_Y4, rtg_y[3]);
180 CHKREG(RTG_Y5, rtg_y[4]);
181 CHKREG(RTG_U1, rtg_user[0]);
182 CHKREG(RTG_U2, rtg_user[1]);
183 CHKREG(RTG_FORMAT, rtg_format);
185 handle_rtg_command(value);
188 handle_irtg_command(value);
192 case OP_TYPE_LONGWORD:
195 rtg_address[0] = value;
196 rtg_address_adj[0] = value - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
199 rtg_address[1] = value;
200 rtg_address_adj[1] = value - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
202 CHKREG(RTG_ADDR3, rtg_address[2]);
203 CHKREG(RTG_ADDR4, rtg_address[3]);
204 CHKREG(RTG_RGB1, rtg_rgb[0]);
205 CHKREG(RTG_RGB2, rtg_rgb[1]);
214 #define gdebug(a) if (realtime_graphics_debug) { printf(a); m68k_end_timeslice(); cpu_emulation_running = 0; }
215 #define M68KR(a) m68k_get_reg(NULL, a)
216 #define RGBF_D7 rgbf_to_rtg[M68KR(M68K_REG_D7)]
217 #define CMD_PITCH be16toh(r->BytesPerRow)
219 static struct P96RenderInfo *r;
220 static struct P96BoardInfo *b;
221 static struct P96Line *ln;
222 static uint8_t cmd_mask;
224 static void handle_irtg_command(uint32_t cmd) {
225 b = (struct P96BoardInfo *)get_mapped_data_pointer_by_address(cfg, M68KR(M68K_REG_A0));
226 r = (struct P96RenderInfo *)get_mapped_data_pointer_by_address(cfg, M68KR(M68K_REG_A1));
229 case RTGCMD_SETPAN: {
230 // A0: struct BoardInfo *b, A1: UBYTE *addr, D0 UWORD width, D1: WORD x_offset, D2: WORD y_offset, D7: RGBFTYPE format
232 if (realtime_graphics_debug) {
233 printf("iSetPanning begin\n");
234 printf("IRTGCmd SetPanning\n");
235 printf("IRTGCmd x: %d y: %d w: %d (%d)\n", M68KR(M68K_REG_D1), M68KR(M68K_REG_D2), M68KR(M68K_REG_D0) << RGBF_D7, M68KR(M68K_REG_D0));
236 printf("BoardInfo: %.8X Addr: %.8X\n", M68KR(M68K_REG_A0), M68KR(M68K_REG_A1));
237 printf("BoardInfo Xoffs: %d Yoffs: %d\n", be16toh(b->XOffset), be16toh(b->YOffset));
242 b->XOffset = (int16_t)htobe16(M68KR(M68K_REG_D1));
243 b->YOffset = (int16_t)htobe16(M68KR(M68K_REG_D2));
245 rtg_offset_x = M68KR(M68K_REG_D1);
246 rtg_offset_y = M68KR(M68K_REG_D2);
247 rtg_pitch = (M68KR(M68K_REG_D0) << RGBF_D7);
248 framebuffer_addr = M68KR(M68K_REG_A1) - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
249 framebuffer_addr_adj = framebuffer_addr + (rtg_offset_x << RGBF_D7) + (rtg_offset_y * rtg_pitch);
252 if (realtime_graphics_debug) {
253 printf("RTG OffsetX/Y: %d/%d\n", rtg_offset_x, rtg_offset_y);
254 printf("RTG Pitch: %d\n", rtg_pitch);
255 printf("RTG FBAddr/Adj: %.8X (%.8X)/%.8X\n", framebuffer_addr, M68KR(M68K_REG_A1), framebuffer_addr_adj);
256 printf("iSetPanning End\n");
262 case RTGCMD_DRAWLINE: {
263 // A0: struct BoardInfo *b, A1: RenderInfo *r A2: struct Line *l, D0: UBYTE mask, D7: RGBFTYPE format
264 gdebug("iDrawLine begin\n");
265 ln = (struct P96Line *)get_mapped_data_pointer_by_address(cfg, M68KR(M68K_REG_A2));
267 if (!ln || !r) break;
269 cmd_mask = (uint8_t)M68KR(M68K_REG_D0);
270 rtg_address_adj[0] = be32toh(r->_p_Memory) - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
272 if (cmd_mask == 0xFF && be16toh(ln->LinePtrn) == 0xFFFF) {
273 rtg_drawline_solid(be16toh(ln->X), be16toh(ln->Y), be16toh(ln->dX), be16toh(ln->dY),
274 be16toh(ln->Length), be32toh(ln->FgPen), CMD_PITCH, RGBF_D7);
276 rtg_drawline(be16toh(ln->X), be16toh(ln->Y), be16toh(ln->dX), be16toh(ln->dY),
277 be16toh(ln->Length), be16toh(ln->LinePtrn), be16toh(ln->PatternShift),
278 be32toh(ln->FgPen), be32toh(ln->BgPen), CMD_PITCH,
279 RGBF_D7, cmd_mask, ln->DrawMode);
281 gdebug("iDrawLine end\n");
284 case RTGCMD_FILLRECT: {
285 // A0: BoardInfo *b, A1: RenderInfo *r
286 // D0 WORD x, D1: WORD y, D2: WORD w, D3: WORD h
287 // D4: ULONG color, D5: UBYTE mask, D7: RGBFTYPE format
288 gdebug("iFillRect begin\n");
290 if (realtime_graphics_debug) {
291 DEBUG("X1/X2: %d/%d-> X2/Y2: %d/%d\n", (int16_t)M68KR(M68K_REG_D0), (int16_t)M68KR(M68K_REG_D1), (int16_t)M68KR(M68K_REG_D2), (int16_t)M68KR(M68K_REG_D3));
292 DEBUG("R: %.8X B: %.8X\n", M68KR(M68K_REG_A0), M68KR(M68K_REG_A1));
298 cmd_mask = (uint8_t)M68KR(M68K_REG_D5);
299 rtg_address_adj[0] = be32toh(r->_p_Memory) - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
301 if (cmd_mask == 0xFF) {
302 rtg_fillrect_solid((int16_t)M68KR(M68K_REG_D0), (int16_t)M68KR(M68K_REG_D1), (int16_t)M68KR(M68K_REG_D2), (int16_t)M68KR(M68K_REG_D3),
303 M68KR(M68K_REG_D4), CMD_PITCH, RGBF_D7);
305 rtg_fillrect((int16_t)M68KR(M68K_REG_D0), (int16_t)M68KR(M68K_REG_D1), (int16_t)M68KR(M68K_REG_D2), (int16_t)M68KR(M68K_REG_D3),
306 M68KR(M68K_REG_D4), CMD_PITCH, RGBF_D7, cmd_mask);
308 gdebug("iFillRect end\n");
311 case RTGCMD_INVERTRECT: {
312 // A0: BoardInfo *b, A1: RenderInfo *r
313 // D0 WORD x, D1: WORD y, D2: WORD w, D3: WORD h
314 // D4: UBYTE mask, D7: RGBFTYPE format
315 gdebug("iInvertRect begin\n");
318 cmd_mask = (uint8_t)M68KR(M68K_REG_D4);
319 rtg_address_adj[0] = be32toh(r->_p_Memory) - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
321 rtg_invertrect((int16_t)M68KR(M68K_REG_D0), (int16_t)M68KR(M68K_REG_D1), (int16_t)M68KR(M68K_REG_D2), (int16_t)M68KR(M68K_REG_D3), CMD_PITCH, RGBF_D7, cmd_mask);
322 gdebug("iInvertRect end\n");
325 case RTGCMD_BLITRECT: {
326 // A0: BoardInfo *b, A1: RenderInfo *r)
327 // D0: WORD x, D1: WORD y, D2: WORD dx, D3: WORD dy, D4: WORD w, D5: WORD h,
328 // D6: UBYTE mask, D7: RGBFTYPE format
329 gdebug("iBlitRect begin\n");
331 cmd_mask = (uint8_t)M68KR(M68K_REG_D6);
332 rtg_address_adj[0] = be32toh(r->_p_Memory) - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
334 if (cmd_mask == 0xFF) {
335 rtg_blitrect_solid(M68KR(M68K_REG_D0), M68KR(M68K_REG_D1), M68KR(M68K_REG_D2), M68KR(M68K_REG_D3), M68KR(M68K_REG_D4), M68KR(M68K_REG_D5), CMD_PITCH, RGBF_D7);
337 rtg_blitrect(M68KR(M68K_REG_D0), M68KR(M68K_REG_D1), M68KR(M68K_REG_D2), M68KR(M68K_REG_D3), M68KR(M68K_REG_D4), M68KR(M68K_REG_D5), CMD_PITCH, RGBF_D7, cmd_mask);
340 gdebug("iBlitRect end\n");
343 case RTGCMD_BLITRECT_NOMASK_COMPLETE: {
344 // A0: BoardInfo *b, A1: RenderInfo *rs, A2: RenderInfo *rt,
345 // D0: WORD x, D1: WORD y, D2: WORD dx, D3: WORD dy, D4: WORD w, D5: WORD h,
346 // D6: UBYTE minterm, D7: RGBFTYPE format
347 gdebug("iBlitRectNoMaskComplete begin\n");
349 uint8_t minterm = (uint8_t)M68KR(M68K_REG_D6);
350 struct P96RenderInfo *rt = (struct P96RenderInfo *)get_mapped_data_pointer_by_address(cfg, M68KR(M68K_REG_A2));
352 uint32_t src_addr = be32toh(r->_p_Memory);
353 uint32_t dst_addr = be32toh(rt->_p_Memory);
355 rtg_blitrect_nomask_complete(M68KR(M68K_REG_D0), M68KR(M68K_REG_D1), M68KR(M68K_REG_D2), M68KR(M68K_REG_D3), M68KR(M68K_REG_D4), M68KR(M68K_REG_D5),
356 CMD_PITCH, be16toh(rt->BytesPerRow), src_addr, dst_addr, RGBF_D7, minterm);
358 gdebug("iBlitRectNoMaskComplete end\n");
361 case RTGCMD_BLITTEMPLATE: {
362 // A0: BoardInfo *b, A1: RenderInfo *r, A2: Template *t
363 // D0: WORD x, D1: WORD y, D2: WORD w, D3: WORD h
364 // D4: UBYTE mask, D7: RGBFTYPE format
365 if (!r || !M68KR(M68K_REG_A2))
367 gdebug("iBlitTemplate begin\n");
369 uint16_t t_pitch = 0, x_offset = 0;
370 uint32_t src_addr = M68KR(M68K_REG_A2);
371 uint32_t fgcol = 0, bgcol = 0;
372 uint8_t draw_mode = 0;
374 struct P96Template *t = (struct P96Template *)get_mapped_data_pointer_by_address(cfg, M68KR(M68K_REG_A2));
376 t_pitch = be16toh(t->BytesPerRow);
377 fgcol = be32toh(t->FgPen);
378 bgcol = be32toh(t->BgPen);
379 x_offset = t->XOffset;
380 draw_mode = t->DrawMode;
381 src_addr = be32toh(t->_p_Memory);
383 t_pitch = be16toh(ps_read_16(src_addr + (uint32_t)&t->BytesPerRow));
384 fgcol = be32toh(ps_read_32(src_addr + (uint32_t)&t->FgPen));
385 bgcol = be32toh(ps_read_32(src_addr + (uint32_t)&t->BgPen));
386 x_offset = ps_read_8(src_addr + (uint32_t)&t->XOffset);
387 draw_mode = ps_read_8(src_addr + (uint32_t)&t->DrawMode);
388 src_addr = be32toh(ps_read_32(src_addr + (uint32_t)&t->_p_Memory));
391 cmd_mask = (uint8_t)M68KR(M68K_REG_D4);
392 rtg_address[1] = be32toh(r->_p_Memory);
393 rtg_address_adj[1] = rtg_address[1] - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
395 rtg_blittemplate(M68KR(M68K_REG_D0), M68KR(M68K_REG_D1), M68KR(M68K_REG_D2), M68KR(M68K_REG_D3), src_addr, fgcol, bgcol, CMD_PITCH, t_pitch, RGBF_D7, x_offset, cmd_mask, draw_mode);
396 gdebug("iBlitTemplate end\n");
399 case RTGCMD_BLITPATTERN: {
400 // A0: BoardInfo *b, A1: RenderInfo *r, A2: Pattern *p
401 // D0: WORD x, D1: WORD y, D2: WORD w, D3: WORD h
402 // D4: UBYTE mask, D7: RGBFTYPE format
403 if (!r || !M68KR(M68K_REG_A2))
405 gdebug("iBlitPattern begin\n");
407 uint16_t x_offset = 0, y_offset = 0;
408 uint32_t src_addr = M68KR(M68K_REG_A2);
409 uint32_t fgcol = 0, bgcol = 0;
410 uint8_t draw_mode = 0, loop_rows = 0;
412 struct P96Pattern *p = (struct P96Pattern *)get_mapped_data_pointer_by_address(cfg, M68KR(M68K_REG_A2));
414 fgcol = be32toh(p->FgPen);
415 bgcol = be32toh(p->BgPen);
416 x_offset = be16toh(p->XOffset);
417 y_offset = be16toh(p->YOffset);
418 draw_mode = p->DrawMode;
419 loop_rows = 1 << p->Size;
420 src_addr = be32toh(p->_p_Memory);
422 fgcol = be32toh(ps_read_32(src_addr + (uint32_t)&p->FgPen));
423 bgcol = be32toh(ps_read_32(src_addr + (uint32_t)&p->BgPen));
424 x_offset = be16toh(ps_read_16(src_addr + (uint32_t)&p->XOffset));
425 y_offset = be16toh(ps_read_16(src_addr + (uint32_t)&p->YOffset));
426 draw_mode = ps_read_8(src_addr + (uint32_t)&p->DrawMode);
427 loop_rows = 1 << ps_read_8(src_addr + (uint32_t)&p->Size);
428 src_addr = be32toh(p->_p_Memory);
431 cmd_mask = (uint8_t)M68KR(M68K_REG_D4);
432 rtg_address[1] = be32toh(r->_p_Memory);
433 rtg_address_adj[1] = rtg_address[1] - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
435 rtg_blitpattern(M68KR(M68K_REG_D0), M68KR(M68K_REG_D1), M68KR(M68K_REG_D2), M68KR(M68K_REG_D3), src_addr, fgcol, bgcol, CMD_PITCH, RGBF_D7, x_offset, y_offset, cmd_mask, draw_mode, loop_rows);
436 gdebug("iBlitPattern end\n");
440 // A0: BoardInfo, A1: BitMap *bm, A2: RenderInfo *r,
441 // D0: SHORT x, D1: SHORT y, D2: SHORT dx, D3: SHORT dy, D4: SHORT w, D5: SHORT h,
442 // D6: UBYTE minterm, D7: UBYTE mask
443 r = (struct P96RenderInfo *)get_mapped_data_pointer_by_address(cfg, M68KR(M68K_REG_A2));
444 struct BitMap *bm = (struct BitMap *)get_mapped_data_pointer_by_address(cfg, M68KR(M68K_REG_A1));
448 gdebug("iP2C begin\n");
451 printf ("Help! BitMap not in mapped memory.\n");
454 gdebug("Data is available in mapped memory.\n");
457 if (realtime_graphics_debug) {
458 printf("bm: %.8X r: %.8X\n", (uint32_t)bm, (uint32_t)r);
460 printf("bm pitch: %d\n", be16toh(bm->BytesPerRow));
462 printf("r pitch: %d\n", be16toh(r->BytesPerRow));
465 uint16_t bmp_pitch = be16toh(bm->BytesPerRow);
466 uint16_t line_pitch = be16toh(r->BytesPerRow);
467 rtg_address_adj[0] = be32toh(r->_p_Memory) - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
469 uint8_t minterm = (uint8_t)M68KR(M68K_REG_D6);
470 cmd_mask = (uint8_t)M68KR(M68K_REG_D7);
472 rtg_p2c_ex(M68KR(M68K_REG_D0), M68KR(M68K_REG_D1), M68KR(M68K_REG_D2), M68KR(M68K_REG_D3), M68KR(M68K_REG_D4), M68KR(M68K_REG_D5), minterm, bm, cmd_mask, line_pitch, bmp_pitch);
473 gdebug("iP2C end\n");
477 printf("[!!!IRTG] Unnkonw/unhandled iRTG command %d.\n", cmd);
482 static void handle_rtg_command(uint32_t cmd) {
483 //printf("Handling RTG command %d (%.8X)\n", cmd, cmd);
486 rtg_display_format = rtg_format;
487 rtg_display_width = rtg_x[0];
488 rtg_display_height = rtg_y[0];
490 //rtg_pitch = rtg_display_width << rtg_format;
491 framebuffer_addr_adj = framebuffer_addr + (rtg_offset_x << rtg_display_format) + (rtg_offset_y * rtg_pitch);
492 rtg_total_rows = rtg_y[1];
495 //rtg_pitch = rtg_display_width << rtg_format;
496 framebuffer_addr_adj = framebuffer_addr + (rtg_offset_x << rtg_display_format) + (rtg_offset_y * rtg_pitch);
497 rtg_total_rows = rtg_y[1];
499 //printf("Set RTG mode:\n");
500 //printf("%dx%d pixels\n", rtg_display_width, rtg_display_height);
501 //printf("Pixel format: %s\n", rtg_format_names[rtg_display_format]);
504 //printf("Command: SetPan.\n");
505 rtg_offset_x = rtg_x[1];
506 rtg_offset_y = rtg_y[1];
507 rtg_pitch = (rtg_x[0] << rtg_display_format);
508 framebuffer_addr = rtg_address[0] - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
509 framebuffer_addr_adj = framebuffer_addr + (rtg_offset_x << rtg_display_format) + (rtg_offset_y * rtg_pitch);
511 case RTGCMD_SETCLUT: {
512 //printf("Command: SetCLUT.\n");
513 //printf("Set palette entry %d to %d, %d, %d\n", rtg_u8[0], rtg_u8[1], rtg_u8[2], rtg_u8[3]);
514 //printf("Set palette entry %d to 32-bit palette color: %.8X\n", rtg_u8[0], rtg_rgb[0]);
515 rtg_set_clut_entry(rtg_u8[0], rtg_rgb[0]);
518 case RTGCMD_SETDISPLAY:
519 //printf("RTG SetDisplay %s\n", (rtg_u8[1]) ? "enabled" : "disabled");
521 //printf("Command: SetDisplay.\n");
524 case RTGCMD_SETSWITCH:
525 //printf("RTG SetSwitch %s\n", ((rtg_x[0]) & 0x01) ? "enabled" : "disabled");
526 //printf("LAL: %.4X\n", rtg_x[0]);
527 if (display_enabled != ((rtg_x[0]) & 0x01)) {
528 display_enabled = ((rtg_x[0]) & 0x01);
529 if (display_enabled) {
533 rtg_shutdown_display();
536 case RTGCMD_FILLRECT:
537 if (rtg_u8[0] == 0xFF || rtg_format != RTGFMT_8BIT) {
538 rtg_fillrect_solid(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_rgb[0], rtg_x[2], rtg_format);
539 gdebug("FillRect Solid\n");
542 rtg_fillrect(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_rgb[0], rtg_x[2], rtg_format, rtg_u8[0]);
543 gdebug("FillRect Masked\n");
546 case RTGCMD_INVERTRECT:
547 rtg_invertrect(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_format, rtg_u8[0]);
548 gdebug("InvertRect\n");
550 case RTGCMD_BLITRECT:
551 if (rtg_u8[0] == 0xFF || rtg_format != RTGFMT_8BIT) {
552 rtg_blitrect_solid(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_x[3], rtg_format);
553 gdebug("BlitRect Solid\n");
556 rtg_blitrect(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_x[3], rtg_format, rtg_u8[0]);
557 gdebug("BlitRect Masked\n");
560 case RTGCMD_BLITRECT_NOMASK_COMPLETE:
561 rtg_blitrect_nomask_complete(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_x[3], rtg_x[4], rtg_address[0], rtg_address[1], rtg_format, rtg_u8[0]);
562 gdebug("BlitRectNoMaskComplete\n");
564 case RTGCMD_BLITPATTERN:
565 rtg_blitpattern(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_address[0], rtg_rgb[0], rtg_rgb[1], rtg_x[3], rtg_format, rtg_x[2], rtg_y[2], rtg_u8[0], rtg_u8[1], rtg_u8[2]);
566 gdebug("BlitPattern\n");
568 case RTGCMD_BLITTEMPLATE:
569 rtg_blittemplate(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_address[0], rtg_rgb[0], rtg_rgb[1], rtg_x[3], rtg_x[4], rtg_format, rtg_x[2], rtg_u8[0], rtg_u8[1]);
570 gdebug("BlitTemplate\n");
572 case RTGCMD_DRAWLINE:
573 if (rtg_u8[0] == 0xFF && rtg_y[2] == 0xFFFF)
574 rtg_drawline_solid(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_rgb[0], rtg_x[3], rtg_format);
576 rtg_drawline(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_x[4], rtg_rgb[0], rtg_rgb[1], rtg_x[3], rtg_format, rtg_u8[0], rtg_u8[1]);
577 gdebug("DrawLine\n");
580 rtg_p2c(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_u8[1], rtg_u8[2], rtg_u8[0], (rtg_user[0] >> 0x8), rtg_x[4], (uint8_t *)&rtg_mem[rtg_address_adj[1]]);
581 gdebug("Planar2Chunky\n");
584 rtg_p2d(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_u8[1], rtg_u8[2], rtg_u8[0], (rtg_user[0] >> 0x8), rtg_x[4], (uint8_t *)&rtg_mem[rtg_address_adj[1]]);
585 gdebug("Planar2Direct\n");
587 case RTGCMD_SETSPRITE:
588 rtg_enable_mouse_cursor();
589 gdebug("SetSprite\n");
591 case RTGCMD_SETSPRITECOLOR:
592 rtg_set_cursor_clut_entry(rtg_u8[0], rtg_u8[1], rtg_u8[2], rtg_u8[3]);
593 gdebug("SetSpriteColor\n");
595 case RTGCMD_SETSPRITEPOS:
596 rtg_set_mouse_cursor_pos((int16_t)rtg_x[0], (int16_t)rtg_y[0]);
597 gdebug("SetSpritePos\n");
599 case RTGCMD_SETSPRITEIMAGE:
600 rtg_set_mouse_cursor_image(&rtg_mem[rtg_address_adj[1]], rtg_u8[0], rtg_u8[1]);
601 gdebug("SetSpriteImage\n");
604 printf ("[RTG] DebugMe!\n");
607 printf("[!!!RTG] Unknown/unhandled RTG command %d ($%.4X)\n", cmd, cmd);