1 ## Generated SDC file "pistorm.sdc"
3 ## Copyright (C) 2020 Intel Corporation. All rights reserved.
4 ## Your use of Intel Corporation's design tools, logic functions
5 ## and other software and tools, and any partner logic
6 ## functions, and any output files from any of the foregoing
7 ## (including device programming or simulation files), and any
8 ## associated documentation or information are expressly subject
9 ## to the terms and conditions of the Intel Program License
10 ## Subscription Agreement, the Intel Quartus Prime License Agreement,
11 ## the Intel FPGA IP License Agreement, or other applicable license
12 ## agreement, including, without limitation, that your use is for
13 ## the sole purpose of programming logic devices manufactured by
14 ## Intel and sold by Intel or its authorized distributors. Please
15 ## refer to the applicable agreement for further details, at
16 ## https://fpgasoftware.intel.com/eula.
20 ## PROGRAM "Quartus Prime"
21 ## VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
23 ## DATE "Sun Dec 20 15:18:48 2020"
26 ## DEVICE "EPM570T100C5"
30 #**************************************************************
32 #**************************************************************
34 set_time_format -unit ns -decimal_places 3
38 #**************************************************************
40 #**************************************************************
42 create_clock -name {PI_CLK} -period 5.000 [get_ports {PI_CLK}]
43 create_clock -name {M68K_CLK} -period 141.000 [get_ports {M68K_CLK}]
46 #**************************************************************
47 # Create Generated Clock
48 #**************************************************************
52 #**************************************************************
54 #**************************************************************
58 #**************************************************************
59 # Set Clock Uncertainty
60 #**************************************************************
64 #**************************************************************
66 #**************************************************************
70 #**************************************************************
72 #**************************************************************
76 #**************************************************************
78 #**************************************************************
82 #**************************************************************
84 #**************************************************************
86 set_false_path -from [get_ports {M68K_CLK M68K_DTACK_n M68K_VPA_n M68K_IPL_n[*] PI_A[*] PI_D[*] PI_RD PI_WR}]
87 set_false_path -to [get_ports {LTCH_A_0 LTCH_A_8 LTCH_A_16 LTCH_A_24 LTCH_A_OE_n LTCH_D_RD_L LTCH_D_RD_OE_n LTCH_D_RD_U LTCH_D_WR_L LTCH_D_WR_OE_n LTCH_D_WR_U M68K_AS_n M68K_BG_n M68K_E M68K_FC[*] M68K_HALT_n M68K_LDS_n M68K_RESET_n M68K_RW M68K_UDS_n M68K_VMA_n PI_TXN_IN_PROGRESS PI_IPL_ZERO PI_D[*]}]
89 set_false_path -from [get_clocks {M68K_CLK}] -to [get_clocks {PI_CLK}]
90 set_false_path -from [get_clocks {PI_CLK}] -to [get_clocks {M68K_CLK}]
92 #**************************************************************
94 #**************************************************************
98 #**************************************************************
100 #**************************************************************
104 #**************************************************************
106 #**************************************************************
110 #**************************************************************
111 # Set Input Transition
112 #**************************************************************