2 Stockfish, a UCI chess playing engine derived from Glaurung 2.1
3 Copyright (C) 2004-2022 The Stockfish developers (see AUTHORS file)
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19 // Definition of layer AffineTransform of NNUE evaluation function
21 #ifndef NNUE_LAYERS_AFFINE_TRANSFORM_H_INCLUDED
22 #define NNUE_LAYERS_AFFINE_TRANSFORM_H_INCLUDED
26 #include <type_traits>
27 #include "../nnue_common.h"
31 This file contains the definition for a fully connected layer (aka affine transform).
32 Two approaches are employed, depending on the sizes of the transform.
35 - used when the PaddedInputDimensions >= 128
36 - uses AVX512 if possible
37 - processes inputs in batches of 2*InputSimdWidth
38 - so in batches of 128 for AVX512
39 - the weight blocks of size InputSimdWidth are transposed such that
41 - N columns of the weight matrix are processed a time, where N
42 depends on the architecture (the amount of registers)
43 - accumulate + hadd is used
46 - used when the PaddedInputDimensions < 128
48 - expected use-case is for when PaddedInputDimensions == 32 and InputDimensions <= 32.
49 - that's why AVX512 is hard to implement
50 - expected use-case is small layers
51 - not optimized as well as the approach 1
52 - inputs are processed in chunks of 4, weights are respectively transposed
53 - accumulation happens directly to int32s
56 namespace Stockfish::Eval::NNUE::Layers {
58 // Fallback implementation for older/other architectures.
59 // Identical for both approaches. Requires the input to be padded to at least 16 values.
60 #if !defined(USE_SSSE3)
61 template <IndexType InputDimensions, IndexType PaddedInputDimensions, IndexType OutputDimensions>
62 static void affine_transform_non_ssse3(std::int32_t* output, const std::int8_t* weights, const std::int32_t* biases, const std::uint8_t* input)
64 # if defined(USE_SSE2)
65 // At least a multiple of 16, with SSE2.
66 constexpr IndexType NumChunks = ceil_to_multiple<IndexType>(InputDimensions, 16) / 16;
67 const __m128i Zeros = _mm_setzero_si128();
68 const auto inputVector = reinterpret_cast<const __m128i*>(input);
70 # elif defined(USE_MMX)
71 constexpr IndexType NumChunks = ceil_to_multiple<IndexType>(InputDimensions, 8) / 8;
72 const __m64 Zeros = _mm_setzero_si64();
73 const auto inputVector = reinterpret_cast<const __m64*>(input);
75 # elif defined(USE_NEON)
76 constexpr IndexType NumChunks = ceil_to_multiple<IndexType>(InputDimensions, 16) / 16;
77 const auto inputVector = reinterpret_cast<const int8x8_t*>(input);
80 for (IndexType i = 0; i < OutputDimensions; ++i) {
81 const IndexType offset = i * PaddedInputDimensions;
83 # if defined(USE_SSE2)
84 __m128i sumLo = _mm_cvtsi32_si128(biases[i]);
85 __m128i sumHi = Zeros;
86 const auto row = reinterpret_cast<const __m128i*>(&weights[offset]);
87 for (IndexType j = 0; j < NumChunks; ++j) {
88 __m128i row_j = _mm_load_si128(&row[j]);
89 __m128i input_j = _mm_load_si128(&inputVector[j]);
90 __m128i extendedRowLo = _mm_srai_epi16(_mm_unpacklo_epi8(row_j, row_j), 8);
91 __m128i extendedRowHi = _mm_srai_epi16(_mm_unpackhi_epi8(row_j, row_j), 8);
92 __m128i extendedInputLo = _mm_unpacklo_epi8(input_j, Zeros);
93 __m128i extendedInputHi = _mm_unpackhi_epi8(input_j, Zeros);
94 __m128i productLo = _mm_madd_epi16(extendedRowLo, extendedInputLo);
95 __m128i productHi = _mm_madd_epi16(extendedRowHi, extendedInputHi);
96 sumLo = _mm_add_epi32(sumLo, productLo);
97 sumHi = _mm_add_epi32(sumHi, productHi);
99 __m128i sum = _mm_add_epi32(sumLo, sumHi);
100 __m128i sumHigh_64 = _mm_shuffle_epi32(sum, _MM_SHUFFLE(1, 0, 3, 2));
101 sum = _mm_add_epi32(sum, sumHigh_64);
102 __m128i sum_second_32 = _mm_shufflelo_epi16(sum, _MM_SHUFFLE(1, 0, 3, 2));
103 sum = _mm_add_epi32(sum, sum_second_32);
104 output[i] = _mm_cvtsi128_si32(sum);
106 # elif defined(USE_MMX)
107 __m64 sumLo = _mm_cvtsi32_si64(biases[i]);
109 const auto row = reinterpret_cast<const __m64*>(&weights[offset]);
110 for (IndexType j = 0; j < NumChunks; ++j) {
111 __m64 row_j = row[j];
112 __m64 input_j = inputVector[j];
113 __m64 extendedRowLo = _mm_srai_pi16(_mm_unpacklo_pi8(row_j, row_j), 8);
114 __m64 extendedRowHi = _mm_srai_pi16(_mm_unpackhi_pi8(row_j, row_j), 8);
115 __m64 extendedInputLo = _mm_unpacklo_pi8(input_j, Zeros);
116 __m64 extendedInputHi = _mm_unpackhi_pi8(input_j, Zeros);
117 __m64 productLo = _mm_madd_pi16(extendedRowLo, extendedInputLo);
118 __m64 productHi = _mm_madd_pi16(extendedRowHi, extendedInputHi);
119 sumLo = _mm_add_pi32(sumLo, productLo);
120 sumHi = _mm_add_pi32(sumHi, productHi);
122 __m64 sum = _mm_add_pi32(sumLo, sumHi);
123 sum = _mm_add_pi32(sum, _mm_unpackhi_pi32(sum, sum));
124 output[i] = _mm_cvtsi64_si32(sum);
126 # elif defined(USE_NEON)
127 int32x4_t sum = {biases[i]};
128 const auto row = reinterpret_cast<const int8x8_t*>(&weights[offset]);
129 for (IndexType j = 0; j < NumChunks; ++j) {
130 int16x8_t product = vmull_s8(inputVector[j * 2], row[j * 2]);
131 product = vmlal_s8(product, inputVector[j * 2 + 1], row[j * 2 + 1]);
132 sum = vpadalq_s16(sum, product);
134 output[i] = sum[0] + sum[1] + sum[2] + sum[3];
137 std::int32_t sum = biases[i];
138 for (IndexType j = 0; j < InputDimensions; ++j) {
139 sum += weights[offset + j] * input[j];
145 # if defined(USE_MMX)
151 template <IndexType InDims, IndexType OutDims, typename Enabled = void>
152 class AffineTransform;
154 #if defined (USE_AVX512)
155 constexpr IndexType LargeInputSize = 2 * 64;
157 constexpr IndexType LargeInputSize = std::numeric_limits<IndexType>::max();
160 // A specialization for large inputs.
161 template <IndexType InDims, IndexType OutDims>
162 class AffineTransform<InDims, OutDims, std::enable_if_t<(ceil_to_multiple<IndexType>(InDims, MaxSimdWidth) >= LargeInputSize)>> {
165 using InputType = std::uint8_t;
166 using OutputType = std::int32_t;
168 // Number of input/output dimensions
169 static constexpr IndexType InputDimensions = InDims;
170 static constexpr IndexType OutputDimensions = OutDims;
172 static constexpr IndexType PaddedInputDimensions =
173 ceil_to_multiple<IndexType>(InputDimensions, MaxSimdWidth);
174 static constexpr IndexType PaddedOutputDimensions =
175 ceil_to_multiple<IndexType>(OutputDimensions, MaxSimdWidth);
177 using OutputBuffer = OutputType[PaddedOutputDimensions];
179 static_assert(PaddedInputDimensions >= LargeInputSize, "Something went wrong. This specialization should not have been chosen.");
181 #if defined (USE_AVX512)
182 static constexpr const IndexType InputSimdWidth = 64;
183 static constexpr const IndexType MaxNumOutputRegs = 16;
184 #elif defined (USE_AVX2)
185 static constexpr const IndexType InputSimdWidth = 32;
186 static constexpr const IndexType MaxNumOutputRegs = 8;
187 #elif defined (USE_SSSE3)
188 static constexpr const IndexType InputSimdWidth = 16;
189 static constexpr const IndexType MaxNumOutputRegs = 8;
190 #elif defined (USE_NEON)
191 static constexpr const IndexType InputSimdWidth = 8;
192 static constexpr const IndexType MaxNumOutputRegs = 8;
194 // The fallback implementation will not have permuted weights.
195 // We define these to avoid a lot of ifdefs later.
196 static constexpr const IndexType InputSimdWidth = 1;
197 static constexpr const IndexType MaxNumOutputRegs = 1;
200 // A big block is a region in the weight matrix of the size [PaddedInputDimensions, NumOutputRegs].
201 // A small block is a region of size [InputSimdWidth, 1]
203 static constexpr const IndexType NumOutputRegs = std::min(MaxNumOutputRegs, OutputDimensions);
204 static constexpr const IndexType SmallBlockSize = InputSimdWidth;
205 static constexpr const IndexType BigBlockSize = NumOutputRegs * PaddedInputDimensions;
206 static constexpr const IndexType NumSmallBlocksInBigBlock = BigBlockSize / SmallBlockSize;
207 static constexpr const IndexType NumSmallBlocksPerOutput = PaddedInputDimensions / SmallBlockSize;
208 static constexpr const IndexType NumBigBlocks = OutputDimensions / NumOutputRegs;
210 static_assert(OutputDimensions % NumOutputRegs == 0);
212 // Hash value embedded in the evaluation file
213 static constexpr std::uint32_t get_hash_value(std::uint32_t prevHash) {
214 std::uint32_t hashValue = 0xCC03DAE4u;
215 hashValue += OutputDimensions;
216 hashValue ^= prevHash >> 1;
217 hashValue ^= prevHash << 31;
222 Transposes the small blocks within a block.
223 Effectively means that weights can be traversed sequentially during inference.
225 static IndexType get_weight_index(IndexType i)
227 const IndexType smallBlock = (i / SmallBlockSize) % NumSmallBlocksInBigBlock;
228 const IndexType smallBlockCol = smallBlock / NumSmallBlocksPerOutput;
229 const IndexType smallBlockRow = smallBlock % NumSmallBlocksPerOutput;
230 const IndexType bigBlock = i / BigBlockSize;
231 const IndexType rest = i % SmallBlockSize;
233 const IndexType idx =
234 bigBlock * BigBlockSize
235 + smallBlockRow * SmallBlockSize * NumOutputRegs
236 + smallBlockCol * SmallBlockSize
242 // Read network parameters
243 bool read_parameters(std::istream& stream) {
244 for (IndexType i = 0; i < OutputDimensions; ++i)
245 biases[i] = read_little_endian<BiasType>(stream);
247 for (IndexType i = 0; i < OutputDimensions * PaddedInputDimensions; ++i)
248 weights[get_weight_index(i)] = read_little_endian<WeightType>(stream);
250 return !stream.fail();
253 // Write network parameters
254 bool write_parameters(std::ostream& stream) const {
255 for (IndexType i = 0; i < OutputDimensions; ++i)
256 write_little_endian<BiasType>(stream, biases[i]);
258 for (IndexType i = 0; i < OutputDimensions * PaddedInputDimensions; ++i)
259 write_little_endian<WeightType>(stream, weights[get_weight_index(i)]);
261 return !stream.fail();
264 // Forward propagation
265 const OutputType* propagate(
266 const InputType* input, OutputType* output) const {
268 #if defined (USE_AVX512)
269 using acc_vec_t = __m512i;
270 using bias_vec_t = __m128i;
271 using weight_vec_t = __m512i;
272 using in_vec_t = __m512i;
273 #define vec_zero _mm512_setzero_si512()
274 #define vec_add_dpbusd_32x2 Simd::m512_add_dpbusd_epi32x2
275 #define vec_hadd Simd::m512_hadd
276 #define vec_haddx4 Simd::m512_haddx4
277 #elif defined (USE_AVX2)
278 using acc_vec_t = __m256i;
279 using bias_vec_t = __m128i;
280 using weight_vec_t = __m256i;
281 using in_vec_t = __m256i;
282 #define vec_zero _mm256_setzero_si256()
283 #define vec_add_dpbusd_32x2 Simd::m256_add_dpbusd_epi32x2
284 #define vec_hadd Simd::m256_hadd
285 #define vec_haddx4 Simd::m256_haddx4
286 #elif defined (USE_SSSE3)
287 using acc_vec_t = __m128i;
288 using bias_vec_t = __m128i;
289 using weight_vec_t = __m128i;
290 using in_vec_t = __m128i;
291 #define vec_zero _mm_setzero_si128()
292 #define vec_add_dpbusd_32x2 Simd::m128_add_dpbusd_epi32x2
293 #define vec_hadd Simd::m128_hadd
294 #define vec_haddx4 Simd::m128_haddx4
295 #elif defined (USE_NEON)
296 using acc_vec_t = int32x4_t;
297 using bias_vec_t = int32x4_t;
298 using weight_vec_t = int8x8_t;
299 using in_vec_t = int8x8_t;
301 #define vec_add_dpbusd_32x2 Simd::neon_m128_add_dpbusd_epi32x2
302 #define vec_hadd Simd::neon_m128_hadd
303 #define vec_haddx4 Simd::neon_m128_haddx4
306 #if defined (USE_SSSE3) || defined (USE_NEON)
307 const in_vec_t* invec = reinterpret_cast<const in_vec_t*>(input);
309 // Perform accumulation to registers for each big block
310 for (IndexType bigBlock = 0; bigBlock < NumBigBlocks; ++bigBlock)
312 acc_vec_t acc[NumOutputRegs] = { vec_zero };
314 // Each big block has NumOutputRegs small blocks in each "row", one per register.
315 // We process two small blocks at a time to save on one addition without VNNI.
316 for (IndexType smallBlock = 0; smallBlock < NumSmallBlocksPerOutput; smallBlock += 2)
318 const weight_vec_t* weightvec =
319 reinterpret_cast<const weight_vec_t*>(
321 + bigBlock * BigBlockSize
322 + smallBlock * SmallBlockSize * NumOutputRegs);
324 const in_vec_t in0 = invec[smallBlock + 0];
325 const in_vec_t in1 = invec[smallBlock + 1];
327 for (IndexType k = 0; k < NumOutputRegs; ++k)
328 vec_add_dpbusd_32x2(acc[k], in0, weightvec[k], in1, weightvec[k + NumOutputRegs]);
331 // Horizontally add all accumulators.
332 if constexpr (NumOutputRegs % 4 == 0)
334 bias_vec_t* outputvec = reinterpret_cast<bias_vec_t*>(output);
335 const bias_vec_t* biasvec = reinterpret_cast<const bias_vec_t*>(biases);
337 for (IndexType k = 0; k < NumOutputRegs; k += 4)
339 const IndexType idx = (bigBlock * NumOutputRegs + k) / 4;
340 outputvec[idx] = vec_haddx4(acc[k+0], acc[k+1], acc[k+2], acc[k+3], biasvec[idx]);
345 for (IndexType k = 0; k < NumOutputRegs; ++k)
347 const IndexType idx = (bigBlock * NumOutputRegs + k);
348 output[idx] = vec_hadd(acc[k], biases[idx]);
354 # undef vec_add_dpbusd_32x2
358 // Use old implementation for the other architectures.
359 affine_transform_non_ssse3<
361 PaddedInputDimensions,
362 OutputDimensions>(output, weights, biases, input);
370 using BiasType = OutputType;
371 using WeightType = std::int8_t;
373 alignas(CacheLineSize) BiasType biases[OutputDimensions];
374 alignas(CacheLineSize) WeightType weights[OutputDimensions * PaddedInputDimensions];
377 template <IndexType InDims, IndexType OutDims>
378 class AffineTransform<InDims, OutDims, std::enable_if_t<(ceil_to_multiple<IndexType>(InDims, MaxSimdWidth) < LargeInputSize)>> {
382 using InputType = std::uint8_t;
383 using OutputType = std::int32_t;
385 // Number of input/output dimensions
386 static constexpr IndexType InputDimensions = InDims;
387 static constexpr IndexType OutputDimensions = OutDims;
389 static constexpr IndexType PaddedInputDimensions =
390 ceil_to_multiple<IndexType>(InputDimensions, MaxSimdWidth);
391 static constexpr IndexType PaddedOutputDimensions =
392 ceil_to_multiple<IndexType>(OutputDimensions, MaxSimdWidth);
394 using OutputBuffer = OutputType[PaddedOutputDimensions];
396 static_assert(PaddedInputDimensions < LargeInputSize, "Something went wrong. This specialization should not have been chosen.");
398 #if defined (USE_SSSE3)
399 static constexpr const IndexType OutputSimdWidth = SimdWidth / 4;
400 static constexpr const IndexType InputSimdWidth = SimdWidth;
403 // Hash value embedded in the evaluation file
404 static constexpr std::uint32_t get_hash_value(std::uint32_t prevHash) {
405 std::uint32_t hashValue = 0xCC03DAE4u;
406 hashValue += OutputDimensions;
407 hashValue ^= prevHash >> 1;
408 hashValue ^= prevHash << 31;
412 static IndexType get_weight_index_scrambled(IndexType i)
415 (i / 4) % (PaddedInputDimensions / 4) * OutputDimensions * 4 +
416 i / PaddedInputDimensions * 4 +
420 static IndexType get_weight_index(IndexType i)
422 #if defined (USE_SSSE3)
423 return get_weight_index_scrambled(i);
429 // Read network parameters
430 bool read_parameters(std::istream& stream) {
431 for (IndexType i = 0; i < OutputDimensions; ++i)
432 biases[i] = read_little_endian<BiasType>(stream);
433 for (IndexType i = 0; i < OutputDimensions * PaddedInputDimensions; ++i)
434 weights[get_weight_index(i)] = read_little_endian<WeightType>(stream);
436 return !stream.fail();
439 // Write network parameters
440 bool write_parameters(std::ostream& stream) const {
441 for (IndexType i = 0; i < OutputDimensions; ++i)
442 write_little_endian<BiasType>(stream, biases[i]);
444 for (IndexType i = 0; i < OutputDimensions * PaddedInputDimensions; ++i)
445 write_little_endian<WeightType>(stream, weights[get_weight_index(i)]);
447 return !stream.fail();
449 // Forward propagation
450 const OutputType* propagate(
451 const InputType* input, OutputType* output) const {
453 #if defined (USE_AVX2)
454 using vec_t = __m256i;
455 #define vec_setzero _mm256_setzero_si256
456 #define vec_set_32 _mm256_set1_epi32
457 #define vec_add_dpbusd_32 Simd::m256_add_dpbusd_epi32
458 #define vec_add_dpbusd_32x2 Simd::m256_add_dpbusd_epi32x2
459 #define vec_add_dpbusd_32x4 Simd::m256_add_dpbusd_epi32x4
460 #define vec_hadd Simd::m256_hadd
461 #define vec_haddx4 Simd::m256_haddx4
462 #elif defined (USE_SSSE3)
463 using vec_t = __m128i;
464 #define vec_setzero _mm_setzero_si128
465 #define vec_set_32 _mm_set1_epi32
466 #define vec_add_dpbusd_32 Simd::m128_add_dpbusd_epi32
467 #define vec_add_dpbusd_32x2 Simd::m128_add_dpbusd_epi32x2
468 #define vec_add_dpbusd_32x4 Simd::m128_add_dpbusd_epi32x4
469 #define vec_hadd Simd::m128_hadd
470 #define vec_haddx4 Simd::m128_haddx4
473 #if defined (USE_SSSE3)
474 const auto inputVector = reinterpret_cast<const vec_t*>(input);
476 static_assert(OutputDimensions % OutputSimdWidth == 0 || OutputDimensions == 1);
478 if constexpr (OutputDimensions % OutputSimdWidth == 0)
480 constexpr IndexType NumChunks = ceil_to_multiple<IndexType>(InputDimensions, 8) / 4;
481 constexpr IndexType NumRegs = OutputDimensions / OutputSimdWidth;
483 const auto input32 = reinterpret_cast<const std::int32_t*>(input);
484 const vec_t* biasvec = reinterpret_cast<const vec_t*>(biases);
486 for (IndexType k = 0; k < NumRegs; ++k)
489 for (IndexType i = 0; i < NumChunks; i += 2)
491 const vec_t in0 = vec_set_32(input32[i + 0]);
492 const vec_t in1 = vec_set_32(input32[i + 1]);
493 const auto col0 = reinterpret_cast<const vec_t*>(&weights[(i + 0) * OutputDimensions * 4]);
494 const auto col1 = reinterpret_cast<const vec_t*>(&weights[(i + 1) * OutputDimensions * 4]);
495 for (IndexType k = 0; k < NumRegs; ++k)
496 vec_add_dpbusd_32x2(acc[k], in0, col0[k], in1, col1[k]);
499 vec_t* outptr = reinterpret_cast<vec_t*>(output);
500 for (IndexType k = 0; k < NumRegs; ++k)
503 else if constexpr (OutputDimensions == 1)
505 constexpr IndexType NumChunks = PaddedInputDimensions / SimdWidth;
506 vec_t sum0 = vec_setzero();
507 const auto row0 = reinterpret_cast<const vec_t*>(&weights[0]);
509 for (int j = 0; j < (int)NumChunks; ++j)
511 const vec_t in = inputVector[j];
512 vec_add_dpbusd_32(sum0, in, row0[j]);
514 output[0] = vec_hadd(sum0, biases[0]);
519 # undef vec_add_dpbusd_32
520 # undef vec_add_dpbusd_32x2
521 # undef vec_add_dpbusd_32x4
525 // Use old implementation for the other architectures.
526 affine_transform_non_ssse3<
528 PaddedInputDimensions,
529 OutputDimensions>(output, weights, biases, input);
536 using BiasType = OutputType;
537 using WeightType = std::int8_t;
539 alignas(CacheLineSize) BiasType biases[OutputDimensions];
540 alignas(CacheLineSize) WeightType weights[OutputDimensions * PaddedInputDimensions];
543 } // namespace Stockfish::Eval::NNUE::Layers
545 #endif // #ifndef NNUE_LAYERS_AFFINE_TRANSFORM_H_INCLUDED