+#if SYS_OPENBSD
+#include <sys/param.h>
+#include <sys/sysctl.h>
+#include <machine/cpu.h>
+#endif
+
+const x264_cpu_name_t x264_cpu_names[] =
+{
+#if HAVE_MMX
+// {"MMX", X264_CPU_MMX}, // we don't support asm on mmx1 cpus anymore
+// {"CMOV", X264_CPU_CMOV}, // we require this unconditionally, so don't print it
+#define MMX2 X264_CPU_MMX|X264_CPU_MMX2|X264_CPU_CMOV
+ {"MMX2", MMX2},
+ {"MMXEXT", MMX2},
+ {"SSE", MMX2|X264_CPU_SSE},
+#define SSE2 MMX2|X264_CPU_SSE|X264_CPU_SSE2
+ {"SSE2Slow", SSE2|X264_CPU_SSE2_IS_SLOW},
+ {"SSE2", SSE2},
+ {"SSE2Fast", SSE2|X264_CPU_SSE2_IS_FAST},
+ {"SSE3", SSE2|X264_CPU_SSE3},
+ {"SSSE3", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3},
+ {"SSE4.1", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4},
+ {"SSE4", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4},
+ {"SSE4.2", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4|X264_CPU_SSE42},
+#define AVX SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4|X264_CPU_SSE42|X264_CPU_AVX
+ {"AVX", AVX},
+ {"XOP", AVX|X264_CPU_XOP},
+ {"FMA4", AVX|X264_CPU_FMA4},
+ {"FMA3", AVX|X264_CPU_FMA3},
+ {"AVX2", AVX|X264_CPU_FMA3|X264_CPU_AVX2},
+#undef AVX
+#undef SSE2
+#undef MMX2
+ {"Cache32", X264_CPU_CACHELINE_32},
+ {"Cache64", X264_CPU_CACHELINE_64},
+ {"LZCNT", X264_CPU_LZCNT},
+ {"BMI1", X264_CPU_BMI1},
+ {"BMI2", X264_CPU_BMI1|X264_CPU_BMI2},
+ {"SlowCTZ", X264_CPU_SLOW_CTZ},
+ {"SlowAtom", X264_CPU_SLOW_ATOM},
+ {"SlowPshufb", X264_CPU_SLOW_PSHUFB},
+ {"SlowPalignr", X264_CPU_SLOW_PALIGNR},
+ {"SlowShuffle", X264_CPU_SLOW_SHUFFLE},
+ {"UnalignedStack", X264_CPU_STACK_MOD4},
+#elif ARCH_PPC
+ {"Altivec", X264_CPU_ALTIVEC},
+#elif ARCH_ARM
+ {"ARMv6", X264_CPU_ARMV6},
+ {"NEON", X264_CPU_NEON},
+ {"FastNeonMRC", X264_CPU_FAST_NEON_MRC},
+#elif ARCH_AARCH64
+ {"ARMv8", X264_CPU_ARMV8},
+ {"NEON", X264_CPU_NEON},
+#elif ARCH_MIPS
+ {"MSA", X264_CPU_MSA},
+#endif
+ {"", 0},
+};