- reg [1:0] state = 2'd0;
- reg wait_req = 1'b1;
- reg wait_dtack = 1'b0;
-
- wire S0 = state == 2'd0 && c7m && !wait_req;
- wire Sr = state == 2'd0 && wait_req;
- wire S1 = state == 2'd1 && !c7m;
- wire S2 = state == 2'd1 && c7m;
- wire S3 = state == 2'd2 && !c7m && !wait_dtack;
- wire S4 = state == 2'd2 && c7m && !wait_dtack;
- wire Sw = state == 2'd2 && wait_dtack;
- wire S5 = state == 2'd3 && !c7m;
- wire S6 = state == 2'd3 && c7m;
- wire S7 = state == 2'd0 && !c7m && !wait_req;
-
- always @(*) begin
- LTCH_A_OE_n <= !(S1 || S2 || S3 || S4 || Sw || S5 || S6 || S7);
- LTCH_D_WR_OE_n <= !(!op_rw && (S3 || S4 || Sw || S5 || S6 || S7));