+// Bitboard type
+typedef uint64_t Bitboard;
+
+
+////
+//// Compiler specific defines
+////
+
+// Quiet a warning on Intel compiler
+#if !defined(__SIZEOF_INT__ )
+#define __SIZEOF_INT__ 0
+#endif
+
+// Check for 64 bits for different compilers: Intel, MSVC and gcc
+#if defined(__x86_64) || defined(_M_X64) || defined(_WIN64) || (__SIZEOF_INT__ > 4)
+#define IS_64BIT
+#endif
+
+#if defined(IS_64BIT) && (defined(__GNUC__) || defined(__INTEL_COMPILER))
+#define USE_BSFQ
+#endif
+
+// Cache line alignment specification
+#if defined(_MSC_VER) || defined(__INTEL_COMPILER)
+#define CACHE_LINE_ALIGNMENT __declspec(align(64))
+#else
+#define CACHE_LINE_ALIGNMENT __attribute__ ((aligned(64)))
+#endif
+
+// Define a __cpuid() function for gcc compilers, for Intel and MSVC
+// is already available as an intrinsic.
+#if defined(_MSC_VER)
+#include <intrin.h>
+#elif defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
+inline void __cpuid(int CPUInfo[4], int InfoType)
+{
+ int* eax = CPUInfo + 0;
+ int* ebx = CPUInfo + 1;
+ int* ecx = CPUInfo + 2;
+ int* edx = CPUInfo + 3;
+
+ *eax = InfoType;
+ *ecx = 0;
+ __asm__("cpuid" : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+ : "0" (*eax), "2" (*ecx));
+}
+#else
+inline void __cpuid(int CPUInfo[4], int)
+{
+ CPUInfo[0] = CPUInfo[1] = CPUInfo[2] = CPUInfo[3] = 0;
+}
+#endif
+