x86: AVX2 high bit-depth pixel_ssd

[x264] / common / cpu.h

diff --git a/common/cpu.h b/common/cpu.h
index 640856628b728a5b008686fcfac54e2cac8083d3..7f76e435b050e6b357b1fda0acb569f1f6ee4869 100644 (file)
--- a/common/cpu.h
+++ b/common/cpu.h
@@ -1,7 +1,7 @@
 /*****************************************************************************
  * cpu.h: cpu detection
  *****************************************************************************
- * Copyright (C) 2004-2011 x264 project
+ * Copyright (C) 2004-2013 x264 project
  *
  * Authors: Loren Merritt <lorenm@u.washington.edu>
  *
@@ -31,12 +31,22 @@ int      x264_cpu_num_processors( void );
 void     x264_cpu_emms( void );
 void     x264_cpu_sfence( void );
 #if HAVE_MMX
+/* There is no way to forbid the compiler from using float instructions
+ * before the emms so miscompilation could theoretically occur in the
+ * unlikely event that the compiler reorders emms and float instructions. */
+#if HAVE_X86_INLINE_ASM
+/* Clobbering memory makes the compiler less likely to reorder code. */
+#define x264_emms() asm volatile( "emms":::"memory","st","st(1)","st(2)", \
+                                  "st(3)","st(4)","st(5)","st(6)","st(7)" )
+#else
 #define x264_emms() x264_cpu_emms()
+#endif
 #else
 #define x264_emms()
 #endif
 #define x264_sfence x264_cpu_sfence
 void     x264_cpu_mask_misalign_sse( void );
+void     x264_safe_intel_cpu_indicator_init( void );
 
 /* kluge:
  * gcc can't give variables any greater alignment than the stack frame has.