sbfx r1, r9, #3, #13
sbfx r10, r4, #3, #13
#else
- sxth r8, r8
- sxth r7, r7
- sxth r9, r9
- sxth r4, r4
- asr r8, #3 @ block[0][0]
- asr r7, #3 @ block[0][1]
- asr r9, #3 @ block[0][2]
- asr r4, #3 @ block[0][3]
+ sxth r6, r8
+ sxth r12, r7
+ sxth r1, r9
+ sxth r10, r4
+ asr r6, #3 @ block[0][0]
+ asr r12, #3 @ block[0][1]
+ asr r1, #3 @ block[0][2]
+ asr r10, #3 @ block[0][3]
#endif
strh r6, [r0], #32
function ff_vp8_idct_dc_add4uv_armv6, export=1
push {r4, lr}
- bl ff_vp8_idct_dc_add_armv6
+ bl X(ff_vp8_idct_dc_add_armv6)
add r0, r0, #4
- bl ff_vp8_idct_dc_add_armv6
+ bl X(ff_vp8_idct_dc_add_armv6)
add r0, r0, r2, lsl #2
sub r0, r0, #4
- bl ff_vp8_idct_dc_add_armv6
+ bl X(ff_vp8_idct_dc_add_armv6)
add r0, r0, #4
- bl ff_vp8_idct_dc_add_armv6
+ bl X(ff_vp8_idct_dc_add_armv6)
pop {r4, pc}
endfunc
function ff_vp8_idct_dc_add4y_armv6, export=1
push {r4, lr}
- bl ff_vp8_idct_dc_add_armv6
+ bl X(ff_vp8_idct_dc_add_armv6)
add r0, r0, #4
- bl ff_vp8_idct_dc_add_armv6
+ bl X(ff_vp8_idct_dc_add_armv6)
add r0, r0, #4
- bl ff_vp8_idct_dc_add_armv6
+ bl X(ff_vp8_idct_dc_add_armv6)
add r0, r0, #4
- bl ff_vp8_idct_dc_add_armv6
+ bl X(ff_vp8_idct_dc_add_armv6)
pop {r4, pc}
endfunc
mov r4, #\size
stm r12, {r4, r5}
orr r12, r6, r7
- b vp8_put_\name\()_\hv\()_armv6 + 4
+ b bl_put_\name\()_\hv\()_armv6
endfunc
.endm
function vp8_put_epel_h6_armv6
push {r1, r4-r11, lr}
+bl_put_epel_h6_armv6:
sub r2, r2, #2
movrel lr, sixtap_filters_13245600 - 16
add lr, lr, r12, lsl #3
function vp8_put_epel_v6_armv6
push {r1, r4-r11, lr}
+bl_put_epel_v6_armv6:
movrel lr, sixtap_filters_13245600 - 16
add lr, lr, r12, lsl #3
str r3, [sp, #48]
function vp8_put_epel_h4_armv6
push {r1, r4-r11, lr}
+bl_put_epel_h4_armv6:
subs r2, r2, #1
movrel lr, fourtap_filters_1324 - 4
add lr, lr, r12, lsl #2
function vp8_put_epel_v4_armv6
push {r1, r4-r11, lr}
+bl_put_epel_v4_armv6:
movrel lr, fourtap_filters_1324 - 4
add lr, lr, r12, lsl #2
ldm lr, {r5, r6}
function vp8_put_bilin_h_armv6
push {r1, r4-r11, lr}
+bl_put_bilin_h_armv6:
rsb r5, r12, r12, lsl #16
ldr r12, [sp, #44]
sub r3, r3, r4
function vp8_put_bilin_v_armv6
push {r1, r4-r11, lr}
+bl_put_bilin_v_armv6:
rsb r5, r12, r12, lsl #16
ldr r12, [sp, #44]
add r5, r5, #8