see <http://developer.apple.com/technotes/tn/tn2087.html>
and <http://developer.apple.com/technotes/tn/tn2086.html>
*/
-static void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
+static void clear_blocks_dcbz32_ppc(int16_t *blocks)
{
register int misal = ((unsigned long)blocks & 0x00000010);
register int i = 0;
((unsigned long*)blocks)[3] = 0L;
i += 16;
}
- for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) {
+ for ( ; i < sizeof(int16_t)*6*64-31 ; i += 32) {
__asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
}
if (misal) {
/* same as above, when dcbzl clear a whole 128B cache line
i.e. the PPC970 aka G5 */
#if HAVE_DCBZL
-static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
+static void clear_blocks_dcbz128_ppc(int16_t *blocks)
{
register int misal = ((unsigned long)blocks & 0x0000007f);
register int i = 0;
// we could probably also optimize this case,
// but there's not much point as the machines
// aren't available yet (2003-06-26)
- memset(blocks, 0, sizeof(DCTELEM)*6*64);
+ memset(blocks, 0, sizeof(int16_t)*6*64);
}
else
- for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
+ for ( ; i < sizeof(int16_t)*6*64 ; i += 128) {
__asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
}
}
#else
-static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
+static void clear_blocks_dcbz128_ppc(int16_t *blocks)
{
- memset(blocks, 0, sizeof(DCTELEM)*6*64);
+ memset(blocks, 0, sizeof(int16_t)*6*64);
}
#endif