/* signed 16x16 -> 32 multiply add accumulate */
#define MAC16(rt, ra, rb) \
- asm ("maclhw %0, %2, %3" : "=r" (rt) : "0" (rt), "r" (ra), "r" (rb));
+ __asm__ ("maclhw %0, %2, %3" : "=r" (rt) : "0" (rt), "r" (ra), "r" (rb));
/* signed 16x16 -> 32 multiply */
#define MUL16(rt, ra, rb) \
- asm ("mullhw %0, %1, %2" : "=r" (rt) : "r" (ra), "r" (rb));
+ __asm__ ("mullhw %0, %1, %2" : "=r" (rt) : "r" (ra), "r" (rb));
#else
col[56] = ((a0 - b0) >> COL_SHIFT);
}
-void simple_idct_put(uint8_t *dest, int line_size, DCTELEM *block)
+void ff_simple_idct_put(uint8_t *dest, int line_size, DCTELEM *block)
{
int i;
for(i=0; i<8; i++)
idctSparseColPut(dest + i, line_size, block + i);
}
-void simple_idct_add(uint8_t *dest, int line_size, DCTELEM *block)
+void ff_simple_idct_add(uint8_t *dest, int line_size, DCTELEM *block)
{
int i;
for(i=0; i<8; i++)
idctSparseColAdd(dest + i, line_size, block + i);
}
-void simple_idct(DCTELEM *block)
+void ff_simple_idct(DCTELEM *block)
{
int i;
for(i=0; i<8; i++)
/* XXX: I think a 1.0/sqrt(2) normalization should be needed to
compensate the extra butterfly stage - I don't have the full DV
specification */
-void simple_idct248_put(uint8_t *dest, int line_size, DCTELEM *block)
+void ff_simple_idct248_put(uint8_t *dest, int line_size, DCTELEM *block)
{
int i;
DCTELEM *ptr;
row[3]= (c0 - c1) >> R_SHIFT;
}
-void simple_idct84_add(uint8_t *dest, int line_size, DCTELEM *block)
+void ff_simple_idct84_add(uint8_t *dest, int line_size, DCTELEM *block)
{
int i;
}
}
-void simple_idct48_add(uint8_t *dest, int line_size, DCTELEM *block)
+void ff_simple_idct48_add(uint8_t *dest, int line_size, DCTELEM *block)
{
int i;
}
}
+void ff_simple_idct44_add(uint8_t *dest, int line_size, DCTELEM *block)
+{
+ int i;
+
+ /* IDCT4 on each line */
+ for(i=0; i<4; i++) {
+ idct4row(block + i*8);
+ }
+
+ /* IDCT4 and store */
+ for(i=0; i<4; i++){
+ idct4col_add(dest + i, line_size, block + i);
+ }
+}