#define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
#define LD_H(RTYPE, psrc) *((RTYPE *)(psrc))
+#define LD_UH(...) LD_H(v8u16, __VA_ARGS__)
#define LD_SH(...) LD_H(v8i16, __VA_ARGS__)
#define LD_W(RTYPE, psrc) *((RTYPE *)(psrc))
+#define LD_UW(...) LD_W(v4u32, __VA_ARGS__)
#define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
#define ST_B(RTYPE, in, pdst) *((RTYPE *)(pdst)) = (in)
#define ST_UB(...) ST_B(v16u8, __VA_ARGS__)
+#define ST_SB(...) ST_B(v16i8, __VA_ARGS__)
#define ST_H(RTYPE, in, pdst) *((RTYPE *)(pdst)) = (in)
+#define ST_UH(...) ST_H(v8u16, __VA_ARGS__)
#define ST_SH(...) ST_H(v8i16, __VA_ARGS__)
#define ST_W(RTYPE, in, pdst) *((RTYPE *)(pdst)) = (in)
+#define ST_UW(...) ST_W(v4u32, __VA_ARGS__)
#define ST_SW(...) ST_W(v4i32, __VA_ARGS__)
#if (__mips_isa_rev >= 6)
out3 = LW((psrc) + 3 * stride); \
}
+/* Description : Load double words with stride
+ Arguments : Inputs - psrc (source pointer to load from)
+ - stride
+ Outputs - out0, out1
+ Details : Loads double word in 'out0' from (psrc)
+ Loads double word in 'out1' from (psrc + stride)
+*/
+#define LD2(psrc, stride, out0, out1) \
+{ \
+ out0 = LD((psrc)); \
+ out1 = LD((psrc) + stride); \
+}
+#define LD4(psrc, stride, out0, out1, out2, out3) \
+{ \
+ LD2((psrc), stride, out0, out1); \
+ LD2((psrc) + 2 * stride, stride, out2, out3); \
+}
+
/* Description : Store 4 words with stride
Arguments : Inputs - in0, in1, in2, in3, pdst, stride
Details : Stores word from 'in0' to (pdst)
LD_B2(RTYPE, (psrc), stride, out0, out1); \
out2 = LD_B(RTYPE, (psrc) + 2 * stride); \
}
+#define LD_UB3(...) LD_B3(v16u8, __VA_ARGS__)
#define LD_SB3(...) LD_B3(v16i8, __VA_ARGS__)
#define LD_B4(RTYPE, psrc, stride, out0, out1, out2, out3) \
#define LD_UB8(...) LD_B8(v16u8, __VA_ARGS__)
#define LD_SB8(...) LD_B8(v16i8, __VA_ARGS__)
+/* Description : Load vectors with 8 halfword elements with stride
+ Arguments : Inputs - psrc (source pointer to load from)
+ - stride
+ Outputs - out0, out1
+ Details : Loads 8 halfword elements in 'out0' from (psrc)
+ Loads 8 halfword elements in 'out1' from (psrc + stride)
+*/
+#define LD_H2(RTYPE, psrc, stride, out0, out1) \
+{ \
+ out0 = LD_H(RTYPE, (psrc)); \
+ out1 = LD_H(RTYPE, (psrc) + (stride)); \
+}
+#define LD_UH2(...) LD_H2(v8u16, __VA_ARGS__)
+#define LD_SH2(...) LD_H2(v8i16, __VA_ARGS__)
+
+#define LD_H4(RTYPE, psrc, stride, out0, out1, out2, out3) \
+{ \
+ LD_H2(RTYPE, (psrc), stride, out0, out1); \
+ LD_H2(RTYPE, (psrc) + 2 * stride, stride, out2, out3); \
+}
+#define LD_UH4(...) LD_H4(v8u16, __VA_ARGS__)
+#define LD_SH4(...) LD_H4(v8i16, __VA_ARGS__)
+
+#define LD_H6(RTYPE, psrc, stride, out0, out1, out2, out3, out4, out5) \
+{ \
+ LD_H4(RTYPE, (psrc), stride, out0, out1, out2, out3); \
+ LD_H2(RTYPE, (psrc) + 4 * stride, stride, out4, out5); \
+}
+#define LD_UH6(...) LD_H6(v8u16, __VA_ARGS__)
+#define LD_SH6(...) LD_H6(v8i16, __VA_ARGS__)
+
+#define LD_H8(RTYPE, psrc, stride, \
+ out0, out1, out2, out3, out4, out5, out6, out7) \
+{ \
+ LD_H4(RTYPE, (psrc), stride, out0, out1, out2, out3); \
+ LD_H4(RTYPE, (psrc) + 4 * stride, stride, out4, out5, out6, out7); \
+}
+#define LD_UH8(...) LD_H8(v8u16, __VA_ARGS__)
+#define LD_SH8(...) LD_H8(v8i16, __VA_ARGS__)
+
+#define LD_H16(RTYPE, psrc, stride, \
+ out0, out1, out2, out3, out4, out5, out6, out7, \
+ out8, out9, out10, out11, out12, out13, out14, out15) \
+{ \
+ LD_H8(RTYPE, (psrc), stride, \
+ out0, out1, out2, out3, out4, out5, out6, out7); \
+ LD_H8(RTYPE, (psrc) + 8 * stride, stride, \
+ out8, out9, out10, out11, out12, out13, out14, out15); \
+}
+#define LD_SH16(...) LD_H16(v8i16, __VA_ARGS__)
+
+/* Description : Load 2 vectors of signed word elements with stride
+ Arguments : Inputs - psrc (source pointer to load from)
+ - stride
+ Outputs - out0, out1
+ Return Type - signed word
+*/
+#define LD_SW2(psrc, stride, out0, out1) \
+{ \
+ out0 = LD_SW((psrc)); \
+ out1 = LD_SW((psrc) + stride); \
+}
+
/* Description : Store vectors of 16 byte elements with stride
Arguments : Inputs - in0, in1, stride
Outputs - pdst (destination pointer to store to)
\
SW4(out0_m, out1_m, out2_m, out3_m, pblk_4x4_m, stride); \
}
+#define ST4x8_UB(in0, in1, pdst, stride) \
+{ \
+ uint8_t *pblk_4x8 = (uint8_t *) (pdst); \
+ \
+ ST4x4_UB(in0, in0, 0, 1, 2, 3, pblk_4x8, stride); \
+ ST4x4_UB(in1, in1, 0, 1, 2, 3, pblk_4x8 + 4 * stride, stride); \
+}
+
+/* Description : Store as 6x4 byte block to destination memory from input
+ vectors
+ Arguments : Inputs - in0, in1, pdst, stride
+ Return Type - unsigned byte
+ Details : Index 0 word element from input vector 'in0' is copied and
+ stored on first line followed by index 2 halfword element
+ Index 2 word element from input vector 'in0' is copied and
+ stored on second line followed by index 2 halfword element
+ Index 0 word element from input vector 'in1' is copied and
+ stored on third line followed by index 2 halfword element
+ Index 2 word element from input vector 'in1' is copied and
+ stored on fourth line followed by index 2 halfword element
+*/
+#define ST6x4_UB(in0, in1, pdst, stride) \
+{ \
+ uint32_t out0_m, out1_m, out2_m, out3_m; \
+ uint16_t out4_m, out5_m, out6_m, out7_m; \
+ uint8_t *pblk_6x4_m = (uint8_t *) (pdst); \
+ \
+ out0_m = __msa_copy_u_w((v4i32) in0, 0); \
+ out1_m = __msa_copy_u_w((v4i32) in0, 2); \
+ out2_m = __msa_copy_u_w((v4i32) in1, 0); \
+ out3_m = __msa_copy_u_w((v4i32) in1, 2); \
+ \
+ out4_m = __msa_copy_u_h((v8i16) in0, 2); \
+ out5_m = __msa_copy_u_h((v8i16) in0, 6); \
+ out6_m = __msa_copy_u_h((v8i16) in1, 2); \
+ out7_m = __msa_copy_u_h((v8i16) in1, 6); \
+ \
+ SW(out0_m, pblk_6x4_m); \
+ SH(out4_m, (pblk_6x4_m + 4)); \
+ pblk_6x4_m += stride; \
+ SW(out1_m, pblk_6x4_m); \
+ SH(out5_m, (pblk_6x4_m + 4)); \
+ pblk_6x4_m += stride; \
+ SW(out2_m, pblk_6x4_m); \
+ SH(out6_m, (pblk_6x4_m + 4)); \
+ pblk_6x4_m += stride; \
+ SW(out3_m, pblk_6x4_m); \
+ SH(out7_m, (pblk_6x4_m + 4)); \
+}
+
+/* Description : Store as 8x1 byte block to destination memory from input vector
+ Arguments : Inputs - in, pdst
+ Details : Index 0 double word element from input vector 'in' is copied
+ and stored to destination memory at (pdst)
+*/
+#define ST8x1_UB(in, pdst) \
+{ \
+ uint64_t out0_m; \
+ out0_m = __msa_copy_u_d((v2i64) in, 0); \
+ SD(out0_m, pdst); \
+}
/* Description : Store as 8x2 byte block to destination memory from input vector
Arguments : Inputs - in, pdst, stride
ST8x4_UB(in0, in1, pblk_8x8_m, stride); \
ST8x4_UB(in2, in3, pblk_8x8_m + 4 * stride, stride); \
}
+#define ST12x4_UB(in0, in1, in2, pdst, stride) \
+{ \
+ uint8_t *pblk_12x4_m = (uint8_t *) (pdst); \
+ \
+ /* left 8x4 */ \
+ ST8x4_UB(in0, in1, pblk_12x4_m, stride); \
+ /* right 4x4 */ \
+ ST4x4_UB(in2, in2, 0, 1, 2, 3, pblk_12x4_m + 8, stride); \
+}
/* Description : Store as 12x8 byte block to destination memory from
input vectors
}
#define SLDI_B4_0_SB(...) SLDI_B4_0(v16i8, __VA_ARGS__)
+/* Description : Immediate number of columns to slide
+ Arguments : Inputs - in0_0, in0_1, in1_0, in1_1, slide_val
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Byte elements from 'in0_0' vector are slide into 'in1_0' by
+ number of elements specified by 'slide_val'
+*/
+#define SLDI_B2(RTYPE, in0_0, in0_1, in1_0, in1_1, out0, out1, slide_val) \
+{ \
+ out0 = (RTYPE) __msa_sldi_b((v16i8) in0_0, (v16i8) in1_0, slide_val); \
+ out1 = (RTYPE) __msa_sldi_b((v16i8) in0_1, (v16i8) in1_1, slide_val); \
+}
+#define SLDI_B2_UB(...) SLDI_B2(v16u8, __VA_ARGS__)
+#define SLDI_B2_SB(...) SLDI_B2(v16i8, __VA_ARGS__)
+#define SLDI_B2_SH(...) SLDI_B2(v8i16, __VA_ARGS__)
+
+
/* Description : Shuffle byte vector elements as per mask vector
Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
Outputs - out0, out1
}
#define DOTP_SB4_SH(...) DOTP_SB4(v8i16, __VA_ARGS__)
+/* Description : Dot product of halfword vector elements
+ Arguments : Inputs - mult0, mult1
+ cnst0, cnst1
+ Outputs - out0, out1
+ Return Type - signed word
+ Details : Signed halfword elements from mult0 are multiplied with
+ signed halfword elements from cnst0 producing a result
+ twice the size of input i.e. signed word.
+ Then this multiplication results of adjacent odd-even elements
+ are added together and stored to the out vector
+ (2 signed word results)
+*/
+#define DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) \
+{ \
+ out0 = (RTYPE) __msa_dotp_s_w((v8i16) mult0, (v8i16) cnst0); \
+ out1 = (RTYPE) __msa_dotp_s_w((v8i16) mult1, (v8i16) cnst1); \
+}
+#define DOTP_SH2_SW(...) DOTP_SH2(v4i32, __VA_ARGS__)
+
+#define DOTP_SH4(RTYPE, mult0, mult1, mult2, mult3, \
+ cnst0, cnst1, cnst2, cnst3, \
+ out0, out1, out2, out3) \
+{ \
+ DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1); \
+ DOTP_SH2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3); \
+}
+#define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__)
+
/* Description : Dot product & addition of byte vector elements
Arguments : Inputs - mult0, mult1
cnst0, cnst1
}
#define DPADD_SH2_SW(...) DPADD_SH2(v4i32, __VA_ARGS__)
+#define DPADD_SH4(RTYPE, mult0, mult1, mult2, mult3, \
+ cnst0, cnst1, cnst2, cnst3, out0, out1, out2, out3) \
+{ \
+ DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1); \
+ DPADD_SH2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3); \
+}
+#define DPADD_SH4_SW(...) DPADD_SH4(v4i32, __VA_ARGS__)
+
/* Description : Clips all halfword elements of input vector between min & max
out = ((in) < (min)) ? (min) : (((in) > (max)) ? (max) : (in))
Arguments : Inputs - in (input vector)
#define HSUB_UB2_UH(...) HSUB_UB2(v8u16, __VA_ARGS__)
#define HSUB_UB2_SH(...) HSUB_UB2(v8i16, __VA_ARGS__)
+#define INSERT_W4(RTYPE, in0, in1, in2, in3, out) \
+{ \
+ out = (RTYPE) __msa_insert_w((v4i32) out, 0, in0); \
+ out = (RTYPE) __msa_insert_w((v4i32) out, 1, in1); \
+ out = (RTYPE) __msa_insert_w((v4i32) out, 2, in2); \
+ out = (RTYPE) __msa_insert_w((v4i32) out, 3, in3); \
+}
+#define INSERT_W4_UB(...) INSERT_W4(v16u8, __VA_ARGS__)
+#define INSERT_W4_SB(...) INSERT_W4(v16i8, __VA_ARGS__)
+#define INSERT_W4_SW(...) INSERT_W4(v4i32, __VA_ARGS__)
+
+/* Description : Insert specified double word elements from input vectors to 1
+ destination vector
+ Arguments : Inputs - in0, in1 (2 input vectors)
+ Outputs - out (output vector)
+ Return Type - as per RTYPE
+*/
+#define INSERT_D2(RTYPE, in0, in1, out) \
+{ \
+ out = (RTYPE) __msa_insert_d((v2i64) out, 0, in0); \
+ out = (RTYPE) __msa_insert_d((v2i64) out, 1, in1); \
+}
+#define INSERT_D2_UB(...) INSERT_D2(v16u8, __VA_ARGS__)
+#define INSERT_D2_SB(...) INSERT_D2(v16i8, __VA_ARGS__)
+#define INSERT_D2_SD(...) INSERT_D2(v2i64, __VA_ARGS__)
+
/* Description : Interleave even halfword elements from vectors
Arguments : Inputs - in0, in1, in2, in3
Outputs - out0, out1
out1 = (RTYPE) __msa_ilvl_h((v8i16) in2, (v8i16) in3); \
}
#define ILVL_H2_SH(...) ILVL_H2(v8i16, __VA_ARGS__)
+#define ILVL_H2_SW(...) ILVL_H2(v4i32, __VA_ARGS__)
#define ILVL_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
out0, out1, out2, out3) \
#define ILVR_B2_SB(...) ILVR_B2(v16i8, __VA_ARGS__)
#define ILVR_B2_UH(...) ILVR_B2(v8u16, __VA_ARGS__)
#define ILVR_B2_SH(...) ILVR_B2(v8i16, __VA_ARGS__)
+#define ILVR_B2_SW(...) ILVR_B2(v4i32, __VA_ARGS__)
+
+#define ILVR_B3(RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2) \
+{ \
+ ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1); \
+ out2 = (RTYPE) __msa_ilvr_b((v16i8) in4, (v16i8) in5); \
+}
+#define ILVR_B3_UB(...) ILVR_B3(v16u8, __VA_ARGS__)
+#define ILVR_B3_UH(...) ILVR_B3(v8u16, __VA_ARGS__)
+#define ILVR_B3_SH(...) ILVR_B3(v8i16, __VA_ARGS__)
#define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
out0, out1, out2, out3) \
out1 = (RTYPE) __msa_ilvr_h((v8i16) in2, (v8i16) in3); \
}
#define ILVR_H2_SH(...) ILVR_H2(v8i16, __VA_ARGS__)
+#define ILVR_H2_SW(...) ILVR_H2(v4i32, __VA_ARGS__)
#define ILVR_H3(RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2) \
{ \
out0 = (RTYPE) __msa_ilvr_w((v4i32) in0, (v4i32) in1); \
out1 = (RTYPE) __msa_ilvl_w((v4i32) in0, (v4i32) in1); \
}
+#define ILVRL_W2_UB(...) ILVRL_W2(v16u8, __VA_ARGS__)
#define ILVRL_W2_SH(...) ILVRL_W2(v8i16, __VA_ARGS__)
+#define ILVRL_W2_SW(...) ILVRL_W2(v4i32, __VA_ARGS__)
/* Description : Maximum values between signed elements of vector and
5-bit signed immediate value are copied to the output vector
}
#define SAT_SH4_SH(...) SAT_SH4(v8i16, __VA_ARGS__)
+/* Description : Saturate the word element values to the max
+ unsigned value of (sat_val+1 bits)
+ The element data width remains unchanged
+ Arguments : Inputs - in0, in1, in2, in3, sat_val
+ Outputs - in0, in1, in2, in3 (in place)
+ Return Type - unsigned word
+ Details : Each unsigned word element from 'in0' is saturated to the
+ value generated with (sat_val+1) bit range
+ Results are in placed to original vectors
+*/
+#define SAT_SW2(RTYPE, in0, in1, sat_val) \
+{ \
+ in0 = (RTYPE) __msa_sat_s_w((v4i32) in0, sat_val); \
+ in1 = (RTYPE) __msa_sat_s_w((v4i32) in1, sat_val); \
+}
+#define SAT_SW2_SW(...) SAT_SW2(v4i32, __VA_ARGS__)
+
+#define SAT_SW4(RTYPE, in0, in1, in2, in3, sat_val) \
+{ \
+ SAT_SW2(RTYPE, in0, in1, sat_val); \
+ SAT_SW2(RTYPE, in2, in3, sat_val); \
+}
+#define SAT_SW4_SW(...) SAT_SW4(v4i32, __VA_ARGS__)
+
/* Description : Indexed halfword element values are replicated to all
elements in output vector
Arguments : Inputs - in, idx0, idx1
out0 = (RTYPE) __msa_splati_h((v8i16) in, idx0); \
out1 = (RTYPE) __msa_splati_h((v8i16) in, idx1); \
}
+#define SPLATI_H2_SB(...) SPLATI_H2(v16i8, __VA_ARGS__)
#define SPLATI_H2_SH(...) SPLATI_H2(v8i16, __VA_ARGS__)
#define SPLATI_H4(RTYPE, in, idx0, idx1, idx2, idx3, \
out0 = (RTYPE) __msa_splati_w((v4i32) in, stidx); \
out1 = (RTYPE) __msa_splati_w((v4i32) in, (stidx+1)); \
}
+#define SPLATI_W2_SH(...) SPLATI_W2(v8i16, __VA_ARGS__)
#define SPLATI_W2_SW(...) SPLATI_W2(v4i32, __VA_ARGS__)
#define SPLATI_W4(RTYPE, in, out0, out1, out2, out3) \
SPLATI_W2(RTYPE, in, 0, out0, out1); \
SPLATI_W2(RTYPE, in, 2, out2, out3); \
}
+#define SPLATI_W4_SH(...) SPLATI_W4(v8i16, __VA_ARGS__)
#define SPLATI_W4_SW(...) SPLATI_W4(v4i32, __VA_ARGS__)
/* Description : Pack even byte elements of vector pairs
}
#define PCKEV_B4_SB(...) PCKEV_B4(v16i8, __VA_ARGS__)
#define PCKEV_B4_UB(...) PCKEV_B4(v16u8, __VA_ARGS__)
+#define PCKEV_B4_SH(...) PCKEV_B4(v8i16, __VA_ARGS__)
+#define PCKEV_B4_SW(...) PCKEV_B4(v4i32, __VA_ARGS__)
/* Description : Pack even halfword elements of vector pairs
Arguments : Inputs - in0, in1, in2, in3
#define PCKEV_H4_SH(...) PCKEV_H4(v8i16, __VA_ARGS__)
#define PCKEV_H4_SW(...) PCKEV_H4(v4i32, __VA_ARGS__)
+/* Description : Pack even double word elements of vector pairs
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - unsigned byte
+ Details : Even double elements of in0 are copied to the left half of
+ out0 & even double elements of in1 are copied to the right
+ half of out0.
+ Even double elements of in2 are copied to the left half of
+ out1 & even double elements of in3 are copied to the right
+ half of out1.
+*/
+#define PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1) \
+{ \
+ out0 = (RTYPE) __msa_pckev_d((v2i64) in0, (v2i64) in1); \
+ out1 = (RTYPE) __msa_pckev_d((v2i64) in2, (v2i64) in3); \
+}
+#define PCKEV_D2_UB(...) PCKEV_D2(v16u8, __VA_ARGS__)
+#define PCKEV_D2_SB(...) PCKEV_D2(v16i8, __VA_ARGS__)
+#define PCKEV_D2_SH(...) PCKEV_D2(v8i16, __VA_ARGS__)
+
+#define PCKEV_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3) \
+{ \
+ PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1); \
+ PCKEV_D2(RTYPE, in4, in5, in6, in7, out2, out3); \
+}
+#define PCKEV_D4_UB(...) PCKEV_D4(v16u8, __VA_ARGS__)
+
/* Description : Each byte element is logically xor'ed with immediate 128
Arguments : Inputs - in0, in1
Outputs - in0, in1 (in-place)
in0 = (RTYPE) __msa_xori_b((v16u8) in0, 128); \
in1 = (RTYPE) __msa_xori_b((v16u8) in1, 128); \
}
+#define XORI_B2_128_UB(...) XORI_B2_128(v16u8, __VA_ARGS__)
#define XORI_B2_128_SB(...) XORI_B2_128(v16i8, __VA_ARGS__)
+#define XORI_B2_128_SH(...) XORI_B2_128(v8i16, __VA_ARGS__)
#define XORI_B3_128(RTYPE, in0, in1, in2) \
{ \
}
#define XORI_B5_128_SB(...) XORI_B5_128(v16i8, __VA_ARGS__)
+#define XORI_B6_128(RTYPE, in0, in1, in2, in3, in4, in5) \
+{ \
+ XORI_B4_128(RTYPE, in0, in1, in2, in3); \
+ XORI_B2_128(RTYPE, in4, in5); \
+}
+#define XORI_B6_128_SB(...) XORI_B6_128(v16i8, __VA_ARGS__)
+
#define XORI_B7_128(RTYPE, in0, in1, in2, in3, in4, in5, in6) \
{ \
XORI_B4_128(RTYPE, in0, in1, in2, in3); \
}
#define SRAR_H4_UH(...) SRAR_H4(v8u16, __VA_ARGS__)
#define SRAR_H4_SH(...) SRAR_H4(v8i16, __VA_ARGS__)
+
+/* Description : Shift right arithmetic rounded words
+ Arguments : Inputs - in0, in1, shift
+ Outputs - in0, in1, (in place)
+ Return Type - as per RTYPE
+ Details : Each element of vector 'in0' is shifted right arithmetic by
+ number of bits respective element holds in vector 'shift'.
+ The last discarded bit is added to shifted value for rounding
+ and the result is in place written to 'in0'
+ Here, 'shift' is a vector passed in
+ Similar for other pairs
+*/
+#define SRAR_W2(RTYPE, in0, in1, shift) \
+{ \
+ in0 = (RTYPE) __msa_srar_w((v4i32) in0, (v4i32) shift); \
+ in1 = (RTYPE) __msa_srar_w((v4i32) in1, (v4i32) shift); \
+}
+#define SRAR_W2_SW(...) SRAR_W2(v4i32, __VA_ARGS__)
+
+#define SRAR_W4(RTYPE, in0, in1, in2, in3, shift) \
+{ \
+ SRAR_W2(RTYPE, in0, in1, shift) \
+ SRAR_W2(RTYPE, in2, in3, shift) \
+}
+#define SRAR_W4_SW(...) SRAR_W4(v4i32, __VA_ARGS__)
+
+/* Description : Shift right arithmetic rounded (immediate)
+ Arguments : Inputs - in0, in1, in2, in3, shift
+ Outputs - in0, in1, in2, in3 (in place)
+ Return Type - as per RTYPE
+ Details : Each element of vector 'in0' is shifted right arithmetic by
+ value in 'shift'.
+ The last discarded bit is added to shifted value for rounding
+ and the result is in place written to 'in0'
+ Similar for other pairs
+*/
+#define SRARI_H2(RTYPE, in0, in1, shift) \
+{ \
+ in0 = (RTYPE) __msa_srari_h((v8i16) in0, shift); \
+ in1 = (RTYPE) __msa_srari_h((v8i16) in1, shift); \
+}
+#define SRARI_H2_UH(...) SRARI_H2(v8u16, __VA_ARGS__)
+#define SRARI_H2_SH(...) SRARI_H2(v8i16, __VA_ARGS__)
+
+#define SRARI_H4(RTYPE, in0, in1, in2, in3, shift) \
+{ \
+ SRARI_H2(RTYPE, in0, in1, shift); \
+ SRARI_H2(RTYPE, in2, in3, shift); \
+}
+#define SRARI_H4_UH(...) SRARI_H4(v8u16, __VA_ARGS__)
+#define SRARI_H4_SH(...) SRARI_H4(v8i16, __VA_ARGS__)
+
/* Description : Shift right arithmetic rounded (immediate)
Arguments : Inputs - in0, in1, shift
Outputs - in0, in1 (in place)
MUL2(in4, in5, in6, in7, out2, out3); \
}
+/* Description : Addition of 2 pairs of vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Details : Each element from 2 pairs vectors is added and 2 results are
+ produced
+*/
+#define ADD2(in0, in1, in2, in3, out0, out1) \
+{ \
+ out0 = in0 + in1; \
+ out1 = in2 + in3; \
+}
+#define ADD4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3) \
+{ \
+ ADD2(in0, in1, in2, in3, out0, out1); \
+ ADD2(in4, in5, in6, in7, out2, out3); \
+}
+
/* Description : Zero extend unsigned byte elements to halfword elements
Arguments : Inputs - in (1 input unsigned byte vector)
Outputs - out0, out1 (unsigned 2 halfword vectors)
ILVRL_B2_SH(zero_m, in, out0, out1); \
}
+/* Description : Sign extend halfword elements from input vector and return
+ result in pair of vectors
+ Arguments : Inputs - in (1 input halfword vector)
+ Outputs - out0, out1 (sign extended 2 word vectors)
+ Return Type - signed word
+ Details : Sign bit of halfword elements from input vector 'in' is
+ extracted and interleaved right with same vector 'in0' to
+ generate 4 signed word elements in 'out0'
+ Then interleaved left with same vector 'in0' to
+ generate 4 signed word elements in 'out1'
+*/
+#define UNPCK_SH_SW(in, out0, out1) \
+{ \
+ v8i16 tmp_m; \
+ \
+ tmp_m = __msa_clti_s_h((v8i16) in, 0); \
+ ILVRL_H2_SW(tmp_m, in, out0, out1); \
+}
+
+/* Description : Butterfly of 4 input vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1, out2, out3
+ Details : Butterfly operation
+*/
+#define BUTTERFLY_4(in0, in1, in2, in3, out0, out1, out2, out3) \
+{ \
+ out0 = in0 + in3; \
+ out1 = in1 + in2; \
+ \
+ out2 = in1 - in2; \
+ out3 = in0 - in3; \
+}
+
/* Description : Transposes input 4x4 byte block
Arguments : Inputs - in0, in1, in2, in3 (input 4x4 byte block)
Outputs - out0, out1, out2, out3 (output 4x4 byte block)
out7 = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
}
+/* Description : Transposes 8x8 block with half word elements in vectors
+ Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
+ Outputs - out0, out1, out2, out3, out4, out5, out6, out7
+ Return Type - signed halfword
+ Details :
+*/
+#define TRANSPOSE8x8_H(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3, out4, out5, out6, out7) \
+{ \
+ v8i16 s0_m, s1_m; \
+ v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
+ v8i16 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \
+ \
+ ILVR_H2_SH(in6, in4, in7, in5, s0_m, s1_m); \
+ ILVRL_H2_SH(s1_m, s0_m, tmp0_m, tmp1_m); \
+ ILVL_H2_SH(in6, in4, in7, in5, s0_m, s1_m); \
+ ILVRL_H2_SH(s1_m, s0_m, tmp2_m, tmp3_m); \
+ ILVR_H2_SH(in2, in0, in3, in1, s0_m, s1_m); \
+ ILVRL_H2_SH(s1_m, s0_m, tmp4_m, tmp5_m); \
+ ILVL_H2_SH(in2, in0, in3, in1, s0_m, s1_m); \
+ ILVRL_H2_SH(s1_m, s0_m, tmp6_m, tmp7_m); \
+ PCKEV_D4(RTYPE, tmp0_m, tmp4_m, tmp1_m, tmp5_m, tmp2_m, tmp6_m, \
+ tmp3_m, tmp7_m, out0, out2, out4, out6); \
+ out1 = (RTYPE) __msa_pckod_d((v2i64) tmp0_m, (v2i64) tmp4_m); \
+ out3 = (RTYPE) __msa_pckod_d((v2i64) tmp1_m, (v2i64) tmp5_m); \
+ out5 = (RTYPE) __msa_pckod_d((v2i64) tmp2_m, (v2i64) tmp6_m); \
+ out7 = (RTYPE) __msa_pckod_d((v2i64) tmp3_m, (v2i64) tmp7_m); \
+}
+#define TRANSPOSE8x8_UH_UH(...) TRANSPOSE8x8_H(v8u16, __VA_ARGS__)
+#define TRANSPOSE8x8_SH_SH(...) TRANSPOSE8x8_H(v8i16, __VA_ARGS__)
+
+/* Description : Transposes 4x4 block with word elements in vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1, out2, out3
+ Return Type - signed word
+ Details :
+*/
+#define TRANSPOSE4x4_SW_SW(in0, in1, in2, in3, out0, out1, out2, out3) \
+{ \
+ v4i32 s0_m, s1_m, s2_m, s3_m; \
+ \
+ ILVRL_W2_SW(in1, in0, s0_m, s1_m); \
+ ILVRL_W2_SW(in3, in2, s2_m, s3_m); \
+ \
+ out0 = (v4i32) __msa_ilvr_d((v2i64) s2_m, (v2i64) s0_m); \
+ out1 = (v4i32) __msa_ilvl_d((v2i64) s2_m, (v2i64) s0_m); \
+ out2 = (v4i32) __msa_ilvr_d((v2i64) s3_m, (v2i64) s1_m); \
+ out3 = (v4i32) __msa_ilvl_d((v2i64) s3_m, (v2i64) s1_m); \
+}
+
/* Description : Pack even elements of input vectors & xor with 128
Arguments : Inputs - in0, in1
Outputs - out_m
projects / ffmpeg / blobdiff