#include <stdlib.h>
#include <string.h>
-#include "libavutil/x86_cpu.h"
+
+#include "libavutil/x86/asm.h"
+#include "libavutil/x86/cpu.h"
#include "libavutil/cpu.h"
+#include "libavutil/cpu_internal.h"
+
+#if HAVE_YASM
+
+#define cpuid(index, eax, ebx, ecx, edx) \
+ ff_cpu_cpuid(index, &eax, &ebx, &ecx, &edx)
+
+#define xgetbv(index, eax, edx) \
+ ff_cpu_xgetbv(index, &eax, &edx)
+
+#elif HAVE_INLINE_ASM
-#if HAVE_INLINE_ASM
/* ebx saving is necessary for PIC. gcc seems unable to see it alone */
#define cpuid(index, eax, ebx, ecx, edx) \
__asm__ volatile ( \
"xchg %%"REG_b", %%"REG_S \
: "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \
: "0" (index))
-#elif HAVE_CPUID
-#include <intrin.h>
-#define cpuid(index, eax, ebx, ecx, edx) \
- do { \
- int info[4]; \
- __cpuid(info, index); \
- eax = info[0]; \
- ebx = info[1]; \
- ecx = info[2]; \
- edx = info[3]; \
- } while (0)
-#endif /* HAVE_CPUID */
-
-#if HAVE_INLINE_ASM
#define xgetbv(index, eax, edx) \
__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
-#elif HAVE_XGETBV
-#include <immintrin.h>
-
-#define xgetbv(index, eax, edx) \
- do { \
- uint64_t res = __xgetbv(index); \
- eax = res; \
- edx = res >> 32; \
- } while (0)
-#endif /* HAVE_XGETBV */
#define get_eflags(x) \
__asm__ volatile ("pushfl \n" \
"popfl \n" \
:: "r"(x))
-/* Function to test if multimedia instructions are supported... */
-int ff_get_cpu_flags_x86(void)
-{
- int rval = 0;
- int eax, ebx, ecx, edx;
- int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0;
- int family = 0, model = 0;
- union { int i[3]; char c[12]; } vendor;
+#endif /* HAVE_INLINE_ASM */
+
+#if ARCH_X86_64
+
+#define cpuid_test() 1
+
+#elif HAVE_YASM
+
+#define cpuid_test ff_cpu_cpuid_test
-#if ARCH_X86_32
+#elif HAVE_INLINE_ASM
+
+static int cpuid_test(void)
+{
x86_reg a, c;
/* Check if CPUID is supported by attempting to toggle the ID bit in
set_eflags(a ^ 0x200000);
get_eflags(c);
- if (a == c)
- return 0; /* CPUID not supported */
+ return a != c;
+}
#endif
- cpuid(0, max_std_level, ebx, ecx, edx);
- vendor.i[0] = ebx;
- vendor.i[1] = edx;
- vendor.i[2] = ecx;
+/* Function to test if multimedia instructions are supported... */
+int ff_get_cpu_flags_x86(void)
+{
+ int rval = 0;
+
+#ifdef cpuid
+
+ int eax, ebx, ecx, edx;
+ int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0;
+ int family = 0, model = 0;
+ union { int i[3]; char c[12]; } vendor;
+
+ if (!cpuid_test())
+ return 0; /* CPUID not supported */
+
+ cpuid(0, max_std_level, vendor.i[0], vendor.i[2], vendor.i[1]);
if (max_std_level >= 1) {
cpuid(1, eax, ebx, ecx, std_caps);
if (std_caps & (1 << 23))
rval |= AV_CPU_FLAG_MMX;
if (std_caps & (1 << 25))
- rval |= AV_CPU_FLAG_MMX2;
+ rval |= AV_CPU_FLAG_MMXEXT;
#if HAVE_SSE
if (std_caps & (1 << 25))
rval |= AV_CPU_FLAG_SSE;
if ((ecx & 0x18000000) == 0x18000000) {
/* Check for OS support */
xgetbv(0, eax, edx);
- if ((eax & 0x6) == 0x6)
+ if ((eax & 0x6) == 0x6) {
rval |= AV_CPU_FLAG_AVX;
+ if (ecx & 0x00001000)
+ rval |= AV_CPU_FLAG_FMA3;
+ }
+ }
+#endif /* HAVE_AVX */
+#endif /* HAVE_SSE */
+ }
+ if (max_std_level >= 7) {
+ cpuid(7, eax, ebx, ecx, edx);
+#if HAVE_AVX2
+ if (ebx & 0x00000020)
+ rval |= AV_CPU_FLAG_AVX2;
+#endif /* HAVE_AVX2 */
+ /* BMI1/2 don't need OS support */
+ if (ebx & 0x00000008) {
+ rval |= AV_CPU_FLAG_BMI1;
+ if (ebx & 0x00000100)
+ rval |= AV_CPU_FLAG_BMI2;
}
-#endif
-#endif
}
cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
if (ext_caps & (1 << 23))
rval |= AV_CPU_FLAG_MMX;
if (ext_caps & (1 << 22))
- rval |= AV_CPU_FLAG_MMX2;
+ rval |= AV_CPU_FLAG_MMXEXT;
+ if (!strncmp(vendor.c, "AuthenticAMD", 12)) {
/* Allow for selectively disabling SSE2 functions on AMD processors
with SSE2 support but not SSE4a. This includes Athlon64, some
Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
so that SSE2 is used unless explicitly disabled by checking
AV_CPU_FLAG_SSE2SLOW. */
- if (!strncmp(vendor.c, "AuthenticAMD", 12) &&
- rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {
- rval |= AV_CPU_FLAG_SSE2SLOW;
+ if (rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040))
+ rval |= AV_CPU_FLAG_SSE2SLOW;
+
+ /* Similar to the above but for AVX functions on AMD processors.
+ This is necessary only for functions using YMM registers on Bulldozer
+ based CPUs as they lack 256-bits execution units. SSE/AVX functions
+ using XMM registers are always faster on them.
+ AV_CPU_FLAG_AVX and AV_CPU_FLAG_AVXSLOW are both set so that AVX is
+ used unless explicitly disabled by checking AV_CPU_FLAG_AVXSLOW.
+ TODO: Confirm if Excavator is affected or not by this once it's
+ released, and update the check if necessary. Same for btver2. */
+ if (family == 0x15 && (rval & AV_CPU_FLAG_AVX))
+ rval |= AV_CPU_FLAG_AVXSLOW;
}
/* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
rval |= AV_CPU_FLAG_ATOM;
}
+#endif /* cpuid */
+
return rval;
}
projects / ffmpeg / blobdiff