x86: cosmetics: Comment some #endifs for better readability

[ffmpeg] / libavutil / x86 / cpu.c

diff --git a/libavutil/x86/cpu.c b/libavutil/x86/cpu.c
index 7d65c6075e4d9944e1bb22b8f211f16a75707bb2..9acc86755d68260647f842df7957faa056dc6998 100644 (file)
--- a/libavutil/x86/cpu.c
+++ b/libavutil/x86/cpu.c
@@ -22,7 +22,7 @@
 
 #include <stdlib.h>
 #include <string.h>
-#include "libavutil/x86_cpu.h"
+#include "libavutil/x86/asm.h"
 #include "libavutil/cpu.h"
 
 #if HAVE_INLINE_ASM
@@ -62,6 +62,8 @@
     } while (0)
 #endif /* HAVE_XGETBV */
 
+#if HAVE_INLINE_ASM
+
 #define get_eflags(x)                           \
     __asm__ volatile ("pushfl     \n"           \
                       "pop    %0  \n"           \
@@ -72,6 +74,18 @@
                       "popfl      \n"           \
                       :: "r"(x))
 
+#elif HAVE_RWEFLAGS
+
+#include <intrin.h>
+
+#define get_eflags(x)                           \
+    x = __readeflags()
+
+#define set_eflags(x)                           \
+    __writeeflags(x)
+
+#endif /* HAVE_INLINE_ASM */
+
 /* Function to test if multimedia instructions are supported...  */
 int ff_get_cpu_flags_x86(void)
 {
@@ -108,7 +122,7 @@ int ff_get_cpu_flags_x86(void)
         if (std_caps & (1 << 23))
             rval |= AV_CPU_FLAG_MMX;
         if (std_caps & (1 << 25))
-            rval |= AV_CPU_FLAG_MMX2;
+            rval |= AV_CPU_FLAG_MMXEXT;
 #if HAVE_SSE
         if (std_caps & (1 << 25))
             rval |= AV_CPU_FLAG_SSE;
@@ -130,8 +144,8 @@ int ff_get_cpu_flags_x86(void)
             if ((eax & 0x6) == 0x6)
                 rval |= AV_CPU_FLAG_AVX;
         }
-#endif
-#endif
+#endif /* HAVE_AVX */
+#endif /* HAVE_SSE */
     }
 
     cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
@@ -145,7 +159,7 @@ int ff_get_cpu_flags_x86(void)
         if (ext_caps & (1 << 23))
             rval |= AV_CPU_FLAG_MMX;
         if (ext_caps & (1 << 22))
-            rval |= AV_CPU_FLAG_MMX2;
+            rval |= AV_CPU_FLAG_MMXEXT;
 
         /* Allow for selectively disabling SSE2 functions on AMD processors
            with SSE2 support but not SSE4a. This includes Athlon64, some