; of 2. $offset is either 0 or 3. $dither holds 8 values.
;-----------------------------------------------------------------------------
-%macro yuv2planeX_fn 4
+%macro yuv2planeX_fn 3
-%ifdef ARCH_X86_32
-%define cntr_reg r1
+%if ARCH_X86_32
+%define cntr_reg fltsizeq
%define movsx mov
%else
%define cntr_reg r11
%define movsx movsxd
%endif
-cglobal yuv2planeX_%2_%1, %4, 7, %3
-%if %2 == 8 || %2 == 9 || %2 == 10
+cglobal yuv2planeX_%1, %3, 7, %2, filter, fltsize, src, dst, w, dither, offset
+%if %1 == 8 || %1 == 9 || %1 == 10
pxor m6, m6
-%endif ; %2 == 8/9/10
+%endif ; %1 == 8/9/10
-%if %2 == 8
-%ifdef ARCH_X86_32
+%if %1 == 8
+%if ARCH_X86_32
%assign pad 0x2c - (stack_offset & 15)
SUB rsp, pad
%define m_dith m7
%endif ; x86-32
; create registers holding dither
- movq m_dith, [r5] ; dither
- test r6d, r6d
+ movq m_dith, [ditherq] ; dither
+ test offsetd, offsetd
jz .no_rot
%if mmsize == 16
punpcklqdq m_dith, m_dith
.no_rot:
%if mmsize == 16
punpcklbw m_dith, m6
-%ifdef ARCH_X86_64
+%if ARCH_X86_64
punpcklwd m8, m_dith, m6
pslld m8, 12
%else ; x86-32
%endif ; x86-32/64
punpckhwd m_dith, m6
pslld m_dith, 12
-%ifdef ARCH_X86_32
+%if ARCH_X86_32
mova [rsp+ 0], m5
mova [rsp+16], m_dith
%endif
mova [rsp+16], m3
mova [rsp+24], m_dith
%endif ; mmsize == 8/16
-%endif ; %2 == 8
+%endif ; %1 == 8
xor r5, r5
; 8 pixels but we can only handle 2 pixels per register, and thus 4
; pixels per iteration. In order to not have to keep track of where
; we are w.r.t. dithering, we unroll the mmx/8bit loop x2.
-%if %2 == 8
-%rep 16/mmsize
-%endif ; %2 == 8
+%if %1 == 8
+%assign %%repcnt 16/mmsize
+%else
+%assign %%repcnt 1
+%endif
+
+%rep %%repcnt
-%if %2 == 8
-%ifdef ARCH_X86_32
+%if %1 == 8
+%if ARCH_X86_32
mova m2, [rsp+mmsize*(0+%%i)]
mova m1, [rsp+mmsize*(1+%%i)]
%else ; x86-64
mova m2, m8
mova m1, m_dith
%endif ; x86-32/64
-%else ; %2 == 9/10/16
- mova m1, [yuv2yuvX_%2_start]
+%else ; %1 == 9/10/16
+ mova m1, [yuv2yuvX_%1_start]
mova m2, m1
-%endif ; %2 == 8/9/10/16
- movsx cntr_reg, r1m
+%endif ; %1 == 8/9/10/16
+ movsx cntr_reg, fltsizem
.filterloop_ %+ %%i:
; input pixels
- mov r6, [r2+gprsize*cntr_reg-2*gprsize]
-%if %2 == 16
+ mov r6, [srcq+gprsize*cntr_reg-2*gprsize]
+%if %1 == 16
mova m3, [r6+r5*4]
mova m5, [r6+r5*4+mmsize]
-%else ; %2 == 8/9/10
+%else ; %1 == 8/9/10
mova m3, [r6+r5*2]
-%endif ; %2 == 8/9/10/16
- mov r6, [r2+gprsize*cntr_reg-gprsize]
-%if %2 == 16
+%endif ; %1 == 8/9/10/16
+ mov r6, [srcq+gprsize*cntr_reg-gprsize]
+%if %1 == 16
mova m4, [r6+r5*4]
mova m6, [r6+r5*4+mmsize]
-%else ; %2 == 8/9/10
+%else ; %1 == 8/9/10
mova m4, [r6+r5*2]
-%endif ; %2 == 8/9/10/16
+%endif ; %1 == 8/9/10/16
; coefficients
- movd m0, [r0+2*cntr_reg-4]; coeff[0], coeff[1]
-%if %2 == 16
+ movd m0, [filterq+2*cntr_reg-4] ; coeff[0], coeff[1]
+%if %1 == 16
pshuflw m7, m0, 0 ; coeff[0]
pshuflw m0, m0, 0x55 ; coeff[1]
pmovsxwd m7, m7 ; word -> dword
paddd m1, m5
paddd m2, m4
paddd m1, m6
-%else ; %2 == 10/9/8
+%else ; %1 == 10/9/8
punpcklwd m5, m3, m4
punpckhwd m3, m4
SPLATD m0, m0
paddd m2, m5
paddd m1, m3
-%endif ; %2 == 8/9/10/16
+%endif ; %1 == 8/9/10/16
sub cntr_reg, 2
jg .filterloop_ %+ %%i
-%if %2 == 16
- psrad m2, 31 - %2
- psrad m1, 31 - %2
-%else ; %2 == 10/9/8
- psrad m2, 27 - %2
- psrad m1, 27 - %2
-%endif ; %2 == 8/9/10/16
+%if %1 == 16
+ psrad m2, 31 - %1
+ psrad m1, 31 - %1
+%else ; %1 == 10/9/8
+ psrad m2, 27 - %1
+ psrad m1, 27 - %1
+%endif ; %1 == 8/9/10/16
-%if %2 == 8
+%if %1 == 8
packssdw m2, m1
packuswb m2, m2
- movh [r3+r5*1], m2
-%else ; %2 == 9/10/16
-%if %2 == 16
+ movh [dstq+r5*1], m2
+%else ; %1 == 9/10/16
+%if %1 == 16
packssdw m2, m1
paddw m2, [minshort]
-%else ; %2 == 9/10
-%ifidn %1, sse4
- packusdw m2, m1
-%elifidn %1, avx
+%else ; %1 == 9/10
+%if cpuflag(sse4)
packusdw m2, m1
%else ; mmx2/sse2
packssdw m2, m1
pmaxsw m2, m6
%endif ; mmx2/sse2/sse4/avx
- pminsw m2, [yuv2yuvX_%2_upper]
-%endif ; %2 == 9/10/16
- mova [r3+r5*2], m2
-%endif ; %2 == 8/9/10/16
+ pminsw m2, [yuv2yuvX_%1_upper]
+%endif ; %1 == 9/10/16
+ mova [dstq+r5*2], m2
+%endif ; %1 == 8/9/10/16
add r5, mmsize/2
- sub r4d, mmsize/2
-%if %2 == 8
+ sub wd, mmsize/2
+
%assign %%i %%i+2
%endrep
-%endif ; %2 == 8
jg .pixelloop
-%if %2 == 8
-%ifdef ARCH_X86_32
+%if %1 == 8
+%if ARCH_X86_32
ADD rsp, pad
RET
%else ; x86-64
REP_RET
%endif ; x86-32/64
-%else ; %2 == 9/10/16
+%else ; %1 == 9/10/16
REP_RET
-%endif ; %2 == 8/9/10/16
+%endif ; %1 == 8/9/10/16
%endmacro
%define PALIGNR PALIGNR_MMX
-%ifdef ARCH_X86_32
-INIT_MMX
-yuv2planeX_fn mmx2, 8, 0, 7
-yuv2planeX_fn mmx2, 9, 0, 5
-yuv2planeX_fn mmx2, 10, 0, 5
+%if ARCH_X86_32
+INIT_MMX mmx2
+yuv2planeX_fn 8, 0, 7
+yuv2planeX_fn 9, 0, 5
+yuv2planeX_fn 10, 0, 5
%endif
-INIT_XMM
-yuv2planeX_fn sse2, 8, 10, 7
-yuv2planeX_fn sse2, 9, 7, 5
-yuv2planeX_fn sse2, 10, 7, 5
+INIT_XMM sse2
+yuv2planeX_fn 8, 10, 7
+yuv2planeX_fn 9, 7, 5
+yuv2planeX_fn 10, 7, 5
%define PALIGNR PALIGNR_SSSE3
-yuv2planeX_fn sse4, 8, 10, 7
-yuv2planeX_fn sse4, 9, 7, 5
-yuv2planeX_fn sse4, 10, 7, 5
-yuv2planeX_fn sse4, 16, 8, 5
-
-%ifdef HAVE_AVX
-INIT_AVX
-yuv2planeX_fn avx, 8, 10, 7
-yuv2planeX_fn avx, 9, 7, 5
-yuv2planeX_fn avx, 10, 7, 5
+INIT_XMM sse4
+yuv2planeX_fn 8, 10, 7
+yuv2planeX_fn 9, 7, 5
+yuv2planeX_fn 10, 7, 5
+yuv2planeX_fn 16, 8, 5
+
+%if HAVE_AVX
+INIT_XMM avx
+yuv2planeX_fn 8, 10, 7
+yuv2planeX_fn 9, 7, 5
+yuv2planeX_fn 10, 7, 5
%endif
; %1=outout-bpc, %2=alignment (u/a)
%macro yuv2plane1_mainloop 2
.loop_%2:
%if %1 == 8
- paddsw m0, m2, [r0+r2*2+mmsize*0]
- paddsw m1, m3, [r0+r2*2+mmsize*1]
+ paddsw m0, m2, [srcq+wq*2+mmsize*0]
+ paddsw m1, m3, [srcq+wq*2+mmsize*1]
psraw m0, 7
psraw m1, 7
packuswb m0, m1
- mov%2 [r1+r2], m0
+ mov%2 [dstq+wq], m0
%elif %1 == 16
- paddd m0, m4, [r0+r2*4+mmsize*0]
- paddd m1, m4, [r0+r2*4+mmsize*1]
- paddd m2, m4, [r0+r2*4+mmsize*2]
- paddd m3, m4, [r0+r2*4+mmsize*3]
+ paddd m0, m4, [srcq+wq*4+mmsize*0]
+ paddd m1, m4, [srcq+wq*4+mmsize*1]
+ paddd m2, m4, [srcq+wq*4+mmsize*2]
+ paddd m3, m4, [srcq+wq*4+mmsize*3]
psrad m0, 3
psrad m1, 3
psrad m2, 3
paddw m0, m5
paddw m2, m5
%endif ; mmx/sse2/sse4/avx
- mov%2 [r1+r2*2], m0
- mov%2 [r1+r2*2+mmsize], m2
-%else
- paddsw m0, m2, [r0+r2*2+mmsize*0]
- paddsw m1, m2, [r0+r2*2+mmsize*1]
+ mov%2 [dstq+wq*2+mmsize*0], m0
+ mov%2 [dstq+wq*2+mmsize*1], m2
+%else ; %1 == 9/10
+ paddsw m0, m2, [srcq+wq*2+mmsize*0]
+ paddsw m1, m2, [srcq+wq*2+mmsize*1]
psraw m0, 15 - %1
psraw m1, 15 - %1
pmaxsw m0, m4
pmaxsw m1, m4
pminsw m0, m3
pminsw m1, m3
- mov%2 [r1+r2*2], m0
- mov%2 [r1+r2*2+mmsize], m1
+ mov%2 [dstq+wq*2+mmsize*0], m0
+ mov%2 [dstq+wq*2+mmsize*1], m1
%endif
- add r2, mmsize
+ add wq, mmsize
jl .loop_%2
%endmacro
%macro yuv2plane1_fn 3
-cglobal yuv2plane1_%1, %3, %3, %2
- add r2, mmsize - 1
- and r2, ~(mmsize - 1)
+cglobal yuv2plane1_%1, %3, %3, %2, src, dst, w, dither, offset
+ movsxdifnidn wq, wd
+ add wq, mmsize - 1
+ and wq, ~(mmsize - 1)
%if %1 == 8
- add r1, r2
+ add dstq, wq
%else ; %1 != 8
- lea r1, [r1+r2*2]
+ lea dstq, [dstq+wq*2]
%endif ; %1 == 8
%if %1 == 16
- lea r0, [r0+r2*4]
+ lea srcq, [srcq+wq*4]
%else ; %1 != 16
- lea r0, [r0+r2*2]
+ lea srcq, [srcq+wq*2]
%endif ; %1 == 16
- neg r2
+ neg wq
%if %1 == 8
pxor m4, m4 ; zero
; create registers holding dither
- movq m3, [r3] ; dither
- test r4d, r4d
+ movq m3, [ditherq] ; dither
+ test offsetd, offsetd
jz .no_rot
%if mmsize == 16
punpcklqdq m3, m3
%if mmsize == 8
yuv2plane1_mainloop %1, a
%else ; mmsize == 16
- test r1, 15
+ test dstq, 15
jnz .unaligned
yuv2plane1_mainloop %1, a
REP_RET
REP_RET
%endmacro
-%ifdef ARCH_X86_32
+%if ARCH_X86_32
INIT_MMX mmx
yuv2plane1_fn 8, 0, 5
yuv2plane1_fn 16, 0, 3
INIT_XMM sse4
yuv2plane1_fn 16, 5, 3
-%ifdef HAVE_AVX
+%if HAVE_AVX
INIT_XMM avx
yuv2plane1_fn 8, 5, 5
yuv2plane1_fn 9, 5, 3
projects / ffmpeg / blobdiff