Prefetch always form a chache line boundary. It seems
that if prefetch address is not cache line aligned then
performance is adversely impacted.
Hopefully we will resuse that 32 bits of padding for something
useful in the future.
Signed-off-by: Marco Costalba <mcostalba@gmail.com>
#endif
// This is the number of TTEntry slots for each position
#endif
// This is the number of TTEntry slots for each position
-static const int ClusterSize = 5;
+static const int ClusterSize = 4;
// The main transposition table
TranspositionTable TT;
// The main transposition table
TranspositionTable TT;
uint32_t data;
int16_t value_;
int16_t depth_;
uint32_t data;
int16_t value_;
int16_t depth_;
+ uint32_t pad_to_16_bytes;
};
/// The transposition table class. This is basically just a huge array
};
/// The transposition table class. This is basically just a huge array