--- /dev/null
- #if HAVE_MIPSDSPR1
- static void float_to_int16_mips(int16_t *dst, const float *src, long len)
- {
- const float *src_end = src + len;
- int ret0, ret1, ret2, ret3, ret4, ret5, ret6, ret7;
- float src0, src1, src2, src3, src4, src5, src6, src7;
-
- /*
- * loop is 8 times unrolled in assembler in order to achieve better performance
- */
- __asm__ volatile(
- "beq %[len], $zero, fti16_end%= \n\t"
- "fti16_lp%=: \n\t"
- "lwc1 %[src0], 0(%[src]) \n\t"
- "lwc1 %[src1], 4(%[src]) \n\t"
- "lwc1 %[src2], 8(%[src]) \n\t"
- "lwc1 %[src3], 12(%[src]) \n\t"
- "cvt.w.s %[src0], %[src0] \n\t"
- "cvt.w.s %[src1], %[src1] \n\t"
- "cvt.w.s %[src2], %[src2] \n\t"
- "cvt.w.s %[src3], %[src3] \n\t"
- "mfc1 %[ret0], %[src0] \n\t"
- "mfc1 %[ret1], %[src1] \n\t"
- "mfc1 %[ret2], %[src2] \n\t"
- "mfc1 %[ret3], %[src3] \n\t"
- "lwc1 %[src4], 16(%[src]) \n\t"
- "lwc1 %[src5], 20(%[src]) \n\t"
- "lwc1 %[src6], 24(%[src]) \n\t"
- "lwc1 %[src7], 28(%[src]) \n\t"
- "cvt.w.s %[src4], %[src4] \n\t"
- "cvt.w.s %[src5], %[src5] \n\t"
- "cvt.w.s %[src6], %[src6] \n\t"
- "cvt.w.s %[src7], %[src7] \n\t"
- "addiu %[src], 32 \n\t"
- "shll_s.w %[ret0], %[ret0], 16 \n\t"
- "shll_s.w %[ret1], %[ret1], 16 \n\t"
- "shll_s.w %[ret2], %[ret2], 16 \n\t"
- "shll_s.w %[ret3], %[ret3], 16 \n\t"
- "srl %[ret0], %[ret0], 16 \n\t"
- "srl %[ret1], %[ret1], 16 \n\t"
- "srl %[ret2], %[ret2], 16 \n\t"
- "srl %[ret3], %[ret3], 16 \n\t"
- "sh %[ret0], 0(%[dst]) \n\t"
- "sh %[ret1], 2(%[dst]) \n\t"
- "sh %[ret2], 4(%[dst]) \n\t"
- "sh %[ret3], 6(%[dst]) \n\t"
- "mfc1 %[ret4], %[src4] \n\t"
- "mfc1 %[ret5], %[src5] \n\t"
- "mfc1 %[ret6], %[src6] \n\t"
- "mfc1 %[ret7], %[src7] \n\t"
- "shll_s.w %[ret4], %[ret4], 16 \n\t"
- "shll_s.w %[ret5], %[ret5], 16 \n\t"
- "shll_s.w %[ret6], %[ret6], 16 \n\t"
- "shll_s.w %[ret7], %[ret7], 16 \n\t"
- "srl %[ret4], %[ret4], 16 \n\t"
- "srl %[ret5], %[ret5], 16 \n\t"
- "srl %[ret6], %[ret6], 16 \n\t"
- "srl %[ret7], %[ret7], 16 \n\t"
- "sh %[ret4], 8(%[dst]) \n\t"
- "sh %[ret5], 10(%[dst]) \n\t"
- "sh %[ret6], 12(%[dst]) \n\t"
- "sh %[ret7], 14(%[dst]) \n\t"
- "addiu %[dst], 16 \n\t"
- "bne %[src], %[src_end], fti16_lp%= \n\t"
- "fti16_end%=: \n\t"
- : [ret0]"=&r"(ret0), [ret1]"=&r"(ret1), [ret2]"=&r"(ret2), [ret3]"=&r"(ret3),
- [ret4]"=&r"(ret4), [ret5]"=&r"(ret5), [ret6]"=&r"(ret6), [ret7]"=&r"(ret7),
- [src0]"=&f"(src0), [src1]"=&f"(src1), [src2]"=&f"(src2), [src3]"=&f"(src3),
- [src4]"=&f"(src4), [src5]"=&f"(src5), [src6]"=&f"(src6), [src7]"=&f"(src7),
- [src]"+r"(src), [dst]"+r"(dst)
- : [src_end]"r"(src_end), [len]"r"(len)
- : "memory"
- );
- }
-
- static void float_to_int16_interleave_mips(int16_t *dst, const float **src, long len,
- int channels)
- {
- int c, ch2 = channels <<1;
- int ret0, ret1, ret2, ret3, ret4, ret5, ret6, ret7;
- float src0, src1, src2, src3, src4, src5, src6, src7;
- int16_t *dst_ptr0, *dst_ptr1, *dst_ptr2, *dst_ptr3;
- int16_t *dst_ptr4, *dst_ptr5, *dst_ptr6, *dst_ptr7;
- const float *src_ptr, *src_ptr2, *src_end;
-
- if (channels == 2) {
- src_ptr = &src[0][0];
- src_ptr2 = &src[1][0];
- src_end = src_ptr + len;
-
- __asm__ volatile (
- "fti16i2_lp%=: \n\t"
- "lwc1 %[src0], 0(%[src_ptr]) \n\t"
- "lwc1 %[src1], 0(%[src_ptr2]) \n\t"
- "addiu %[src_ptr], 4 \n\t"
- "cvt.w.s $f9, %[src0] \n\t"
- "cvt.w.s $f10, %[src1] \n\t"
- "mfc1 %[ret0], $f9 \n\t"
- "mfc1 %[ret1], $f10 \n\t"
- "shll_s.w %[ret0], %[ret0], 16 \n\t"
- "shll_s.w %[ret1], %[ret1], 16 \n\t"
- "addiu %[src_ptr2], 4 \n\t"
- "srl %[ret0], %[ret0], 16 \n\t"
- "srl %[ret1], %[ret1], 16 \n\t"
- "sh %[ret0], 0(%[dst]) \n\t"
- "sh %[ret1], 2(%[dst]) \n\t"
- "addiu %[dst], 4 \n\t"
- "bne %[src_ptr], %[src_end], fti16i2_lp%= \n\t"
- : [ret0]"=&r"(ret0), [ret1]"=&r"(ret1),
- [src0]"=&f"(src0), [src1]"=&f"(src1),
- [src_ptr]"+r"(src_ptr), [src_ptr2]"+r"(src_ptr2),
- [dst]"+r"(dst)
- : [src_end]"r"(src_end)
- : "memory"
- );
- } else {
- for (c = 0; c < channels; c++) {
- src_ptr = &src[c][0];
- dst_ptr0 = &dst[c];
- src_end = src_ptr + len;
- /*
- * loop is 8 times unrolled in assembler in order to achieve better performance
- */
- __asm__ volatile(
- "fti16i_lp%=: \n\t"
- "lwc1 %[src0], 0(%[src_ptr]) \n\t"
- "lwc1 %[src1], 4(%[src_ptr]) \n\t"
- "lwc1 %[src2], 8(%[src_ptr]) \n\t"
- "lwc1 %[src3], 12(%[src_ptr]) \n\t"
- "cvt.w.s %[src0], %[src0] \n\t"
- "cvt.w.s %[src1], %[src1] \n\t"
- "cvt.w.s %[src2], %[src2] \n\t"
- "cvt.w.s %[src3], %[src3] \n\t"
- "mfc1 %[ret0], %[src0] \n\t"
- "mfc1 %[ret1], %[src1] \n\t"
- "mfc1 %[ret2], %[src2] \n\t"
- "mfc1 %[ret3], %[src3] \n\t"
- "lwc1 %[src4], 16(%[src_ptr]) \n\t"
- "lwc1 %[src5], 20(%[src_ptr]) \n\t"
- "lwc1 %[src6], 24(%[src_ptr]) \n\t"
- "lwc1 %[src7], 28(%[src_ptr]) \n\t"
- "addu %[dst_ptr1], %[dst_ptr0], %[ch2] \n\t"
- "addu %[dst_ptr2], %[dst_ptr1], %[ch2] \n\t"
- "addu %[dst_ptr3], %[dst_ptr2], %[ch2] \n\t"
- "addu %[dst_ptr4], %[dst_ptr3], %[ch2] \n\t"
- "addu %[dst_ptr5], %[dst_ptr4], %[ch2] \n\t"
- "addu %[dst_ptr6], %[dst_ptr5], %[ch2] \n\t"
- "addu %[dst_ptr7], %[dst_ptr6], %[ch2] \n\t"
- "addiu %[src_ptr], 32 \n\t"
- "cvt.w.s %[src4], %[src4] \n\t"
- "cvt.w.s %[src5], %[src5] \n\t"
- "cvt.w.s %[src6], %[src6] \n\t"
- "cvt.w.s %[src7], %[src7] \n\t"
- "shll_s.w %[ret0], %[ret0], 16 \n\t"
- "shll_s.w %[ret1], %[ret1], 16 \n\t"
- "shll_s.w %[ret2], %[ret2], 16 \n\t"
- "shll_s.w %[ret3], %[ret3], 16 \n\t"
- "srl %[ret0], %[ret0], 16 \n\t"
- "srl %[ret1], %[ret1], 16 \n\t"
- "srl %[ret2], %[ret2], 16 \n\t"
- "srl %[ret3], %[ret3], 16 \n\t"
- "sh %[ret0], 0(%[dst_ptr0]) \n\t"
- "sh %[ret1], 0(%[dst_ptr1]) \n\t"
- "sh %[ret2], 0(%[dst_ptr2]) \n\t"
- "sh %[ret3], 0(%[dst_ptr3]) \n\t"
- "mfc1 %[ret4], %[src4] \n\t"
- "mfc1 %[ret5], %[src5] \n\t"
- "mfc1 %[ret6], %[src6] \n\t"
- "mfc1 %[ret7], %[src7] \n\t"
- "shll_s.w %[ret4], %[ret4], 16 \n\t"
- "shll_s.w %[ret5], %[ret5], 16 \n\t"
- "shll_s.w %[ret6], %[ret6], 16 \n\t"
- "shll_s.w %[ret7], %[ret7], 16 \n\t"
- "srl %[ret4], %[ret4], 16 \n\t"
- "srl %[ret5], %[ret5], 16 \n\t"
- "srl %[ret6], %[ret6], 16 \n\t"
- "srl %[ret7], %[ret7], 16 \n\t"
- "sh %[ret4], 0(%[dst_ptr4]) \n\t"
- "sh %[ret5], 0(%[dst_ptr5]) \n\t"
- "sh %[ret6], 0(%[dst_ptr6]) \n\t"
- "sh %[ret7], 0(%[dst_ptr7]) \n\t"
- "addu %[dst_ptr0], %[dst_ptr7], %[ch2] \n\t"
- "bne %[src_ptr], %[src_end], fti16i_lp%= \n\t"
- : [ret0]"=&r"(ret0), [ret1]"=&r"(ret1), [ret2]"=&r"(ret2), [ret3]"=&r"(ret3),
- [ret4]"=&r"(ret4), [ret5]"=&r"(ret5), [ret6]"=&r"(ret6), [ret7]"=&r"(ret7),
- [src0]"=&f"(src0), [src1]"=&f"(src1), [src2]"=&f"(src2), [src3]"=&f"(src3),
- [src4]"=&f"(src4), [src5]"=&f"(src5), [src6]"=&f"(src6), [src7]"=&f"(src7),
- [dst_ptr1]"=&r"(dst_ptr1), [dst_ptr2]"=&r"(dst_ptr2), [dst_ptr3]"=&r"(dst_ptr3),
- [dst_ptr4]"=&r"(dst_ptr4), [dst_ptr5]"=&r"(dst_ptr5), [dst_ptr6]"=&r"(dst_ptr6),
- [dst_ptr7]"=&r"(dst_ptr7), [dst_ptr0]"+r"(dst_ptr0), [src_ptr]"+r"(src_ptr)
- : [ch2]"r"(ch2), [src_end]"r"(src_end)
- : "memory"
- );
- }
- }
- }
- #endif /* HAVE_MIPSDSPR1 */
+/*
+ * Format Conversion Utils for MIPS
+ *
+ * Copyright (c) 2012
+ * MIPS Technologies, Inc., California.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the MIPS Technologies, Inc., nor the names of is
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Author: Zoran Lukic (zoranl@mips.com)
+ * Author: Nedeljko Babic (nbabic@mips.com)
+ *
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include "config.h"
+#include "libavcodec/avcodec.h"
+#include "libavcodec/fmtconvert.h"
+
+#if HAVE_INLINE_ASM
- #if HAVE_MIPSDSPR1
- c->float_to_int16_interleave = float_to_int16_interleave_mips;
- c->float_to_int16 = float_to_int16_mips;
- #endif
+
+static void int32_to_float_fmul_scalar_mips(float *dst, const int *src,
+ float mul, int len)
+{
+ /*
+ * variables used in inline assembler
+ */
+ float temp1, temp3, temp5, temp7, temp9, temp11, temp13, temp15;
+
+ int rpom1, rpom2, rpom11, rpom21, rpom12, rpom22, rpom13, rpom23;
+ const int *src_end = src + len;
+ /*
+ * loop is 8 times unrolled in assembler in order to achieve better performance
+ */
+ __asm__ volatile (
+ "i32tf_lp%=: \n\t"
+ "lw %[rpom11], 0(%[src]) \n\t"
+ "lw %[rpom21], 4(%[src]) \n\t"
+ "lw %[rpom1], 8(%[src]) \n\t"
+ "lw %[rpom2], 12(%[src]) \n\t"
+ "mtc1 %[rpom11], %[temp1] \n\t"
+ "mtc1 %[rpom21], %[temp3] \n\t"
+ "mtc1 %[rpom1], %[temp5] \n\t"
+ "mtc1 %[rpom2], %[temp7] \n\t"
+
+ "lw %[rpom13], 16(%[src]) \n\t"
+ "lw %[rpom23], 20(%[src]) \n\t"
+ "lw %[rpom12], 24(%[src]) \n\t"
+ "lw %[rpom22], 28(%[src]) \n\t"
+ "mtc1 %[rpom13], %[temp9] \n\t"
+ "mtc1 %[rpom23], %[temp11] \n\t"
+ "mtc1 %[rpom12], %[temp13] \n\t"
+ "mtc1 %[rpom22], %[temp15] \n\t"
+
+ "addiu %[src], 32 \n\t"
+ "cvt.s.w %[temp1], %[temp1] \n\t"
+ "cvt.s.w %[temp3], %[temp3] \n\t"
+ "cvt.s.w %[temp5], %[temp5] \n\t"
+ "cvt.s.w %[temp7], %[temp7] \n\t"
+
+ "cvt.s.w %[temp9], %[temp9] \n\t"
+ "cvt.s.w %[temp11], %[temp11] \n\t"
+ "cvt.s.w %[temp13], %[temp13] \n\t"
+ "cvt.s.w %[temp15], %[temp15] \n\t"
+
+ "mul.s %[temp1], %[temp1], %[mul] \n\t"
+ "mul.s %[temp3], %[temp3], %[mul] \n\t"
+ "mul.s %[temp5], %[temp5], %[mul] \n\t"
+ "mul.s %[temp7], %[temp7], %[mul] \n\t"
+
+ "mul.s %[temp9], %[temp9], %[mul] \n\t"
+ "mul.s %[temp11], %[temp11], %[mul] \n\t"
+ "mul.s %[temp13], %[temp13], %[mul] \n\t"
+ "mul.s %[temp15], %[temp15], %[mul] \n\t"
+
+ "swc1 %[temp1], 0(%[dst]) \n\t" /*dst[i] = src[i] * mul; */
+ "swc1 %[temp3], 4(%[dst]) \n\t" /*dst[i+1] = src[i+1] * mul;*/
+ "swc1 %[temp5], 8(%[dst]) \n\t" /*dst[i+2] = src[i+2] * mul;*/
+ "swc1 %[temp7], 12(%[dst]) \n\t" /*dst[i+3] = src[i+3] * mul;*/
+
+ "swc1 %[temp9], 16(%[dst]) \n\t" /*dst[i+4] = src[i+4] * mul;*/
+ "swc1 %[temp11], 20(%[dst]) \n\t" /*dst[i+5] = src[i+5] * mul;*/
+ "swc1 %[temp13], 24(%[dst]) \n\t" /*dst[i+6] = src[i+6] * mul;*/
+ "swc1 %[temp15], 28(%[dst]) \n\t" /*dst[i+7] = src[i+7] * mul;*/
+ "addiu %[dst], 32 \n\t"
+ "bne %[src], %[src_end], i32tf_lp%= \n\t"
+ : [temp1]"=&f"(temp1), [temp11]"=&f"(temp11),
+ [temp13]"=&f"(temp13), [temp15]"=&f"(temp15),
+ [temp3]"=&f"(temp3), [temp5]"=&f"(temp5),
+ [temp7]"=&f"(temp7), [temp9]"=&f"(temp9),
+ [rpom1]"=&r"(rpom1), [rpom2]"=&r"(rpom2),
+ [rpom11]"=&r"(rpom11), [rpom21]"=&r"(rpom21),
+ [rpom12]"=&r"(rpom12), [rpom22]"=&r"(rpom22),
+ [rpom13]"=&r"(rpom13), [rpom23]"=&r"(rpom23),
+ [dst]"+r"(dst), [src]"+r"(src)
+ : [mul]"f"(mul), [src_end]"r"(src_end)
+ : "memory"
+ );
+}
+#endif /* HAVE_INLINE_ASM */
+
+av_cold void ff_fmt_convert_init_mips(FmtConvertContext *c)
+{
+#if HAVE_INLINE_ASM
+ c->int32_to_float_fmul_scalar = int32_to_float_fmul_scalar_mips;
+#endif
+}
INT32_TO_FLOAT_FMUL_SCALAR 5
INIT_XMM sse2
INT32_TO_FLOAT_FMUL_SCALAR 3
- ;------------------------------------------------------------------------------
- ; void ff_float_to_int16(int16_t *dst, const float *src, long len);
- ;------------------------------------------------------------------------------
- %macro FLOAT_TO_INT16 1
- cglobal float_to_int16, 3, 3, %1, dst, src, len
- add lenq, lenq
- lea srcq, [srcq+2*lenq]
- add dstq, lenq
- neg lenq
- .loop:
- %if cpuflag(sse2)
- cvtps2dq m0, [srcq+2*lenq ]
- cvtps2dq m1, [srcq+2*lenq+16]
- packssdw m0, m1
- mova [dstq+lenq], m0
- %else
- CVTPS2PI m0, [srcq+2*lenq ]
- CVTPS2PI m1, [srcq+2*lenq+ 8]
- CVTPS2PI m2, [srcq+2*lenq+16]
- CVTPS2PI m3, [srcq+2*lenq+24]
- packssdw m0, m1
- packssdw m2, m3
- mova [dstq+lenq ], m0
- mova [dstq+lenq+8], m2
- %endif
- add lenq, 16
- js .loop
- %if mmsize == 8
- emms
- %endif
- REP_RET
- %endmacro
-
- INIT_XMM sse2
- FLOAT_TO_INT16 2
- INIT_MMX sse
- FLOAT_TO_INT16 0
- INIT_MMX 3dnow
- FLOAT_TO_INT16 0
-
- ;------------------------------------------------------------------------------
- ; void ff_float_to_int16_step(int16_t *dst, const float *src, long len, long step);
- ;------------------------------------------------------------------------------
- %macro FLOAT_TO_INT16_STEP 1
- cglobal float_to_int16_step, 4, 7, %1, dst, src, len, step, step3, v1, v2
- add lenq, lenq
- lea srcq, [srcq+2*lenq]
- lea step3q, [stepq*3]
- neg lenq
- .loop:
- %if cpuflag(sse2)
- cvtps2dq m0, [srcq+2*lenq ]
- cvtps2dq m1, [srcq+2*lenq+16]
- packssdw m0, m1
- movd v1d, m0
- psrldq m0, 4
- movd v2d, m0
- psrldq m0, 4
- mov [dstq], v1w
- mov [dstq+stepq*4], v2w
- shr v1d, 16
- shr v2d, 16
- mov [dstq+stepq*2], v1w
- mov [dstq+step3q*2], v2w
- lea dstq, [dstq+stepq*8]
- movd v1d, m0
- psrldq m0, 4
- movd v2d, m0
- mov [dstq], v1w
- mov [dstq+stepq*4], v2w
- shr v1d, 16
- shr v2d, 16
- mov [dstq+stepq*2], v1w
- mov [dstq+step3q*2], v2w
- lea dstq, [dstq+stepq*8]
- %else
- CVTPS2PI m0, [srcq+2*lenq ]
- CVTPS2PI m1, [srcq+2*lenq+ 8]
- CVTPS2PI m2, [srcq+2*lenq+16]
- CVTPS2PI m3, [srcq+2*lenq+24]
- packssdw m0, m1
- packssdw m2, m3
- movd v1d, m0
- psrlq m0, 32
- movd v2d, m0
- mov [dstq], v1w
- mov [dstq+stepq*4], v2w
- shr v1d, 16
- shr v2d, 16
- mov [dstq+stepq*2], v1w
- mov [dstq+step3q*2], v2w
- lea dstq, [dstq+stepq*8]
- movd v1d, m2
- psrlq m2, 32
- movd v2d, m2
- mov [dstq], v1w
- mov [dstq+stepq*4], v2w
- shr v1d, 16
- shr v2d, 16
- mov [dstq+stepq*2], v1w
- mov [dstq+step3q*2], v2w
- lea dstq, [dstq+stepq*8]
- %endif
- add lenq, 16
- js .loop
- %if mmsize == 8
- emms
- %endif
- REP_RET
- %endmacro
-
- INIT_XMM sse2
- FLOAT_TO_INT16_STEP 2
- INIT_MMX sse
- FLOAT_TO_INT16_STEP 0
- INIT_MMX 3dnow
- FLOAT_TO_INT16_STEP 0
-
- ;-------------------------------------------------------------------------------
- ; void ff_float_to_int16_interleave2(int16_t *dst, const float **src, long len);
- ;-------------------------------------------------------------------------------
- %macro FLOAT_TO_INT16_INTERLEAVE2 0
- cglobal float_to_int16_interleave2, 3, 4, 2, dst, src0, src1, len
- lea lenq, [4*r2q]
- mov src1q, [src0q+gprsize]
- mov src0q, [src0q]
- add dstq, lenq
- add src0q, lenq
- add src1q, lenq
- neg lenq
- .loop:
- %if cpuflag(sse2)
- cvtps2dq m0, [src0q+lenq]
- cvtps2dq m1, [src1q+lenq]
- packssdw m0, m1
- movhlps m1, m0
- punpcklwd m0, m1
- mova [dstq+lenq], m0
- %else
- CVTPS2PI m0, [src0q+lenq ]
- CVTPS2PI m1, [src0q+lenq+8]
- CVTPS2PI m2, [src1q+lenq ]
- CVTPS2PI m3, [src1q+lenq+8]
- packssdw m0, m1
- packssdw m2, m3
- mova m1, m0
- punpcklwd m0, m2
- punpckhwd m1, m2
- mova [dstq+lenq ], m0
- mova [dstq+lenq+8], m1
- %endif
- add lenq, 16
- js .loop
- %if mmsize == 8
- emms
- %endif
- REP_RET
- %endmacro
-
- INIT_MMX 3dnow
- FLOAT_TO_INT16_INTERLEAVE2
- INIT_MMX sse
- FLOAT_TO_INT16_INTERLEAVE2
- INIT_XMM sse2
- FLOAT_TO_INT16_INTERLEAVE2
-
- ;-----------------------------------------------------------------------------
- ; void ff_float_to_int16_interleave6(int16_t *dst, const float **src, int len)
- ;-----------------------------------------------------------------------------
- %macro FLOAT_TO_INT16_INTERLEAVE6 0
- cglobal float_to_int16_interleave6, 2, 8, 0, dst, src, src1, src2, src3, src4, src5, len
- %if ARCH_X86_64
- mov lend, r2d
- %else
- %define lend dword r2m
- %endif
- mov src1q, [srcq+1*gprsize]
- mov src2q, [srcq+2*gprsize]
- mov src3q, [srcq+3*gprsize]
- mov src4q, [srcq+4*gprsize]
- mov src5q, [srcq+5*gprsize]
- mov srcq, [srcq]
- sub src1q, srcq
- sub src2q, srcq
- sub src3q, srcq
- sub src4q, srcq
- sub src5q, srcq
- .loop:
- CVTPS2PI mm0, [srcq]
- CVTPS2PI mm1, [srcq+src1q]
- CVTPS2PI mm2, [srcq+src2q]
- CVTPS2PI mm3, [srcq+src3q]
- CVTPS2PI mm4, [srcq+src4q]
- CVTPS2PI mm5, [srcq+src5q]
- packssdw mm0, mm3
- packssdw mm1, mm4
- packssdw mm2, mm5
- PSWAPD mm3, mm0
- punpcklwd mm0, mm1
- punpckhwd mm1, mm2
- punpcklwd mm2, mm3
- PSWAPD mm3, mm0
- punpckldq mm0, mm2
- punpckhdq mm2, mm1
- punpckldq mm1, mm3
- movq [dstq ], mm0
- movq [dstq+16], mm2
- movq [dstq+ 8], mm1
- add srcq, 8
- add dstq, 24
- sub lend, 2
- jg .loop
- emms
- RET
- %endmacro ; FLOAT_TO_INT16_INTERLEAVE6
-
- INIT_MMX sse
- FLOAT_TO_INT16_INTERLEAVE6
- INIT_MMX 3dnow
- FLOAT_TO_INT16_INTERLEAVE6
- INIT_MMX 3dnowext
- FLOAT_TO_INT16_INTERLEAVE6
-
- ;-----------------------------------------------------------------------------
- ; void ff_float_interleave6(float *dst, const float **src, unsigned int len);
- ;-----------------------------------------------------------------------------
-
- %macro FLOAT_INTERLEAVE6 1
- cglobal float_interleave6, 2, 8, %1, dst, src, src1, src2, src3, src4, src5, len
- %if ARCH_X86_64
- mov lend, r2d
- %else
- %define lend dword r2m
- %endif
- mov src1q, [srcq+1*gprsize]
- mov src2q, [srcq+2*gprsize]
- mov src3q, [srcq+3*gprsize]
- mov src4q, [srcq+4*gprsize]
- mov src5q, [srcq+5*gprsize]
- mov srcq, [srcq]
- sub src1q, srcq
- sub src2q, srcq
- sub src3q, srcq
- sub src4q, srcq
- sub src5q, srcq
- .loop:
- %if cpuflag(sse)
- movaps m0, [srcq]
- movaps m1, [srcq+src1q]
- movaps m2, [srcq+src2q]
- movaps m3, [srcq+src3q]
- movaps m4, [srcq+src4q]
- movaps m5, [srcq+src5q]
-
- SBUTTERFLYPS 0, 1, 6
- SBUTTERFLYPS 2, 3, 6
- SBUTTERFLYPS 4, 5, 6
-
- movaps m6, m4
- shufps m4, m0, 0xe4
- movlhps m0, m2
- movhlps m6, m2
- movaps [dstq ], m0
- movaps [dstq+16], m4
- movaps [dstq+32], m6
-
- movaps m6, m5
- shufps m5, m1, 0xe4
- movlhps m1, m3
- movhlps m6, m3
- movaps [dstq+48], m1
- movaps [dstq+64], m5
- movaps [dstq+80], m6
- %else ; mmx
- movq m0, [srcq]
- movq m1, [srcq+src1q]
- movq m2, [srcq+src2q]
- movq m3, [srcq+src3q]
- movq m4, [srcq+src4q]
- movq m5, [srcq+src5q]
-
- SBUTTERFLY dq, 0, 1, 6
- SBUTTERFLY dq, 2, 3, 6
- SBUTTERFLY dq, 4, 5, 6
- movq [dstq ], m0
- movq [dstq+ 8], m2
- movq [dstq+16], m4
- movq [dstq+24], m1
- movq [dstq+32], m3
- movq [dstq+40], m5
- %endif
- add srcq, mmsize
- add dstq, mmsize*6
- sub lend, mmsize/4
- jg .loop
- %if mmsize == 8
- emms
- %endif
- REP_RET
- %endmacro
-
- INIT_MMX mmx
- FLOAT_INTERLEAVE6 0
- INIT_XMM sse
- FLOAT_INTERLEAVE6 7
-
- ;-----------------------------------------------------------------------------
- ; void ff_float_interleave2(float *dst, const float **src, unsigned int len);
- ;-----------------------------------------------------------------------------
-
- %macro FLOAT_INTERLEAVE2 1
- cglobal float_interleave2, 3, 4, %1, dst, src, len, src1
- mov src1q, [srcq+gprsize]
- mov srcq, [srcq ]
- sub src1q, srcq
- .loop:
- mova m0, [srcq ]
- mova m1, [srcq+src1q ]
- mova m3, [srcq +mmsize]
- mova m4, [srcq+src1q+mmsize]
-
- mova m2, m0
- PUNPCKLDQ m0, m1
- PUNPCKHDQ m2, m1
-
- mova m1, m3
- PUNPCKLDQ m3, m4
- PUNPCKHDQ m1, m4
-
- mova [dstq ], m0
- mova [dstq+1*mmsize], m2
- mova [dstq+2*mmsize], m3
- mova [dstq+3*mmsize], m1
-
- add srcq, mmsize*2
- add dstq, mmsize*4
- sub lend, mmsize/2
- jg .loop
- %if mmsize == 8
- emms
- %endif
- REP_RET
- %endmacro
-
- INIT_MMX mmx
- %define PUNPCKLDQ punpckldq
- %define PUNPCKHDQ punpckhdq
- FLOAT_INTERLEAVE2 0
- INIT_XMM sse
- %define PUNPCKLDQ unpcklps
- %define PUNPCKHDQ unpckhps
- FLOAT_INTERLEAVE2 5
+
+;------------------------------------------------------------------------------
+; void ff_int32_to_float_fmul_array8(FmtConvertContext *c, float *dst, const int32_t *src,
+; const float *mul, int len);
+;------------------------------------------------------------------------------
+%macro INT32_TO_FLOAT_FMUL_ARRAY8 0
+cglobal int32_to_float_fmul_array8, 5, 5, 5, c, dst, src, mul, len
+ shl lend, 2
+ add srcq, lenq
+ add dstq, lenq
+ neg lenq
+.loop:
+ movss m0, [mulq]
+ SPLATD m0
+%if cpuflag(sse2)
+ cvtdq2ps m1, [srcq+lenq ]
+ cvtdq2ps m2, [srcq+lenq+16]
+%else
+ cvtpi2ps m1, [srcq+lenq ]
+ cvtpi2ps m3, [srcq+lenq+ 8]
+ cvtpi2ps m2, [srcq+lenq+16]
+ cvtpi2ps m4, [srcq+lenq+24]
+ movlhps m1, m3
+ movlhps m2, m4
+%endif
+ mulps m1, m0
+ mulps m2, m0
+ mova [dstq+lenq ], m1
+ mova [dstq+lenq+16], m2
+ add mulq, 4
+ add lenq, 32
+ jl .loop
+ REP_RET
+%endmacro
+
+INIT_XMM sse
+INT32_TO_FLOAT_FMUL_ARRAY8
+INIT_XMM sse2
+INT32_TO_FLOAT_FMUL_ARRAY8
+
void ff_int32_to_float_fmul_scalar_sse (float *dst, const int32_t *src, float mul, int len);
void ff_int32_to_float_fmul_scalar_sse2(float *dst, const int32_t *src, float mul, int len);
+void ff_int32_to_float_fmul_array8_sse (FmtConvertContext *c, float *dst, const int32_t *src,
+ const float *mul, int len);
+void ff_int32_to_float_fmul_array8_sse2(FmtConvertContext *c, float *dst, const int32_t *src,
+ const float *mul, int len);
- void ff_float_to_int16_3dnow(int16_t *dst, const float *src, long len);
- void ff_float_to_int16_sse (int16_t *dst, const float *src, long len);
- void ff_float_to_int16_sse2 (int16_t *dst, const float *src, long len);
-
- void ff_float_to_int16_step_3dnow(int16_t *dst, const float *src, long len, long step);
- void ff_float_to_int16_step_sse (int16_t *dst, const float *src, long len, long step);
- void ff_float_to_int16_step_sse2 (int16_t *dst, const float *src, long len, long step);
-
- void ff_float_to_int16_interleave2_3dnow(int16_t *dst, const float **src, long len);
- void ff_float_to_int16_interleave2_sse (int16_t *dst, const float **src, long len);
- void ff_float_to_int16_interleave2_sse2 (int16_t *dst, const float **src, long len);
-
- void ff_float_to_int16_interleave6_sse(int16_t *dst, const float **src, int len);
- void ff_float_to_int16_interleave6_3dnow(int16_t *dst, const float **src, int len);
- void ff_float_to_int16_interleave6_3dnowext(int16_t *dst, const float **src, int len);
-
- #define ff_float_to_int16_interleave6_sse2 ff_float_to_int16_interleave6_sse
-
- #define FLOAT_TO_INT16_INTERLEAVE(cpu) \
- /* gcc pessimizes register allocation if this is in the same function as float_to_int16_interleave_sse2*/\
- static av_noinline void float_to_int16_interleave_misc_##cpu(int16_t *dst, const float **src, long len, int channels){\
- int c;\
- for(c=0; c<channels; c++){\
- ff_float_to_int16_step_##cpu(dst+c, src[c], len, channels);\
- }\
- }\
- \
- static void float_to_int16_interleave_##cpu(int16_t *dst, const float **src, long len, int channels){\
- if(channels==1)\
- ff_float_to_int16_##cpu(dst, src[0], len);\
- else if(channels==2){\
- ff_float_to_int16_interleave2_##cpu(dst, src, len);\
- }else if(channels==6){\
- ff_float_to_int16_interleave6_##cpu(dst, src, len);\
- }else\
- float_to_int16_interleave_misc_##cpu(dst, src, len, channels);\
- }
-
- FLOAT_TO_INT16_INTERLEAVE(3dnow)
- FLOAT_TO_INT16_INTERLEAVE(sse)
- FLOAT_TO_INT16_INTERLEAVE(sse2)
-
- static void float_to_int16_interleave_3dnowext(int16_t *dst, const float **src,
- long len, int channels)
- {
- if(channels==6)
- ff_float_to_int16_interleave6_3dnowext(dst, src, len);
- else
- float_to_int16_interleave_3dnow(dst, src, len, channels);
- }
-
- void ff_float_interleave2_mmx(float *dst, const float **src, unsigned int len);
- void ff_float_interleave2_sse(float *dst, const float **src, unsigned int len);
-
- void ff_float_interleave6_mmx(float *dst, const float **src, unsigned int len);
- void ff_float_interleave6_sse(float *dst, const float **src, unsigned int len);
-
- static void float_interleave_mmx(float *dst, const float **src,
- unsigned int len, int channels)
- {
- if (channels == 2) {
- ff_float_interleave2_mmx(dst, src, len);
- } else if (channels == 6)
- ff_float_interleave6_mmx(dst, src, len);
- else
- ff_float_interleave_c(dst, src, len, channels);
- }
-
- static void float_interleave_sse(float *dst, const float **src,
- unsigned int len, int channels)
- {
- if (channels == 2) {
- ff_float_interleave2_sse(dst, src, len);
- } else if (channels == 6)
- ff_float_interleave6_sse(dst, src, len);
- else
- ff_float_interleave_c(dst, src, len, channels);
- }
#endif /* HAVE_YASM */
av_cold void ff_fmt_convert_init_x86(FmtConvertContext *c, AVCodecContext *avctx)
#if HAVE_YASM
int cpu_flags = av_get_cpu_flags();
- if (EXTERNAL_MMX(cpu_flags)) {
- c->float_interleave = float_interleave_mmx;
- }
- if (EXTERNAL_AMD3DNOW(cpu_flags)) {
- if (!(avctx->flags & CODEC_FLAG_BITEXACT)) {
- c->float_to_int16 = ff_float_to_int16_3dnow;
- c->float_to_int16_interleave = float_to_int16_interleave_3dnow;
- }
- }
- if (EXTERNAL_AMD3DNOWEXT(cpu_flags)) {
- if (!(avctx->flags & CODEC_FLAG_BITEXACT)) {
- c->float_to_int16_interleave = float_to_int16_interleave_3dnowext;
- }
- }
if (EXTERNAL_SSE(cpu_flags)) {
c->int32_to_float_fmul_scalar = ff_int32_to_float_fmul_scalar_sse;
- c->float_to_int16 = ff_float_to_int16_sse;
- c->float_to_int16_interleave = float_to_int16_interleave_sse;
- c->float_interleave = float_interleave_sse;
+ c->int32_to_float_fmul_array8 = ff_int32_to_float_fmul_array8_sse;
}
if (EXTERNAL_SSE2(cpu_flags)) {
c->int32_to_float_fmul_scalar = ff_int32_to_float_fmul_scalar_sse2;
- c->float_to_int16 = ff_float_to_int16_sse2;
- c->float_to_int16_interleave = float_to_int16_interleave_sse2;
+ c->int32_to_float_fmul_array8 = ff_int32_to_float_fmul_array8_sse2;
}
#endif /* HAVE_YASM */
}
projects / ffmpeg / commitdiff