Pass around a m68i_cpu_core pointer instead of accessing it as a global variable
}
void *cpu_task() {
- m68k_pulse_reset();
+ m68ki_cpu_core *state = &m68ki_cpu;
+ m68k_pulse_reset(state);
cpu_loop:
if (mouse_hook_enabled) {
printf("%.8X (%.8X)]] %s\n", m68k_get_reg(NULL, M68K_REG_PC), (m68k_get_reg(NULL, M68K_REG_PC) & 0xFFFFFF), disasm_buf);
if (do_disasm)
do_disasm--;
- m68k_execute(1);
+ m68k_execute(state, 1);
}
else {
if (cpu_emulation_running) {
- if (irq)
- m68k_execute(5);
- else
- m68k_execute(loop_cycles);
+ if (irq)
+ m68k_execute(state, 5);
+ else
+ m68k_execute(state, loop_cycles);
}
}
m68k_init();
printf("Setting CPU type to %d.\n", cpu_type);
- m68k_set_cpu_type(cpu_type);
+ m68k_set_cpu_type(&m68ki_cpu, cpu_type);
cpu_pulse_reset();
pthread_t ipl_tid = 0, cpu_tid, kbd_tid;
}
void cpu_pulse_reset(void) {
+ m68ki_cpu_core *state = &m68ki_cpu;
ps_pulse_reset();
if (cfg->platform->handle_reset)
cfg->platform->handle_reset(cfg);
//m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
//m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
- m68k_pulse_reset();
+ m68k_pulse_reset(state);
}
int cpu_irq_ack(int level) {
#include MUSASHI_CNF
#else
#include "m68kconf.h"
+
#endif
/* ======================================================================== */
*/
#define M68K_INT_ACK_SPURIOUS 0xfffffffe
+struct m68ki_cpu_core;
/* CPU types for use in m68k_set_cpu_type() */
enum
unsigned int m68k_read_memory_32(unsigned int address);
/* Read data immediately following the PC */
-unsigned int m68k_read_immediate_16(unsigned int address);
-unsigned int m68k_read_immediate_32(unsigned int address);
+unsigned int m68k_read_immediate_16(struct m68ki_cpu_core *state, unsigned int address);
+unsigned int m68k_read_immediate_32(struct m68ki_cpu_core *state, unsigned int address);
/* Read data relative to the PC */
-unsigned int m68k_read_pcrelative_8(unsigned int address);
-unsigned int m68k_read_pcrelative_16(unsigned int address);
-unsigned int m68k_read_pcrelative_32(unsigned int address);
+unsigned int m68k_read_pcrelative_8(struct m68ki_cpu_core *state, unsigned int address);
+unsigned int m68k_read_pcrelative_16(struct m68ki_cpu_core *state, unsigned int address);
+unsigned int m68k_read_pcrelative_32(struct m68ki_cpu_core *state, unsigned int address);
/* Memory access for the disassembler */
unsigned int m68k_read_disassembler_8 (unsigned int address);
* Currently supported types are: M68K_CPU_TYPE_68000, M68K_CPU_TYPE_68010,
* M68K_CPU_TYPE_EC020, and M68K_CPU_TYPE_68020.
*/
-void m68k_set_cpu_type(unsigned int cpu_type);
+void m68k_set_cpu_type(struct m68ki_cpu_core *state, unsigned int cpu_type);
/* Do whatever initialisations the core requires. Should be called
* at least once at init time.
* the CPU for the first time, the CPU will be set to
* M68K_CPU_TYPE_68000.
*/
-void m68k_pulse_reset(void);
+void m68k_pulse_reset(struct m68ki_cpu_core *state);
/* execute num_cycles worth of instructions. returns number of cycles used */
-int m68k_execute(int num_cycles);
+int m68k_execute(struct m68ki_cpu_core *state, int num_cycles);
/* These functions let you read/write/modify the number of cycles left to run
* while m68k_execute() is running.
/* Trigger a bus error exception */
-void m68k_pulse_bus_error(void);
+void m68k_pulse_bus_error(struct m68ki_cpu_core *state);
/* Context switching to allow multiple CPUs */
unsigned int m68k_get_reg(void* context, m68k_register_t reg);
/* Poke values into the internals of the currently running CPU context */
-void m68k_set_reg(m68k_register_t reg, unsigned int value);
+void m68k_set_reg(void *context, m68k_register_t regnum, unsigned int value);
/* Check if an instruction is valid for the specified CPU type */
unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type);
/* Build the opcode handler table */
void m68ki_build_opcode_table(void);
-extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
+struct m68ki_cpu_core;
+
+extern void (*m68ki_instruction_jump_table[0x10000])(struct m68ki_cpu_core *state); /* opcode handler jump table */
extern unsigned char m68ki_cycles[][0x10000];
#define NUM_CPU_TYPES 5
-void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
+void (*m68ki_instruction_jump_table[0x10000])(m68ki_cpu_core *state); /* opcode handler jump table */
unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
/* This is used to generate the opcode handler jump table */
typedef struct
{
- void (*opcode_handler)(void); /* handler function */
+ void (*opcode_handler)(m68ki_cpu_core *state); /* handler function */
unsigned int mask; /* mask on opcode */
unsigned int match; /* what to match after masking */
unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
#include <stdio.h>
#include "m68kcpu.h"
-extern void m68040_fpu_op0(void);
-extern void m68040_fpu_op1(void);
-extern void m68851_mmu_ops();
-extern void m68881_ftrap();
+extern void m68040_fpu_op0(m68ki_cpu_core *state);
+extern void m68040_fpu_op1(m68ki_cpu_core *state);
+extern void m68851_mmu_ops(m68ki_cpu_core *state);
+extern void m68881_ftrap(m68ki_cpu_core *state);
/* ======================================================================== */
/* ========================= INSTRUCTION HANDLERS ========================= */
M68KMAKE_OP(1010, 0, ., .)
{
- m68ki_exception_1010();
+ m68ki_exception_1010(state);
}
M68KMAKE_OP(1111, 0, ., .)
{
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
// printf("FPU 040fpu0 HAS_FPU=%d\n",!!HAS_FPU);
if(HAS_FPU)
{
- m68040_fpu_op0();
+ m68040_fpu_op0(state);
return;
}
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
// printf("FPU 040fpu1 HAS_FPU=%d\n",!!HAS_FPU);
if(HAS_FPU)
{
- m68040_fpu_op1();
+ m68040_fpu_op1(state);
return;
}
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
M68KMAKE_OP(abcd, 8, mm, ax7)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_A7_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
uint corf = 0;
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(abcd, 8, mm, ay7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_AX_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
uint corf = 0;
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(abcd, 8, mm, axy7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_A7_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
uint corf = 0;
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(abcd, 8, mm, .)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_AX_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
uint corf = 0;
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
{
uint ea = M68KMAKE_GET_EA_AY_8;
uint src = MASK_OUT_ABOVE_8(DX);
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = src + dst;
FLAG_N = NFLAG_8(res);
FLAG_X = FLAG_C = CFLAG_8(res);
FLAG_Z = MASK_OUT_ABOVE_8(res);
- m68ki_write_8(ea, FLAG_Z);
+ m68ki_write_8(state, ea, FLAG_Z);
}
{
uint ea = M68KMAKE_GET_EA_AY_16;
uint src = MASK_OUT_ABOVE_16(DX);
- uint dst = m68ki_read_16(ea);
+ uint dst = m68ki_read_16(state, ea);
uint res = src + dst;
FLAG_N = NFLAG_16(res);
FLAG_X = FLAG_C = CFLAG_16(res);
FLAG_Z = MASK_OUT_ABOVE_16(res);
- m68ki_write_16(ea, FLAG_Z);
+ m68ki_write_16(state, ea, FLAG_Z);
}
{
uint ea = M68KMAKE_GET_EA_AY_32;
uint src = DX;
- uint dst = m68ki_read_32(ea);
+ uint dst = m68ki_read_32(state, ea);
uint res = src + dst;
FLAG_N = NFLAG_32(res);
FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
FLAG_Z = MASK_OUT_ABOVE_32(res);
- m68ki_write_32(ea, FLAG_Z);
+ m68ki_write_32(state, ea, FLAG_Z);
}
M68KMAKE_OP(addi, 8, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint dst = MASK_OUT_ABOVE_8(*r_dst);
uint res = src + dst;
M68KMAKE_OP(addi, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = src + dst;
FLAG_N = NFLAG_8(res);
FLAG_X = FLAG_C = CFLAG_8(res);
FLAG_Z = MASK_OUT_ABOVE_8(res);
- m68ki_write_8(ea, FLAG_Z);
+ m68ki_write_8(state, ea, FLAG_Z);
}
M68KMAKE_OP(addi, 16, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint dst = MASK_OUT_ABOVE_16(*r_dst);
uint res = src + dst;
M68KMAKE_OP(addi, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
- uint dst = m68ki_read_16(ea);
+ uint dst = m68ki_read_16(state, ea);
uint res = src + dst;
FLAG_N = NFLAG_16(res);
FLAG_X = FLAG_C = CFLAG_16(res);
FLAG_Z = MASK_OUT_ABOVE_16(res);
- m68ki_write_16(ea, FLAG_Z);
+ m68ki_write_16(state, ea, FLAG_Z);
}
M68KMAKE_OP(addi, 32, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint dst = *r_dst;
uint res = src + dst;
M68KMAKE_OP(addi, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
- uint dst = m68ki_read_32(ea);
+ uint dst = m68ki_read_32(state, ea);
uint res = src + dst;
FLAG_N = NFLAG_32(res);
FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
FLAG_Z = MASK_OUT_ABOVE_32(res);
- m68ki_write_32(ea, FLAG_Z);
+ m68ki_write_32(state, ea, FLAG_Z);
}
{
uint src = (((REG_IR >> 9) - 1) & 7) + 1;
uint ea = M68KMAKE_GET_EA_AY_8;
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = src + dst;
FLAG_N = NFLAG_8(res);
FLAG_X = FLAG_C = CFLAG_8(res);
FLAG_Z = MASK_OUT_ABOVE_8(res);
- m68ki_write_8(ea, FLAG_Z);
+ m68ki_write_8(state, ea, FLAG_Z);
}
{
uint src = (((REG_IR >> 9) - 1) & 7) + 1;
uint ea = M68KMAKE_GET_EA_AY_16;
- uint dst = m68ki_read_16(ea);
+ uint dst = m68ki_read_16(state, ea);
uint res = src + dst;
FLAG_N = NFLAG_16(res);
FLAG_X = FLAG_C = CFLAG_16(res);
FLAG_Z = MASK_OUT_ABOVE_16(res);
- m68ki_write_16(ea, FLAG_Z);
+ m68ki_write_16(state, ea, FLAG_Z);
}
{
uint src = (((REG_IR >> 9) - 1) & 7) + 1;
uint ea = M68KMAKE_GET_EA_AY_32;
- uint dst = m68ki_read_32(ea);
+ uint dst = m68ki_read_32(state, ea);
uint res = src + dst;
FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
FLAG_Z = MASK_OUT_ABOVE_32(res);
- m68ki_write_32(ea, FLAG_Z);
+ m68ki_write_32(state, ea, FLAG_Z);
}
M68KMAKE_OP(addx, 8, mm, ax7)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_A7_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = src + dst + XFLAG_AS_1();
FLAG_N = NFLAG_8(res);
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(addx, 8, mm, ay7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_AX_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = src + dst + XFLAG_AS_1();
FLAG_N = NFLAG_8(res);
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(addx, 8, mm, axy7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_A7_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = src + dst + XFLAG_AS_1();
FLAG_N = NFLAG_8(res);
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(addx, 8, mm, .)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_AX_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = src + dst + XFLAG_AS_1();
FLAG_N = NFLAG_8(res);
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(addx, 16, mm, .)
{
- uint src = OPER_AY_PD_16();
+ uint src = OPER_AY_PD_16(state);
uint ea = EA_AX_PD_16();
- uint dst = m68ki_read_16(ea);
+ uint dst = m68ki_read_16(state, ea);
uint res = src + dst + XFLAG_AS_1();
FLAG_N = NFLAG_16(res);
res = MASK_OUT_ABOVE_16(res);
FLAG_Z |= res;
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
}
M68KMAKE_OP(addx, 32, mm, .)
{
- uint src = OPER_AY_PD_32();
+ uint src = OPER_AY_PD_32(state);
uint ea = EA_AX_PD_32();
- uint dst = m68ki_read_32(ea);
+ uint dst = m68ki_read_32(state, ea);
uint res = src + dst + XFLAG_AS_1();
FLAG_N = NFLAG_32(res);
res = MASK_OUT_ABOVE_32(res);
FLAG_Z |= res;
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
}
M68KMAKE_OP(and, 8, re, .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint res = DX & m68ki_read_8(ea);
+ uint res = DX & m68ki_read_8(state, ea);
FLAG_N = NFLAG_8(res);
FLAG_C = CFLAG_CLEAR;
FLAG_V = VFLAG_CLEAR;
FLAG_Z = MASK_OUT_ABOVE_8(res);
- m68ki_write_8(ea, FLAG_Z);
+ m68ki_write_8(state, ea, FLAG_Z);
}
M68KMAKE_OP(and, 16, re, .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint res = DX & m68ki_read_16(ea);
+ uint res = DX & m68ki_read_16(state, ea);
FLAG_N = NFLAG_16(res);
FLAG_C = CFLAG_CLEAR;
FLAG_V = VFLAG_CLEAR;
FLAG_Z = MASK_OUT_ABOVE_16(res);
- m68ki_write_16(ea, FLAG_Z);
+ m68ki_write_16(state, ea, FLAG_Z);
}
M68KMAKE_OP(and, 32, re, .)
{
uint ea = M68KMAKE_GET_EA_AY_32;
- uint res = DX & m68ki_read_32(ea);
+ uint res = DX & m68ki_read_32(state, ea);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
FLAG_V = VFLAG_CLEAR;
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
}
M68KMAKE_OP(andi, 8, ., d)
{
- FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
+ FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8(state) | 0xffffff00));
FLAG_N = NFLAG_8(FLAG_Z);
FLAG_C = CFLAG_CLEAR;
M68KMAKE_OP(andi, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
- uint res = src & m68ki_read_8(ea);
+ uint res = src & m68ki_read_8(state, ea);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
FLAG_V = VFLAG_CLEAR;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(andi, 16, ., d)
{
- FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
+ FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16(state) | 0xffff0000));
FLAG_N = NFLAG_16(FLAG_Z);
FLAG_C = CFLAG_CLEAR;
M68KMAKE_OP(andi, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
- uint res = src & m68ki_read_16(ea);
+ uint res = src & m68ki_read_16(state, ea);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
FLAG_V = VFLAG_CLEAR;
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
}
M68KMAKE_OP(andi, 32, ., d)
{
- FLAG_Z = DY &= (OPER_I_32());
+ FLAG_Z = DY &= (OPER_I_32(state));
FLAG_N = NFLAG_32(FLAG_Z);
FLAG_C = CFLAG_CLEAR;
M68KMAKE_OP(andi, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
- uint res = src & m68ki_read_32(ea);
+ uint res = src & m68ki_read_32(state, ea);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
FLAG_V = VFLAG_CLEAR;
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
}
M68KMAKE_OP(andi, 16, toc, .)
{
- m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8());
+ m68ki_set_ccr(state, m68ki_get_ccr(state) & OPER_I_8(state));
}
{
if(FLAG_S)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_set_sr(m68ki_get_sr() & src);
+ m68ki_set_sr(state, m68ki_get_sr() & src);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
M68KMAKE_OP(asr, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = src >> 1;
if(GET_MSB_16(src))
res |= 0x8000;
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(asl, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = MASK_OUT_ABOVE_16(src << 1);
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
if(M68KMAKE_CC)
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+ m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
return;
}
USE_CYCLES(CYC_BCC_NOTAKE_B);
{
if(M68KMAKE_CC)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
REG_PC -= 2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_16(offset);
+ m68ki_branch_16(state, offset);
return;
}
REG_PC += 2;
{
if(M68KMAKE_CC)
{
- uint offset = OPER_I_32();
+ uint offset = OPER_I_32(state);
REG_PC -= 4;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_32(offset);
+ m68ki_branch_32(state, offset);
return;
}
REG_PC += 4;
if(M68KMAKE_CC)
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+ m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
return;
}
USE_CYCLES(CYC_BCC_NOTAKE_B);
M68KMAKE_OP(bchg, 8, r, .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint src = m68ki_read_8(ea);
+ uint src = m68ki_read_8(state, ea);
uint mask = 1 << (DX & 7);
FLAG_Z = src & mask;
- m68ki_write_8(ea, src ^ mask);
+ m68ki_write_8(state, ea, src ^ mask);
}
M68KMAKE_OP(bchg, 32, s, d)
{
uint* r_dst = &DY;
- uint mask = 1 << (OPER_I_8() & 0x1f);
+ uint mask = 1 << (OPER_I_8(state) & 0x1f);
FLAG_Z = *r_dst & mask;
*r_dst ^= mask;
M68KMAKE_OP(bchg, 8, s, .)
{
- uint mask = 1 << (OPER_I_8() & 7);
+ uint mask = 1 << (OPER_I_8(state) & 7);
uint ea = M68KMAKE_GET_EA_AY_8;
- uint src = m68ki_read_8(ea);
+ uint src = m68ki_read_8(state, ea);
FLAG_Z = src & mask;
- m68ki_write_8(ea, src ^ mask);
+ m68ki_write_8(state, ea, src ^ mask);
}
M68KMAKE_OP(bclr, 8, r, .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint src = m68ki_read_8(ea);
+ uint src = m68ki_read_8(state, ea);
uint mask = 1 << (DX & 7);
FLAG_Z = src & mask;
- m68ki_write_8(ea, src & ~mask);
+ m68ki_write_8(state, ea, src & ~mask);
}
M68KMAKE_OP(bclr, 32, s, d)
{
uint* r_dst = &DY;
- uint mask = 1 << (OPER_I_8() & 0x1f);
+ uint mask = 1 << (OPER_I_8(state) & 0x1f);
FLAG_Z = *r_dst & mask;
*r_dst &= ~mask;
M68KMAKE_OP(bclr, 8, s, .)
{
- uint mask = 1 << (OPER_I_8() & 7);
+ uint mask = 1 << (OPER_I_8(state) & 7);
uint ea = M68KMAKE_GET_EA_AY_8;
- uint src = m68ki_read_8(ea);
+ uint src = m68ki_read_8(state, ea);
FLAG_Z = src & mask;
- m68ki_write_8(ea, src & ~mask);
+ m68ki_write_8(state, ea, src & ~mask);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint mask_base;
mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
mask_long = mask_base >> offset;
- data_long = m68ki_read_32(ea);
+ data_long = m68ki_read_32(state, ea);
FLAG_N = NFLAG_32(data_long << offset);
FLAG_Z = data_long & mask_long;
FLAG_V = VFLAG_CLEAR;
FLAG_C = CFLAG_CLEAR;
- m68ki_write_32(ea, data_long ^ mask_long);
+ m68ki_write_32(state, ea, data_long ^ mask_long);
if((width + offset) > 32)
{
mask_byte = MASK_OUT_ABOVE_8(mask_base) << (8-offset);
- data_byte = m68ki_read_8(ea+4);
+ data_byte = m68ki_read_8(state, ea+4);
FLAG_Z |= (data_byte & mask_byte);
- m68ki_write_8(ea+4, data_byte ^ mask_byte);
+ m68ki_write_8(state, ea+4, data_byte ^ mask_byte);
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint mask_base;
mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
mask_long = mask_base >> offset;
- data_long = m68ki_read_32(ea);
+ data_long = m68ki_read_32(state, ea);
FLAG_N = NFLAG_32(data_long << offset);
FLAG_Z = data_long & mask_long;
FLAG_V = VFLAG_CLEAR;
FLAG_C = CFLAG_CLEAR;
- m68ki_write_32(ea, data_long & ~mask_long);
+ m68ki_write_32(state, ea, data_long & ~mask_long);
if((width + offset) > 32)
{
mask_byte = MASK_OUT_ABOVE_8(mask_base) << (8-offset);
- data_byte = m68ki_read_8(ea+4);
+ data_byte = m68ki_read_8(state, ea+4);
FLAG_Z |= (data_byte & mask_byte);
- m68ki_write_8(ea+4, data_byte & ~mask_byte);
+ m68ki_write_8(state, ea+4, data_byte & ~mask_byte);
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint64 data = DY;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint data;
}
width = ((width-1) & 31) + 1;
- data = (offset+width) < 8 ? (m68ki_read_8(ea) << 24) :
- (offset+width) < 16 ? (m68ki_read_16(ea) << 16) : m68ki_read_32(ea);
+ data = (offset+width) < 8 ? (m68ki_read_8(state, ea) << 24) :
+ (offset+width) < 16 ? (m68ki_read_16(state, ea) << 16) : m68ki_read_32(state, ea);
data = MASK_OUT_ABOVE_32(data<<offset);
if((offset+width) > 32)
- data |= (m68ki_read_8(ea+4) << offset) >> 8;
+ data |= (m68ki_read_8(state, ea+4) << offset) >> 8;
FLAG_N = NFLAG_32(data);
data = MAKE_INT_32(data) >> (32 - width);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint64 data = DY;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint data;
}
width = ((width-1) & 31) + 1;
- data = (offset+width) < 8 ? (m68ki_read_8(ea) << 24) :
- (offset+width) < 16 ? (m68ki_read_16(ea) << 16) : m68ki_read_32(ea);
+ data = (offset+width) < 8 ? (m68ki_read_8(state, ea) << 24) :
+ (offset+width) < 16 ? (m68ki_read_16(state, ea) << 16) : m68ki_read_32(state, ea);
data = MASK_OUT_ABOVE_32(data<<offset);
if((offset+width) > 32)
- data |= (m68ki_read_8(ea+4) << offset) >> 8;
+ data |= (m68ki_read_8(state, ea+4) << offset) >> 8;
FLAG_N = NFLAG_32(data);
data >>= (32 - width);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint64 data = DY;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
sint local_offset;
uint width = word2;
}
width = ((width-1) & 31) + 1;
- data = (offset+width) < 16 ? (m68ki_read_16(ea) << 16) : m68ki_read_32(ea);
+ data = (offset+width) < 16 ? (m68ki_read_16(state, ea) << 16) : m68ki_read_32(state, ea);
data = MASK_OUT_ABOVE_32(data<<local_offset);
if((local_offset+width) > 32)
- data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+ data |= (m68ki_read_8(state, ea+4) << local_offset) >> 8;
FLAG_N = NFLAG_32(data);
data >>= (32 - width);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint insert_base = REG_D[(word2>>12)&7];
FLAG_Z = insert_base;
insert_long = insert_base >> offset;
- data_long = (offset+width) < 8 ? (m68ki_read_8(ea) << 24) :
- (offset+width) < 16 ? (m68ki_read_16(ea) << 16) : m68ki_read_32(ea);
+ data_long = (offset+width) < 8 ? (m68ki_read_8(state, ea) << 24) :
+ (offset+width) < 16 ? (m68ki_read_16(state, ea) << 16) : m68ki_read_32(state, ea);
FLAG_V = VFLAG_CLEAR;
FLAG_C = CFLAG_CLEAR;
if((width + offset) < 8) {
- m68ki_write_8(ea, ((data_long & ~mask_long) | insert_long) >> 24);
+ m68ki_write_8(state, ea, ((data_long & ~mask_long) | insert_long) >> 24);
} else if((width + offset) < 16) {
- m68ki_write_16(ea, ((data_long & ~mask_long) | insert_long) >> 16);
+ m68ki_write_16(state, ea, ((data_long & ~mask_long) | insert_long) >> 16);
} else {
- m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+ m68ki_write_32(state, ea, (data_long & ~mask_long) | insert_long);
}
if((width + offset) > 32)
{
mask_byte = MASK_OUT_ABOVE_8(mask_base);
insert_byte = MASK_OUT_ABOVE_8(insert_base);
- data_byte = m68ki_read_8(ea+4);
+ data_byte = m68ki_read_8(state, ea+4);
FLAG_Z |= (data_byte & mask_byte);
- m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+ m68ki_write_8(state, ea+4, (data_byte & ~mask_byte) | insert_byte);
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint mask_base;
mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
mask_long = mask_base >> offset;
- data_long = m68ki_read_32(ea);
+ data_long = m68ki_read_32(state, ea);
FLAG_N = NFLAG_32(data_long << offset);
FLAG_Z = data_long & mask_long;
FLAG_V = VFLAG_CLEAR;
FLAG_C = CFLAG_CLEAR;
- m68ki_write_32(ea, data_long | mask_long);
+ m68ki_write_32(state, ea, data_long | mask_long);
if((width + offset) > 32)
{
mask_byte = MASK_OUT_ABOVE_8(mask_base);
- data_byte = m68ki_read_8(ea+4);
+ data_byte = m68ki_read_8(state, ea+4);
FLAG_Z |= (data_byte & mask_byte);
- m68ki_write_8(ea+4, data_byte | mask_byte);
+ m68ki_write_8(state, ea+4, data_byte | mask_byte);
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint mask_base;
mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
mask_long = mask_base >> offset;
- data_long = m68ki_read_32(ea);
+ data_long = m68ki_read_32(state, ea);
FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
FLAG_Z = data_long & mask_long;
FLAG_V = VFLAG_CLEAR;
if((width + offset) > 32)
{
mask_byte = MASK_OUT_ABOVE_8(mask_base);
- data_byte = m68ki_read_8(ea+4);
+ data_byte = m68ki_read_8(state, ea+4);
FLAG_Z |= (data_byte & mask_byte);
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(bra, 8, ., .)
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+ m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
// TODO: review this...
// if(REG_PC == REG_PPC)
// USE_ALL_CYCLES();
M68KMAKE_OP(bra, 16, ., .)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
REG_PC -= 2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_16(offset);
+ m68ki_branch_16(state, offset);
// TODO: review this...
// if(REG_PC == REG_PPC)
// USE_ALL_CYCLES();
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint offset = OPER_I_32();
+ uint offset = OPER_I_32(state);
REG_PC -= 4;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_32(offset);
+ m68ki_branch_32(state, offset);
// TODO: review this...
// if(REG_PC == REG_PPC)
// USE_ALL_CYCLES();
else
{
// TODO: review this...
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
// m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
-// m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+// m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
// if(REG_PC == REG_PPC)
// USE_ALL_CYCLES();
}
M68KMAKE_OP(bset, 8, r, .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint src = m68ki_read_8(ea);
+ uint src = m68ki_read_8(state, ea);
uint mask = 1 << (DX & 7);
FLAG_Z = src & mask;
- m68ki_write_8(ea, src | mask);
+ m68ki_write_8(state, ea, src | mask);
}
M68KMAKE_OP(bset, 32, s, d)
{
uint* r_dst = &DY;
- uint mask = 1 << (OPER_I_8() & 0x1f);
+ uint mask = 1 << (OPER_I_8(state) & 0x1f);
FLAG_Z = *r_dst & mask;
*r_dst |= mask;
M68KMAKE_OP(bset, 8, s, .)
{
- uint mask = 1 << (OPER_I_8() & 7);
+ uint mask = 1 << (OPER_I_8(state) & 7);
uint ea = M68KMAKE_GET_EA_AY_8;
- uint src = m68ki_read_8(ea);
+ uint src = m68ki_read_8(state, ea);
FLAG_Z = src & mask;
- m68ki_write_8(ea, src | mask);
+ m68ki_write_8(state, ea, src | mask);
}
M68KMAKE_OP(bsr, 8, ., .)
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_push_32(REG_PC);
- m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+ m68ki_push_32(state, REG_PC);
+ m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
}
M68KMAKE_OP(bsr, 16, ., .)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_push_32(REG_PC);
+ m68ki_push_32(state, REG_PC);
REG_PC -= 2;
- m68ki_branch_16(offset);
+ m68ki_branch_16(state, offset);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint offset = OPER_I_32();
+ uint offset = OPER_I_32(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_push_32(REG_PC);
+ m68ki_push_32(state, REG_PC);
REG_PC -= 4;
- m68ki_branch_32(offset);
+ m68ki_branch_32(state, offset);
return;
}
else
{
// TODO: review this...
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
// m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
-// m68ki_push_32(REG_PC);
-// m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+// m68ki_push_32(state, REG_PC);
+// m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
}
}
M68KMAKE_OP(btst, 32, s, d)
{
- FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
+ FLAG_Z = DY & (1 << (OPER_I_8(state) & 0x1f));
}
M68KMAKE_OP(btst, 8, s, .)
{
- uint bit = OPER_I_8() & 7;
+ uint bit = OPER_I_8(state) & 7;
FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
}
m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_8;
- uint dest = m68ki_read_8(ea);
+ uint dest = m68ki_read_8(state, ea);
uint* compare = ®_D[word2 & 7];
uint res = dest - MASK_OUT_ABOVE_8(*compare);
else
{
USE_CYCLES(3);
- m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+ m68ki_write_8(state, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
- uint dest = m68ki_read_16(ea);
+ uint dest = m68ki_read_16(state, ea);
uint* compare = ®_D[word2 & 7];
uint res = dest - MASK_OUT_ABOVE_16(*compare);
else
{
USE_CYCLES(3);
- m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+ m68ki_write_16(state, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_32;
- uint dest = m68ki_read_32(ea);
+ uint dest = m68ki_read_32(state, ea);
uint* compare = ®_D[word2 & 7];
uint res = dest - *compare;
else
{
USE_CYCLES(3);
- m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+ m68ki_write_32(state, ea, REG_D[(word2 >> 6) & 7]);
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_32();
+ uint word2 = OPER_I_32(state);
uint* compare1 = ®_D[(word2 >> 16) & 7];
uint ea1 = REG_DA[(word2 >> 28) & 15];
- uint dest1 = m68ki_read_16(ea1);
+ uint dest1 = m68ki_read_16(state, ea1);
uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
uint* compare2 = ®_D[word2 & 7];
uint ea2 = REG_DA[(word2 >> 12) & 15];
- uint dest2 = m68ki_read_16(ea2);
+ uint dest2 = m68ki_read_16(state, ea2);
uint res2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
if(COND_EQ())
{
USE_CYCLES(3);
- m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
- m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
+ m68ki_write_16(state, ea1, REG_D[(word2 >> 22) & 7]);
+ m68ki_write_16(state, ea2, REG_D[(word2 >> 6) & 7]);
return;
}
}
*compare2 = BIT_F(word2) ? (uint)MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_32();
+ uint word2 = OPER_I_32(state);
uint* compare1 = ®_D[(word2 >> 16) & 7];
uint ea1 = REG_DA[(word2 >> 28) & 15];
- uint dest1 = m68ki_read_32(ea1);
+ uint dest1 = m68ki_read_32(state, ea1);
uint res1 = dest1 - *compare1;
uint* compare2 = ®_D[word2 & 7];
uint ea2 = REG_DA[(word2 >> 12) & 15];
- uint dest2 = m68ki_read_32(ea2);
+ uint dest2 = m68ki_read_32(state, ea2);
uint res2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
if(COND_EQ())
{
USE_CYCLES(3);
- m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
- m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
+ m68ki_write_32(state, ea1, REG_D[(word2 >> 22) & 7]);
+ m68ki_write_32(state, ea2, REG_D[(word2 >> 6) & 7]);
return;
}
}
*compare2 = dest2;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
return;
}
FLAG_N = (src < 0)<<7;
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
}
return;
}
FLAG_N = (src < 0)<<7;
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
}
return;
}
FLAG_N = (src < 0)<<7;
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
return;
}
FLAG_N = (src < 0)<<7;
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xff;
uint ea = EA_PCDI_8();
- sint lower_bound = m68ki_read_pcrel_8(ea);
- sint upper_bound = m68ki_read_pcrel_8(ea + 1);
+ sint lower_bound = m68ki_read_pcrel_8(state, ea);
+ sint upper_bound = m68ki_read_pcrel_8(state, ea + 1);
// for signed compare, the arithmetically smaller value is the lower bound
if (lower_bound & 0x80) {
FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
if(COND_CS() && BIT_B(word2))
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
-
- m68ki_exception_illegal();
+
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xff;
uint ea = EA_PCIX_8();
- sint lower_bound = m68ki_read_pcrel_8(ea);
- sint upper_bound = m68ki_read_pcrel_8(ea + 1);
+ sint lower_bound = m68ki_read_pcrel_8(state, ea);
+ sint upper_bound = m68ki_read_pcrel_8(state, ea + 1);
if (lower_bound & 0x80) {
lower_bound = (int32)(int8)lower_bound;
FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
if(COND_CS() && BIT_B(word2))
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xff;
uint ea = M68KMAKE_GET_EA_AY_8;
- sint lower_bound = (int8)m68ki_read_8(ea);
- sint upper_bound = (int8)m68ki_read_8(ea + 1);
+ sint lower_bound = (int8)m68ki_read_8(state, ea);
+ sint upper_bound = (int8)m68ki_read_8(state, ea + 1);
// for signed compare, the arithmetically smaller value is the lower bound
if (lower_bound & 0x80) {
FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
if(COND_CS() && BIT_B(word2))
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xffff;
uint ea = EA_PCDI_16();
- sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
- sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
+ sint lower_bound = (int16)m68ki_read_pcrel_16(state, ea);
+ sint upper_bound = (int16)m68ki_read_pcrel_16(state, ea + 2);
// for signed compare, the arithmetically smaller value is the lower bound
if (lower_bound & 0x8000) {
FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
if(COND_CS() && BIT_B(word2))
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xffff;
uint ea = EA_PCIX_16();
- sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
- sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
+ sint lower_bound = (int16)m68ki_read_pcrel_16(state, ea);
+ sint upper_bound = (int16)m68ki_read_pcrel_16(state, ea + 2);
// for signed compare, the arithmetically smaller value is the lower bound
if (lower_bound & 0x8000) {
FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
if(COND_CS() && BIT_B(word2))
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xffff;
uint ea = M68KMAKE_GET_EA_AY_16;
- sint lower_bound = (int16)m68ki_read_16(ea);
- sint upper_bound = (int16)m68ki_read_16(ea + 2);
+ sint lower_bound = (int16)m68ki_read_16(state, ea);
+ sint upper_bound = (int16)m68ki_read_16(state, ea + 2);
// for signed compare, the arithmetically smaller value is the lower bound
if (lower_bound & 0x8000) {
FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
if(COND_CS() && BIT_B(word2))
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint32 word2 = OPER_I_16();
+ uint32 word2 = OPER_I_16(state);
sint64 compare = REG_DA[(word2 >> 12) & 15];
uint32 ea = EA_PCDI_32();
- sint64 lower_bound = m68ki_read_pcrel_32(ea);
- sint64 upper_bound = m68ki_read_pcrel_32(ea + 4);
+ sint64 lower_bound = m68ki_read_pcrel_32(state, ea);
+ sint64 upper_bound = m68ki_read_pcrel_32(state, ea + 4);
// for signed compare, the arithmetically smaller value is the lower bound
if (lower_bound & 0x80000000) {
FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
if(COND_CS() && BIT_B(word2))
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint32 word2 = OPER_I_16();
+ uint32 word2 = OPER_I_16(state);
sint64 compare = REG_DA[(word2 >> 12) & 15];
uint32 ea = EA_PCIX_32();
- sint64 lower_bound = m68ki_read_32(ea);
- sint64 upper_bound = m68ki_read_32(ea + 4);
+ sint64 lower_bound = m68ki_read_32(state, ea);
+ sint64 upper_bound = m68ki_read_32(state, ea + 4);
// for signed compare, the arithmetically smaller value is the lower bound
if (lower_bound & 0x80000000) {
FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
if(COND_CS() && BIT_B(word2))
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(chk2cmp2, 32, ., .)
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
- {
- uint32 word2 = OPER_I_16();
+ {
+ uint32 word2 = OPER_I_16(state);
sint64 compare = REG_DA[(word2 >> 12) & 15];
uint32 ea = M68KMAKE_GET_EA_AY_32;
- sint64 lower_bound = m68ki_read_32(ea);
- sint64 upper_bound = m68ki_read_32(ea + 4);
+ sint64 lower_bound = m68ki_read_32(state, ea);
+ sint64 upper_bound = m68ki_read_32(state, ea + 4);
// for signed compare, the arithmetically smaller value is the lower bound
if (lower_bound & 0x80000000) {
FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
if(COND_CS() && BIT_B(word2))
- m68ki_exception_trap(EXCEPTION_CHK);
+ m68ki_exception_trap(state, EXCEPTION_CHK);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
uint32 ea = M68KMAKE_GET_EA_AY_8;
if(CPU_TYPE_IS_000(CPU_TYPE))
- m68ki_read_8(ea); /* the 68000 does a dummy read, the value is discarded */
- m68ki_write_8(ea, 0);
+ m68ki_read_8(state, ea); /* the 68000 does a dummy read, the value is discarded */
+ m68ki_write_8(state, ea, 0);
FLAG_N = NFLAG_CLEAR;
FLAG_V = VFLAG_CLEAR;
uint32 ea = M68KMAKE_GET_EA_AY_16;
if(CPU_TYPE_IS_000(CPU_TYPE))
- m68ki_read_16(ea); /* the 68000 does a dummy read, the value is discarded */
- m68ki_write_16(ea, 0);
+ m68ki_read_16(state, ea); /* the 68000 does a dummy read, the value is discarded */
+ m68ki_write_16(state, ea, 0);
FLAG_N = NFLAG_CLEAR;
FLAG_V = VFLAG_CLEAR;
uint32 ea = M68KMAKE_GET_EA_AY_32;
if(CPU_TYPE_IS_000(CPU_TYPE))
- m68ki_read_32(ea); /* the 68000 does a dummy read, the value is discarded */
- m68ki_write_32(ea, 0);
+ m68ki_read_32(state, ea); /* the 68000 does a dummy read, the value is discarded */
+ m68ki_write_32(state, ea, 0);
FLAG_N = NFLAG_CLEAR;
FLAG_V = VFLAG_CLEAR;
M68KMAKE_OP(cmpi, 8, ., d)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint dst = MASK_OUT_ABOVE_8(DY);
uint res = dst - src;
M68KMAKE_OP(cmpi, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint dst = M68KMAKE_GET_OPER_AY_8;
uint res = dst - src;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_8();
- uint dst = OPER_PCDI_8();
+ uint src = OPER_I_8(state);
+ uint dst = OPER_PCDI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
FLAG_C = CFLAG_8(res);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_8();
- uint dst = OPER_PCIX_8();
+ uint src = OPER_I_8(state);
+ uint dst = OPER_PCIX_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
FLAG_C = CFLAG_8(res);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(cmpi, 16, ., d)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint dst = MASK_OUT_ABOVE_16(DY);
uint res = dst - src;
M68KMAKE_OP(cmpi, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint dst = M68KMAKE_GET_OPER_AY_16;
uint res = dst - src;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_16();
- uint dst = OPER_PCDI_16();
+ uint src = OPER_I_16(state);
+ uint dst = OPER_PCDI_16(state);
uint res = dst - src;
FLAG_N = NFLAG_16(res);
FLAG_C = CFLAG_16(res);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_16();
- uint dst = OPER_PCIX_16();
+ uint src = OPER_I_16(state);
+ uint dst = OPER_PCIX_16(state);
uint res = dst - src;
FLAG_N = NFLAG_16(res);
FLAG_C = CFLAG_16(res);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(cmpi, 32, ., d)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint dst = DY;
uint res = dst - src;
M68KMAKE_OP(cmpi, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint dst = M68KMAKE_GET_OPER_AY_32;
uint res = dst - src;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_32();
- uint dst = OPER_PCDI_32();
+ uint src = OPER_I_32(state);
+ uint dst = OPER_PCDI_32(state);
uint res = dst - src;
FLAG_N = NFLAG_32(res);
FLAG_C = CFLAG_SUB_32(src, dst, res);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_32();
- uint dst = OPER_PCIX_32();
+ uint src = OPER_I_32(state);
+ uint dst = OPER_PCIX_32(state);
uint res = dst - src;
FLAG_N = NFLAG_32(res);
FLAG_C = CFLAG_SUB_32(src, dst, res);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(cmpm, 8, ., ax7)
{
- uint src = OPER_AY_PI_8();
- uint dst = OPER_A7_PI_8();
+ uint src = OPER_AY_PI_8(state);
+ uint dst = OPER_A7_PI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
M68KMAKE_OP(cmpm, 8, ., ay7)
{
- uint src = OPER_A7_PI_8();
- uint dst = OPER_AX_PI_8();
+ uint src = OPER_A7_PI_8(state);
+ uint dst = OPER_AX_PI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
M68KMAKE_OP(cmpm, 8, ., axy7)
{
- uint src = OPER_A7_PI_8();
- uint dst = OPER_A7_PI_8();
+ uint src = OPER_A7_PI_8(state);
+ uint dst = OPER_A7_PI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
M68KMAKE_OP(cmpm, 8, ., .)
{
- uint src = OPER_AY_PI_8();
- uint dst = OPER_AX_PI_8();
+ uint src = OPER_AY_PI_8(state);
+ uint dst = OPER_AX_PI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
M68KMAKE_OP(cmpm, 16, ., .)
{
- uint src = OPER_AY_PI_16();
- uint dst = OPER_AX_PI_16();
+ uint src = OPER_AY_PI_16(state);
+ uint dst = OPER_AX_PI_16(state);
uint res = dst - src;
FLAG_N = NFLAG_16(res);
M68KMAKE_OP(cmpm, 32, ., .)
{
- uint src = OPER_AY_PI_32();
- uint dst = OPER_AX_PI_32();
+ uint src = OPER_AY_PI_32(state);
+ uint dst = OPER_AX_PI_32(state);
uint res = dst - src;
FLAG_N = NFLAG_32(res);
m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
return;
}
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
return;
}
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
return;
}
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
return;
}
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
// JFF: unsupported, but at least if the trap doesn't occur, app should still work, so at least PC increase is correct
- REG_PC += 4;
+ REG_PC += 4;
return;
}
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
M68KMAKE_OP(ftrapcc,32, ., .)
{
if(HAS_FPU)
{
- m68881_ftrap();
+ m68881_ftrap(state);
} else {
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
}
*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
if(res != 0xffff)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
REG_PC -= 2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_16(offset);
+ m68ki_branch_16(state, offset);
USE_CYCLES(CYC_DBCC_F_NOEXP);
return;
}
*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
if(res != 0xffff)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
REG_PC -= 2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_16(offset);
+ m68ki_branch_16(state, offset);
USE_CYCLES(CYC_DBCC_F_NOEXP);
return;
}
FLAG_V = VFLAG_SET;
return;
}
- m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+ m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
}
FLAG_V = VFLAG_SET;
return;
}
- m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+ m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
}
FLAG_V = VFLAG_SET;
return;
}
- m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+ m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
}
FLAG_V = VFLAG_SET;
return;
}
- m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+ m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint64 divisor = DY;
uint64 dividend = 0;
uint64 quotient = 0;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+ m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
#else
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint divisor = DY;
uint dividend_hi = REG_D[word2 & 7];
uint dividend_lo = REG_D[(word2 >> 12) & 7];
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+ m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
#endif
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint64 divisor = M68KMAKE_GET_OPER_AY_32;
uint64 dividend = 0;
uint64 quotient = 0;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+ m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
#else
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint divisor = M68KMAKE_GET_OPER_AY_32;
uint dividend_hi = REG_D[word2 & 7];
uint dividend_lo = REG_D[(word2 >> 12) & 7];
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+ m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
#endif
}
M68KMAKE_OP(eor, 8, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+ uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(state, ea));
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
M68KMAKE_OP(eor, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+ uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(state, ea));
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(eor, 32, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_32;
- uint res = DX ^ m68ki_read_32(ea);
+ uint res = DX ^ m68ki_read_32(state, ea);
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 8, ., d)
{
- uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
+ uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8(state));
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
- uint res = src ^ m68ki_read_8(ea);
+ uint res = src ^ m68ki_read_8(state, ea);
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 16, ., d)
{
- uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
+ uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16(state));
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
- uint res = src ^ m68ki_read_16(ea);
+ uint res = src ^ m68ki_read_16(state, ea);
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 32, ., d)
{
- uint res = DY ^= OPER_I_32();
+ uint res = DY ^= OPER_I_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
- uint res = src ^ m68ki_read_32(ea);
+ uint res = src ^ m68ki_read_32(state, ea);
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 16, toc, .)
{
- m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8());
+ m68ki_set_ccr(state, m68ki_get_ccr(state) ^ OPER_I_8(state));
}
{
if(FLAG_S)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_set_sr(m68ki_get_sr() ^ src);
+ m68ki_set_sr(state, m68ki_get_sr() ^ src);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(illegal, 0, ., .)
{
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(jmp, 32, ., .)
{
- m68ki_jump(M68KMAKE_GET_EA_AY_32);
+ m68ki_jump(state, M68KMAKE_GET_EA_AY_32);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
}
{
uint ea = M68KMAKE_GET_EA_AY_32;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_push_32(REG_PC);
- m68ki_jump(ea);
+ m68ki_push_32(state, REG_PC);
+ m68ki_jump(state, ea);
}
M68KMAKE_OP(link, 16, ., a7)
{
REG_A[7] -= 4;
- m68ki_write_32(REG_A[7], REG_A[7]);
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+ m68ki_write_32(state, REG_A[7], REG_A[7]);
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state)));
}
{
uint* r_dst = &AY;
- m68ki_push_32(*r_dst);
+ m68ki_push_32(state, *r_dst);
*r_dst = REG_A[7];
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state)));
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
REG_A[7] -= 4;
- m68ki_write_32(REG_A[7], REG_A[7]);
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
+ m68ki_write_32(state, REG_A[7], REG_A[7]);
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(state));
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
uint* r_dst = &AY;
- m68ki_push_32(*r_dst);
+ m68ki_push_32(state, *r_dst);
*r_dst = REG_A[7];
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(state));
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(lsr, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = src >> 1;
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_CLEAR;
FLAG_Z = res;
M68KMAKE_OP(lsl, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = MASK_OUT_ABOVE_16(src << 1);
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_8(DY);
uint ea = EA_AX_AI_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_8;
uint ea = EA_AX_AI_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_8(DY);
uint ea = EA_A7_PI_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_8(DY);
uint ea = EA_AX_PI_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_8;
uint ea = EA_A7_PI_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_8;
uint ea = EA_AX_PI_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_8(DY);
uint ea = EA_A7_PD_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_8(DY);
uint ea = EA_AX_PD_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_8;
uint ea = EA_A7_PD_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_8;
uint ea = EA_AX_PD_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_8(DY);
uint ea = EA_AX_DI_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_8;
uint ea = EA_AX_DI_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_8(DY);
uint ea = EA_AX_IX_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_8;
uint ea = EA_AX_IX_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_8(DY);
uint ea = EA_AW_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_8;
uint ea = EA_AW_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_8(DY);
uint ea = EA_AL_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_8;
uint ea = EA_AL_8();
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(DY);
uint ea = EA_AX_AI_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(AY);
uint ea = EA_AX_AI_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_16;
uint ea = EA_AX_AI_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(DY);
uint ea = EA_AX_PI_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(AY);
uint ea = EA_AX_PI_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_16;
uint ea = EA_AX_PI_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(DY);
uint ea = EA_AX_PD_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(AY);
uint ea = EA_AX_PD_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_16;
uint ea = EA_AX_PD_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(DY);
uint ea = EA_AX_DI_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(AY);
uint ea = EA_AX_DI_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_16;
uint ea = EA_AX_DI_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(DY);
uint ea = EA_AX_IX_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(AY);
uint ea = EA_AX_IX_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_16;
uint ea = EA_AX_IX_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(DY);
uint ea = EA_AW_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(AY);
uint ea = EA_AW_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_16;
uint ea = EA_AW_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(DY);
uint ea = EA_AL_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = MASK_OUT_ABOVE_16(AY);
uint ea = EA_AL_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_16;
uint ea = EA_AL_16();
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
uint res = DY;
uint ea = EA_AX_AI_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = AY;
uint ea = EA_AX_AI_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_32;
uint ea = EA_AX_AI_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = DY;
uint ea = EA_AX_PI_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = AY;
uint ea = EA_AX_PI_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_32;
uint ea = EA_AX_PI_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = DY;
uint ea = EA_AX_PD_32();
- m68ki_write_16(ea+2, res & 0xFFFF );
- m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+ m68ki_write_16(state, ea+2, res & 0xFFFF );
+ m68ki_write_16(state, ea, (res >> 16) & 0xFFFF );
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = AY;
uint ea = EA_AX_PD_32();
- m68ki_write_16(ea+2, res & 0xFFFF );
- m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+ m68ki_write_16(state, ea+2, res & 0xFFFF );
+ m68ki_write_16(state, ea, (res >> 16) & 0xFFFF );
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_32;
uint ea = EA_AX_PD_32();
- m68ki_write_16(ea+2, res & 0xFFFF );
- m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+ m68ki_write_16(state, ea+2, res & 0xFFFF );
+ m68ki_write_16(state, ea, (res >> 16) & 0xFFFF );
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = DY;
uint ea = EA_AX_DI_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = AY;
uint ea = EA_AX_DI_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_32;
uint ea = EA_AX_DI_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = DY;
uint ea = EA_AX_IX_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = AY;
uint ea = EA_AX_IX_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_32;
uint ea = EA_AX_IX_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = DY;
uint ea = EA_AW_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = AY;
uint ea = EA_AW_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_32;
uint ea = EA_AW_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = DY;
uint ea = EA_AL_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = AY;
uint ea = EA_AL_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint res = M68KMAKE_GET_OPER_AY_32;
uint ea = EA_AL_32();
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
{
- DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
+ DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr(state);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
{
- m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
+ m68ki_write_16(state, M68KMAKE_GET_EA_AY_16, m68ki_get_ccr(state));
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(move, 16, toc, d)
{
- m68ki_set_ccr(DY);
+ m68ki_set_ccr(state, DY);
}
M68KMAKE_OP(move, 16, toc, .)
{
- m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
+ m68ki_set_ccr(state, M68KMAKE_GET_OPER_AY_16);
}
DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
{
uint ea = M68KMAKE_GET_EA_AY_16;
- m68ki_write_16(ea, m68ki_get_sr());
+ m68ki_write_16(state, ea, m68ki_get_sr());
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
{
if(FLAG_S)
{
- m68ki_set_sr(DY);
+ m68ki_set_sr(state, DY);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
{
uint new_sr = M68KMAKE_GET_OPER_AY_16;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
AY = REG_USP;
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
REG_USP = AY;
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
switch (word2 & 0xfff)
REG_DA[(word2 >> 12) & 15] = REG_CAAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
break;
case 0x803: /* MSP */
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x804: /* ISP */
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x003: /* TC */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_tc;
+ REG_DA[(word2 >> 12) & 15] = state->mmu_tc;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x004: /* ITT0 */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_itt0;
+ REG_DA[(word2 >> 12) & 15] = state->mmu_itt0;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x005: /* ITT1 */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_itt1;
+ REG_DA[(word2 >> 12) & 15] = state->mmu_itt1;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x006: /* DTT0 */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_dtt0;
+ REG_DA[(word2 >> 12) & 15] = state->mmu_dtt0;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x007: /* DTT1 */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_dtt1;
+ REG_DA[(word2 >> 12) & 15] = state->mmu_dtt1;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x805: /* MMUSR */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_sr_040;
+ REG_DA[(word2 >> 12) & 15] = state->mmu_sr_040;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x806: /* URP */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_urp_aptr;
+ REG_DA[(word2 >> 12) & 15] = state->mmu_urp_aptr;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x807: /* SRP */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_srp_aptr;
+ REG_DA[(word2 >> 12) & 15] = state->mmu_srp_aptr;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
default:
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
}
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
switch (word2 & 0xfff)
}
if (REG_CACR & (M68K_CACR_CI | M68K_CACR_CEI)) {
- m68ki_ic_clear();
+ m68ki_ic_clear(state);
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x800: /* USP */
REG_USP = REG_DA[(word2 >> 12) & 15];
REG_CAAR = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x803: /* MSP */
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
REG_SP = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x804: /* ISP */
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
REG_ISP = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x003: /* TC */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- m68ki_cpu.mmu_tc = REG_DA[(word2 >> 12) & 15];
+ state->mmu_tc = REG_DA[(word2 >> 12) & 15];
- if (m68ki_cpu.mmu_tc & 0x8000)
+ if (state->mmu_tc & 0x8000)
{
- m68ki_cpu.pmmu_enabled = 1;
+ state->pmmu_enabled = 1;
}
else
{
- m68ki_cpu.pmmu_enabled = 0;
+ state->pmmu_enabled = 0;
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x004: /* ITT0 */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- m68ki_cpu.mmu_itt0 = REG_DA[(word2 >> 12) & 15];
+ state->mmu_itt0 = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x005: /* ITT1 */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- m68ki_cpu.mmu_itt1 = REG_DA[(word2 >> 12) & 15];
+ state->mmu_itt1 = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x006: /* DTT0 */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- m68ki_cpu.mmu_dtt0 = REG_DA[(word2 >> 12) & 15];
+ state->mmu_dtt0 = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x007: /* DTT1 */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- m68ki_cpu.mmu_dtt1 = REG_DA[(word2 >> 12) & 15];
+ state->mmu_dtt1 = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x805: /* MMUSR */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- m68ki_cpu.mmu_sr_040 = REG_DA[(word2 >> 12) & 15];
+ state->mmu_sr_040 = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x806: /* URP */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- m68ki_cpu.mmu_urp_aptr = REG_DA[(word2 >> 12) & 15];
+ state->mmu_urp_aptr = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
case 0x807: /* SRP */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
- m68ki_cpu.mmu_srp_aptr = REG_DA[(word2 >> 12) & 15];
+ state->mmu_srp_aptr = REG_DA[(word2 >> 12) & 15];
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
default:
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
return;
}
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(movem, 16, re, pd)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = AY;
uint count = 0;
if(register_list & (1 << i))
{
ea -= 2;
- m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
+ m68ki_write_16(state, ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
count++;
}
AY = ea;
M68KMAKE_OP(movem, 16, re, .)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+ m68ki_write_16(state, ea, MASK_OUT_ABOVE_16(REG_DA[i]));
ea += 2;
count++;
}
M68KMAKE_OP(movem, 32, re, pd)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = AY;
uint count = 0;
if(register_list & (1 << i))
{
ea -= 4;
- m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
- m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
+ m68ki_write_16(state, ea+2, REG_DA[15-i] & 0xFFFF );
+ m68ki_write_16(state, ea, (REG_DA[15-i] >> 16) & 0xFFFF );
count++;
}
AY = ea;
M68KMAKE_OP(movem, 32, re, .)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- m68ki_write_32(ea, REG_DA[i]);
+ m68ki_write_32(state, ea, REG_DA[i]);
ea += 4;
count++;
}
M68KMAKE_OP(movem, 16, er, pi)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = AY;
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+ REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(state, ea)));
ea += 2;
count++;
}
M68KMAKE_OP(movem, 16, er, pcdi)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = EA_PCDI_16();
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
+ REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(state, ea)));
ea += 2;
count++;
}
M68KMAKE_OP(movem, 16, er, pcix)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = EA_PCIX_16();
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
+ REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(state, ea)));
ea += 2;
count++;
}
M68KMAKE_OP(movem, 16, er, .)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+ REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(state, ea)));
ea += 2;
count++;
}
M68KMAKE_OP(movem, 32, er, pi)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = AY;
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- REG_DA[i] = m68ki_read_32(ea);
+ REG_DA[i] = m68ki_read_32(state, ea);
ea += 4;
count++;
}
M68KMAKE_OP(movem, 32, er, pcdi)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = EA_PCDI_32();
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- REG_DA[i] = m68ki_read_pcrel_32(ea);
+ REG_DA[i] = m68ki_read_pcrel_32(state, ea);
ea += 4;
count++;
}
M68KMAKE_OP(movem, 32, er, pcix)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = EA_PCIX_32();
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- REG_DA[i] = m68ki_read_pcrel_32(ea);
+ REG_DA[i] = m68ki_read_pcrel_32(state, ea);
ea += 4;
count++;
}
M68KMAKE_OP(movem, 32, er, .)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint count = 0;
for(; i < 16; i++)
if(register_list & (1 << i))
{
- REG_DA[i] = m68ki_read_32(ea);
+ REG_DA[i] = m68ki_read_32(state, ea);
ea += 4;
count++;
}
uint ea = EA_AY_DI_16();
uint src = DX;
- m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
- m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+ m68ki_write_8(state, ea, MASK_OUT_ABOVE_8(src >> 8));
+ m68ki_write_8(state, ea += 2, MASK_OUT_ABOVE_8(src));
}
uint ea = EA_AY_DI_32();
uint src = DX;
- m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
- m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
- m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
- m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+ m68ki_write_8(state, ea, MASK_OUT_ABOVE_8(src >> 24));
+ m68ki_write_8(state, ea += 2, MASK_OUT_ABOVE_8(src >> 16));
+ m68ki_write_8(state, ea += 2, MASK_OUT_ABOVE_8(src >> 8));
+ m68ki_write_8(state, ea += 2, MASK_OUT_ABOVE_8(src));
}
uint ea = EA_AY_DI_16();
uint* r_dst = &DX;
- *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(state, ea) << 8) + m68ki_read_8(state, ea + 2));
}
{
uint ea = EA_AY_DI_32();
- DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
- + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
+ DX = (m68ki_read_8(state, ea) << 24) + (m68ki_read_8(state, ea + 2) << 16)
+ + (m68ki_read_8(state, ea + 4) << 8) + m68ki_read_8(state, ea + 6);
}
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_8;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
if(BIT_B(word2)) /* Register to memory */
{
- m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+ m68ki_write_8_fc(state, ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
return;
}
if(BIT_F(word2)) /* Memory to address register */
{
- REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+ REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(state, ea, REG_SFC));
if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
USE_CYCLES(2);
return;
}
/* Memory to data register */
- REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+ REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(state, ea, REG_SFC);
if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
USE_CYCLES(2);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
if(BIT_B(word2)) /* Register to memory */
{
- m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+ m68ki_write_16_fc(state, ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
return;
}
if(BIT_F(word2)) /* Memory to address register */
{
- REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+ REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(state, ea, REG_SFC));
if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
USE_CYCLES(2);
return;
}
/* Memory to data register */
- REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+ REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(state, ea, REG_SFC);
if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
USE_CYCLES(2);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_32;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
if(BIT_B(word2)) /* Register to memory */
{
- m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+ m68ki_write_32_fc(state, ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
USE_CYCLES(2);
return;
}
/* Memory to register */
- REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+ REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(state, ea, REG_SFC);
if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
USE_CYCLES(2);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(move16, 32, ., .)
{
- uint16 w2 = OPER_I_16();
+ uint16 w2 = OPER_I_16(state);
int ax = REG_IR & 7;
int ay = (w2 >> 12) & 7;
- m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
- m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
- m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
- m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
+ m68ki_write_32(state, REG_A[ay], m68ki_read_32(state, REG_A[ax]));
+ m68ki_write_32(state, REG_A[ay]+4, m68ki_read_32(state, REG_A[ax]+4));
+ m68ki_write_32(state, REG_A[ay]+8, m68ki_read_32(state, REG_A[ax]+8));
+ m68ki_write_32(state, REG_A[ay]+12, m68ki_read_32(state, REG_A[ax]+12));
REG_A[ax] += 16;
REG_A[ay] += 16;
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint64 src = DY;
uint64 dst = REG_D[(word2 >> 12) & 7];
uint64 res;
REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
#else
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint src = DY;
uint dst = REG_D[(word2 >> 12) & 7];
uint neg = GET_MSB_32(src ^ dst);
FLAG_V = (hi != 0) << 7;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
#endif
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint64 src = M68KMAKE_GET_OPER_AY_32;
uint64 dst = REG_D[(word2 >> 12) & 7];
uint64 res;
REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
#else
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint src = M68KMAKE_GET_OPER_AY_32;
uint dst = REG_D[(word2 >> 12) & 7];
uint neg = GET_MSB_32(src ^ dst);
FLAG_V = (hi != 0) << 7;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
#endif
}
M68KMAKE_OP(nbcd, 8, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = - dst - XFLAG_AS_1();
if(res != 0)
FLAG_V &= ~res; /* Undefined V behavior part II */
- m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+ m68ki_write_8(state, ea, MASK_OUT_ABOVE_8(res));
FLAG_Z |= res;
FLAG_C = CFLAG_SET;
M68KMAKE_OP(neg, 8, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint src = m68ki_read_8(ea);
+ uint src = m68ki_read_8(state, ea);
uint res = 0 - src;
FLAG_N = NFLAG_8(res);
FLAG_V = src & res;
FLAG_Z = MASK_OUT_ABOVE_8(res);
- m68ki_write_8(ea, FLAG_Z);
+ m68ki_write_8(state, ea, FLAG_Z);
}
M68KMAKE_OP(neg, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = 0 - src;
FLAG_N = NFLAG_16(res);
FLAG_V = (src & res)>>8;
FLAG_Z = MASK_OUT_ABOVE_16(res);
- m68ki_write_16(ea, FLAG_Z);
+ m68ki_write_16(state, ea, FLAG_Z);
}
M68KMAKE_OP(neg, 32, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_32;
- uint src = m68ki_read_32(ea);
+ uint src = m68ki_read_32(state, ea);
uint res = 0 - src;
FLAG_N = NFLAG_32(res);
FLAG_V = (src & res)>>24;
FLAG_Z = MASK_OUT_ABOVE_32(res);
- m68ki_write_32(ea, FLAG_Z);
+ m68ki_write_32(state, ea, FLAG_Z);
}
M68KMAKE_OP(negx, 8, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint src = m68ki_read_8(ea);
+ uint src = m68ki_read_8(state, ea);
uint res = 0 - src - XFLAG_AS_1();
FLAG_N = NFLAG_8(res);
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(negx, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
FLAG_N = NFLAG_16(res);
res = MASK_OUT_ABOVE_16(res);
FLAG_Z |= res;
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
}
M68KMAKE_OP(negx, 32, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_32;
- uint src = m68ki_read_32(ea);
+ uint src = m68ki_read_32(state, ea);
uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
FLAG_N = NFLAG_32(res);
res = MASK_OUT_ABOVE_32(res);
FLAG_Z |= res;
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
}
M68KMAKE_OP(not, 8, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+ uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(state, ea));
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
M68KMAKE_OP(not, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+ uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(state, ea));
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(not, 32, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_32;
- uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+ uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(state, ea));
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
M68KMAKE_OP(or, 8, re, .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+ uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(state, ea));
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
M68KMAKE_OP(or, 16, re, .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+ uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(state, ea));
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(or, 32, re, .)
{
uint ea = M68KMAKE_GET_EA_AY_32;
- uint res = DX | m68ki_read_32(ea);
+ uint res = DX | m68ki_read_32(state, ea);
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 8, ., d)
{
- uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
+ uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8(state)));
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
- uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+ uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(state, ea));
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 16, ., d)
{
- uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
+ uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16(state));
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
- uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+ uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(state, ea));
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 32, ., d)
{
- uint res = DY |= OPER_I_32();
+ uint res = DY |= OPER_I_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
- uint res = src | m68ki_read_32(ea);
+ uint res = src | m68ki_read_32(state, ea);
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 16, toc, .)
{
- m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8());
+ m68ki_set_ccr(state, m68ki_get_ccr(state) | OPER_I_8(state));
}
{
if(FLAG_S)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_set_sr(m68ki_get_sr() | src);
+ m68ki_set_sr(state, m68ki_get_sr() | src);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
/* Note: DX and DY are reversed in Motorola's docs */
- uint src = DY + OPER_I_16();
+ uint src = DY + OPER_I_16(state);
uint* r_dst = &DX;
*r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
/* Note: AX and AY are reversed in Motorola's docs */
uint ea_src = EA_AY_PD_8();
- uint src = m68ki_read_8(ea_src);
+ uint src = m68ki_read_8(state, ea_src);
ea_src = EA_AY_PD_8();
- src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+ src = ((src << 8) | m68ki_read_8(state, ea_src)) + OPER_I_16(state);
- m68ki_write_8(EA_A7_PD_8(), ((src >> 8) & 0x000f) | ((src<<4) & 0x00f0));
+ m68ki_write_8(state, EA_A7_PD_8(), ((src >> 8) & 0x000f) | ((src<<4) & 0x00f0));
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
/* Note: AX and AY are reversed in Motorola's docs */
uint ea_src = EA_A7_PD_8();
- uint src = m68ki_read_8(ea_src);
+ uint src = m68ki_read_8(state, ea_src);
ea_src = EA_A7_PD_8();
- src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16();
+ src = (src | (m68ki_read_8(state, ea_src) << 8)) + OPER_I_16(state);
- m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+ m68ki_write_8(state, EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
uint ea_src = EA_A7_PD_8();
- uint src = m68ki_read_8(ea_src);
+ uint src = m68ki_read_8(state, ea_src);
ea_src = EA_A7_PD_8();
- src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16();
+ src = (src | (m68ki_read_8(state, ea_src) << 8)) + OPER_I_16(state);
- m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+ m68ki_write_8(state, EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
/* Note: AX and AY are reversed in Motorola's docs */
uint ea_src = EA_AY_PD_8();
- uint src = m68ki_read_8(ea_src);
+ uint src = m68ki_read_8(state, ea_src);
ea_src = EA_AY_PD_8();
- src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16();
+ src = (src | (m68ki_read_8(state, ea_src) << 8)) + OPER_I_16(state);
- m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+ m68ki_write_8(state, EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
uint ea = M68KMAKE_GET_EA_AY_32;
- m68ki_push_32(ea);
+ m68ki_push_32(state, ea);
}
M68KMAKE_OP(pflusha, 32, ., .)
fprintf(stderr,"68040: unhandled PFLUSHA (ir=%04x)\n", REG_IR);
return;
}
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
M68KMAKE_OP(pflushan, 32, ., .)
fprintf(stderr,"68040: unhandled PFLUSHAN (ir=%04x)\n", REG_IR);
return;
}
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
M68KMAKE_OP(pmmu, 32, ., .)
{
if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU))
{
- m68851_mmu_ops();
+ m68851_mmu_ops(state);
}
else
{
- m68ki_exception_1111();
+ m68ki_exception_1111(state);
}
}
USE_CYCLES(CYC_RESET);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
M68KMAKE_OP(ror, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = ROR_16(src, 1);
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(rol, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(roxr, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
FLAG_C = FLAG_X = res >> 8;
res = MASK_OUT_ABOVE_16(res);
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(roxl, 16, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_16;
- uint src = m68ki_read_16(ea);
+ uint src = m68ki_read_16(state, ea);
uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
FLAG_C = FLAG_X = res >> 8;
res = MASK_OUT_ABOVE_16(res);
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
{
- uint new_pc = m68ki_pull_32();
+ uint new_pc = m68ki_pull_32(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
- m68ki_jump(new_pc);
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state)));
+ m68ki_jump(state, new_pc);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
if(CPU_TYPE_IS_000(CPU_TYPE))
{
- new_sr = m68ki_pull_16();
- new_pc = m68ki_pull_32();
- m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ new_sr = m68ki_pull_16(state);
+ new_pc = m68ki_pull_32(state);
+ m68ki_jump(state, new_pc);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
if(CPU_TYPE_IS_010(CPU_TYPE))
{
- format_word = m68ki_read_16(REG_A[7]+6) >> 12;
+ format_word = m68ki_read_16(state, REG_A[7]+6) >> 12;
if(format_word == 0)
{
- new_sr = m68ki_pull_16();
- new_pc = m68ki_pull_32();
- m68ki_fake_pull_16(); /* format word */
- m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ new_sr = m68ki_pull_16(state);
+ new_pc = m68ki_pull_32(state);
+ m68ki_fake_pull_16(state); /* format word */
+ m68ki_jump(state, new_pc);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
} else if (format_word == 8) {
/* Format 8 stack frame -- 68010 only. 29 word bus/address error */
- new_sr = m68ki_pull_16();
- new_pc = m68ki_pull_32();
- m68ki_fake_pull_16(); /* format word */
- m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ new_sr = m68ki_pull_16(state);
+ new_pc = m68ki_pull_32(state);
+ m68ki_fake_pull_16(state); /* format word */
+ m68ki_jump(state, new_pc);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
- m68ki_fake_pull_16(); /* special status */
- m68ki_fake_pull_32(); /* fault address */
- m68ki_fake_pull_32(); /* reserved and data output buffer */
- m68ki_fake_pull_32(); /* reserved and data input buffer */
- m68ki_fake_pull_32(); /* reserved and instruction input buffer */
- m68ki_fake_pull_32(); /* 8 dwords of CPU specific undocumented data */
- m68ki_fake_pull_32();
- m68ki_fake_pull_32();
- m68ki_fake_pull_32();
- m68ki_fake_pull_32();
- m68ki_fake_pull_32();
- m68ki_fake_pull_32();
- m68ki_fake_pull_32();
+ m68ki_fake_pull_16(state); /* special status */
+ m68ki_fake_pull_32(state); /* fault address */
+ m68ki_fake_pull_32(state); /* reserved and data output buffer */
+ m68ki_fake_pull_32(state); /* reserved and data input buffer */
+ m68ki_fake_pull_32(state); /* reserved and instruction input buffer */
+ m68ki_fake_pull_32(state); /* 8 dwords of CPU specific undocumented data */
+ m68ki_fake_pull_32(state);
+ m68ki_fake_pull_32(state);
+ m68ki_fake_pull_32(state);
+ m68ki_fake_pull_32(state);
+ m68ki_fake_pull_32(state);
+ m68ki_fake_pull_32(state);
+ m68ki_fake_pull_32(state);
return;
}
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
/* Not handling other exception types (9) */
- m68ki_exception_format_error();
+ m68ki_exception_format_error(state);
return;
}
/* Otherwise it's 020 */
rte_loop:
- format_word = m68ki_read_16(REG_A[7]+6) >> 12;
+ format_word = m68ki_read_16(state, REG_A[7]+6) >> 12;
switch(format_word)
{
case 0: /* Normal */
- new_sr = m68ki_pull_16();
- new_pc = m68ki_pull_32();
- m68ki_fake_pull_16(); /* format word */
- m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ new_sr = m68ki_pull_16(state);
+ new_pc = m68ki_pull_32(state);
+ m68ki_fake_pull_16(state); /* format word */
+ m68ki_jump(state, new_pc);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
case 1: /* Throwaway */
- new_sr = m68ki_pull_16();
- m68ki_fake_pull_32(); /* program counter */
- m68ki_fake_pull_16(); /* format word */
- m68ki_set_sr_noint(new_sr);
+ new_sr = m68ki_pull_16(state);
+ m68ki_fake_pull_32(state); /* program counter */
+ m68ki_fake_pull_16(state); /* format word */
+ m68ki_set_sr_noint(state, new_sr);
goto rte_loop;
case 2: /* Trap */
- new_sr = m68ki_pull_16();
- new_pc = m68ki_pull_32();
- m68ki_fake_pull_16(); /* format word */
- m68ki_fake_pull_32(); /* address */
- m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ new_sr = m68ki_pull_16(state);
+ new_pc = m68ki_pull_32(state);
+ m68ki_fake_pull_16(state); /* format word */
+ m68ki_fake_pull_32(state); /* address */
+ m68ki_jump(state, new_pc);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
case 7: /* 68040 access error */
- new_sr = m68ki_pull_16();
- new_pc = m68ki_pull_32();
- m68ki_fake_pull_16(); /* $06: format word */
- m68ki_fake_pull_32(); /* $08: effective address */
- m68ki_fake_pull_16(); /* $0c: special status word */
- m68ki_fake_pull_16(); /* $0e: wb3s */
- m68ki_fake_pull_16(); /* $10: wb2s */
- m68ki_fake_pull_16(); /* $12: wb1s */
- m68ki_fake_pull_32(); /* $14: data fault address */
- m68ki_fake_pull_32(); /* $18: wb3a */
- m68ki_fake_pull_32(); /* $1c: wb3d */
- m68ki_fake_pull_32(); /* $20: wb2a */
- m68ki_fake_pull_32(); /* $24: wb2d */
- m68ki_fake_pull_32(); /* $28: wb1a */
- m68ki_fake_pull_32(); /* $2c: wb1d/pd0 */
- m68ki_fake_pull_32(); /* $30: pd1 */
- m68ki_fake_pull_32(); /* $34: pd2 */
- m68ki_fake_pull_32(); /* $38: pd3 */
- m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ new_sr = m68ki_pull_16(state);
+ new_pc = m68ki_pull_32(state);
+ m68ki_fake_pull_16(state); /* $06: format word */
+ m68ki_fake_pull_32(state); /* $08: effective address */
+ m68ki_fake_pull_16(state); /* $0c: special status word */
+ m68ki_fake_pull_16(state); /* $0e: wb3s */
+ m68ki_fake_pull_16(state); /* $10: wb2s */
+ m68ki_fake_pull_16(state); /* $12: wb1s */
+ m68ki_fake_pull_32(state); /* $14: data fault address */
+ m68ki_fake_pull_32(state); /* $18: wb3a */
+ m68ki_fake_pull_32(state); /* $1c: wb3d */
+ m68ki_fake_pull_32(state); /* $20: wb2a */
+ m68ki_fake_pull_32(state); /* $24: wb2d */
+ m68ki_fake_pull_32(state); /* $28: wb1a */
+ m68ki_fake_pull_32(state); /* $2c: wb1d/pd0 */
+ m68ki_fake_pull_32(state); /* $30: pd1 */
+ m68ki_fake_pull_32(state); /* $34: pd2 */
+ m68ki_fake_pull_32(state); /* $38: pd3 */
+ m68ki_jump(state, new_pc);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
case 0x0a: /* Bus Error at instruction boundary */
- new_sr = m68ki_pull_16();
- new_pc = m68ki_pull_32();
- m68ki_fake_pull_16(); /* $06: format word */
- m68ki_fake_pull_16(); /* $08: internal register */
- m68ki_fake_pull_16(); /* $0a: special status word */
- m68ki_fake_pull_16(); /* $0c: instruction pipe stage c */
- m68ki_fake_pull_16(); /* $0e: instruction pipe stage b */
- m68ki_fake_pull_32(); /* $10: data fault address */
- m68ki_fake_pull_32(); /* $14: internal registers */
- m68ki_fake_pull_32(); /* $18: data output buffer */
- m68ki_fake_pull_32(); /* $1c: internal registers */
-
- m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ new_sr = m68ki_pull_16(state);
+ new_pc = m68ki_pull_32(state);
+ m68ki_fake_pull_16(state); /* $06: format word */
+ m68ki_fake_pull_16(state); /* $08: internal register */
+ m68ki_fake_pull_16(state); /* $0a: special status word */
+ m68ki_fake_pull_16(state); /* $0c: instruction pipe stage c */
+ m68ki_fake_pull_16(state); /* $0e: instruction pipe stage b */
+ m68ki_fake_pull_32(state); /* $10: data fault address */
+ m68ki_fake_pull_32(state); /* $14: internal registers */
+ m68ki_fake_pull_32(state); /* $18: data output buffer */
+ m68ki_fake_pull_32(state); /* $1c: internal registers */
+
+ m68ki_jump(state, new_pc);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
case 0x0b: /* Bus Error - Instruction Execution in Progress */
- new_sr = m68ki_pull_16();
- new_pc = m68ki_pull_32();
- m68ki_fake_pull_16(); /* $06: format word */
- m68ki_fake_pull_16(); /* $08: internal register */
- m68ki_fake_pull_16(); /* $0a: special status word */
- m68ki_fake_pull_16(); /* $0c: instruction pipe stage c */
- m68ki_fake_pull_16(); /* $0e: instruction pipe stage b */
- m68ki_fake_pull_32(); /* $10: data fault address */
- m68ki_fake_pull_32(); /* $14: internal registers */
- m68ki_fake_pull_32(); /* $18: data output buffer */
- m68ki_fake_pull_32(); /* $1c: internal registers */
- m68ki_fake_pull_32(); /* $20: */
- m68ki_fake_pull_32(); /* $24: stage B address */
- m68ki_fake_pull_32(); /* $28: */
- m68ki_fake_pull_32(); /* $2c: data input buffer */
- m68ki_fake_pull_32(); /* $30: */
- m68ki_fake_pull_16(); /* $34: */
- m68ki_fake_pull_16(); /* $36: version #, internal information */
- m68ki_fake_pull_32(); /* $38: */
- m68ki_fake_pull_32(); /* $3c: */
- m68ki_fake_pull_32(); /* $40: */
- m68ki_fake_pull_32(); /* $44: */
- m68ki_fake_pull_32(); /* $48: */
- m68ki_fake_pull_32(); /* $4c: */
- m68ki_fake_pull_32(); /* $50: */
- m68ki_fake_pull_32(); /* $54: */
- m68ki_fake_pull_32(); /* $58: */
-
- m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ new_sr = m68ki_pull_16(state);
+ new_pc = m68ki_pull_32(state);
+ m68ki_fake_pull_16(state); /* $06: format word */
+ m68ki_fake_pull_16(state); /* $08: internal register */
+ m68ki_fake_pull_16(state); /* $0a: special status word */
+ m68ki_fake_pull_16(state); /* $0c: instruction pipe stage c */
+ m68ki_fake_pull_16(state); /* $0e: instruction pipe stage b */
+ m68ki_fake_pull_32(state); /* $10: data fault address */
+ m68ki_fake_pull_32(state); /* $14: internal registers */
+ m68ki_fake_pull_32(state); /* $18: data output buffer */
+ m68ki_fake_pull_32(state); /* $1c: internal registers */
+ m68ki_fake_pull_32(state); /* $20: */
+ m68ki_fake_pull_32(state); /* $24: stage B address */
+ m68ki_fake_pull_32(state); /* $28: */
+ m68ki_fake_pull_32(state); /* $2c: data input buffer */
+ m68ki_fake_pull_32(state); /* $30: */
+ m68ki_fake_pull_16(state); /* $34: */
+ m68ki_fake_pull_16(state); /* $36: version #, internal information */
+ m68ki_fake_pull_32(state); /* $38: */
+ m68ki_fake_pull_32(state); /* $3c: */
+ m68ki_fake_pull_32(state); /* $40: */
+ m68ki_fake_pull_32(state); /* $44: */
+ m68ki_fake_pull_32(state); /* $48: */
+ m68ki_fake_pull_32(state); /* $4c: */
+ m68ki_fake_pull_32(state); /* $50: */
+ m68ki_fake_pull_32(state); /* $54: */
+ m68ki_fake_pull_32(state); /* $58: */
+
+ m68ki_jump(state, new_pc);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
/* Not handling long or short bus fault */
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
- m68ki_exception_format_error();
+ m68ki_exception_format_error(state);
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(rtr, 32, ., .)
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_set_ccr(m68ki_pull_16());
- m68ki_jump(m68ki_pull_32());
+ m68ki_set_ccr(state, m68ki_pull_16(state));
+ m68ki_jump(state, m68ki_pull_32(state));
}
M68KMAKE_OP(rts, 32, ., .)
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_jump(m68ki_pull_32());
+ m68ki_jump(state, m68ki_pull_32(state));
}
M68KMAKE_OP(sbcd, 8, mm, ax7)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_A7_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
uint corf = 0;
FLAG_N = NFLAG_8(res); /* Undefined N behavior */
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(sbcd, 8, mm, ay7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_AX_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
uint corf = 0;
FLAG_N = NFLAG_8(res); /* Undefined N behavior */
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(sbcd, 8, mm, axy7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_A7_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
uint corf = 0;
FLAG_N = NFLAG_8(res); /* Undefined N behavior */
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(sbcd, 8, mm, .)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_AX_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
uint corf = 0;
FLAG_N = NFLAG_8(res); /* Undefined N behavior */
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(st, 8, ., .)
{
- m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
+ m68ki_write_8(state, M68KMAKE_GET_EA_AY_8, 0xff);
}
M68KMAKE_OP(sf, 8, ., .)
{
- m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
+ m68ki_write_8(state, M68KMAKE_GET_EA_AY_8, 0);
}
M68KMAKE_OP(scc, 8, ., .)
{
- m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
+ m68ki_write_8(state, M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
}
{
if(FLAG_S)
{
- uint new_sr = OPER_I_16();
+ uint new_sr = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
CPU_STOPPED |= STOP_LEVEL_STOP;
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR])
m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR];
else
USE_ALL_CYCLES();
return;
}
- m68ki_exception_privilege_violation();
+ m68ki_exception_privilege_violation(state);
}
{
uint ea = M68KMAKE_GET_EA_AY_8;
uint src = MASK_OUT_ABOVE_8(DX);
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
FLAG_X = FLAG_C = CFLAG_8(res);
FLAG_V = VFLAG_SUB_8(src, dst, res);
- m68ki_write_8(ea, FLAG_Z);
+ m68ki_write_8(state, ea, FLAG_Z);
}
{
uint ea = M68KMAKE_GET_EA_AY_16;
uint src = MASK_OUT_ABOVE_16(DX);
- uint dst = m68ki_read_16(ea);
+ uint dst = m68ki_read_16(state, ea);
uint res = dst - src;
FLAG_N = NFLAG_16(res);
FLAG_X = FLAG_C = CFLAG_16(res);
FLAG_V = VFLAG_SUB_16(src, dst, res);
- m68ki_write_16(ea, FLAG_Z);
+ m68ki_write_16(state, ea, FLAG_Z);
}
{
uint ea = M68KMAKE_GET_EA_AY_32;
uint src = DX;
- uint dst = m68ki_read_32(ea);
+ uint dst = m68ki_read_32(state, ea);
uint res = dst - src;
FLAG_N = NFLAG_32(res);
FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
FLAG_V = VFLAG_SUB_32(src, dst, res);
- m68ki_write_32(ea, FLAG_Z);
+ m68ki_write_32(state, ea, FLAG_Z);
}
M68KMAKE_OP(subi, 8, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint dst = MASK_OUT_ABOVE_8(*r_dst);
uint res = dst - src;
M68KMAKE_OP(subi, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
FLAG_X = FLAG_C = CFLAG_8(res);
FLAG_V = VFLAG_SUB_8(src, dst, res);
- m68ki_write_8(ea, FLAG_Z);
+ m68ki_write_8(state, ea, FLAG_Z);
}
M68KMAKE_OP(subi, 16, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint dst = MASK_OUT_ABOVE_16(*r_dst);
uint res = dst - src;
M68KMAKE_OP(subi, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
- uint dst = m68ki_read_16(ea);
+ uint dst = m68ki_read_16(state, ea);
uint res = dst - src;
FLAG_N = NFLAG_16(res);
FLAG_X = FLAG_C = CFLAG_16(res);
FLAG_V = VFLAG_SUB_16(src, dst, res);
- m68ki_write_16(ea, FLAG_Z);
+ m68ki_write_16(state, ea, FLAG_Z);
}
M68KMAKE_OP(subi, 32, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint dst = *r_dst;
uint res = dst - src;
M68KMAKE_OP(subi, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
- uint dst = m68ki_read_32(ea);
+ uint dst = m68ki_read_32(state, ea);
uint res = dst - src;
FLAG_N = NFLAG_32(res);
FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
FLAG_V = VFLAG_SUB_32(src, dst, res);
- m68ki_write_32(ea, FLAG_Z);
+ m68ki_write_32(state, ea, FLAG_Z);
}
{
uint src = (((REG_IR >> 9) - 1) & 7) + 1;
uint ea = M68KMAKE_GET_EA_AY_8;
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
FLAG_X = FLAG_C = CFLAG_8(res);
FLAG_V = VFLAG_SUB_8(src, dst, res);
- m68ki_write_8(ea, FLAG_Z);
+ m68ki_write_8(state, ea, FLAG_Z);
}
{
uint src = (((REG_IR >> 9) - 1) & 7) + 1;
uint ea = M68KMAKE_GET_EA_AY_16;
- uint dst = m68ki_read_16(ea);
+ uint dst = m68ki_read_16(state, ea);
uint res = dst - src;
FLAG_N = NFLAG_16(res);
FLAG_X = FLAG_C = CFLAG_16(res);
FLAG_V = VFLAG_SUB_16(src, dst, res);
- m68ki_write_16(ea, FLAG_Z);
+ m68ki_write_16(state, ea, FLAG_Z);
}
{
uint src = (((REG_IR >> 9) - 1) & 7) + 1;
uint ea = M68KMAKE_GET_EA_AY_32;
- uint dst = m68ki_read_32(ea);
+ uint dst = m68ki_read_32(state, ea);
uint res = dst - src;
FLAG_N = NFLAG_32(res);
FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
FLAG_V = VFLAG_SUB_32(src, dst, res);
- m68ki_write_32(ea, FLAG_Z);
+ m68ki_write_32(state, ea, FLAG_Z);
}
M68KMAKE_OP(subx, 8, mm, ax7)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_A7_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = dst - src - XFLAG_AS_1();
FLAG_N = NFLAG_8(res);
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(subx, 8, mm, ay7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_AX_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = dst - src - XFLAG_AS_1();
FLAG_N = NFLAG_8(res);
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(subx, 8, mm, axy7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_A7_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = dst - src - XFLAG_AS_1();
FLAG_N = NFLAG_8(res);
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(subx, 8, mm, .)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_AX_PD_8();
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint res = dst - src - XFLAG_AS_1();
FLAG_N = NFLAG_8(res);
res = MASK_OUT_ABOVE_8(res);
FLAG_Z |= res;
- m68ki_write_8(ea, res);
+ m68ki_write_8(state, ea, res);
}
M68KMAKE_OP(subx, 16, mm, .)
{
- uint src = OPER_AY_PD_16();
+ uint src = OPER_AY_PD_16(state);
uint ea = EA_AX_PD_16();
- uint dst = m68ki_read_16(ea);
+ uint dst = m68ki_read_16(state, ea);
uint res = dst - src - XFLAG_AS_1();
FLAG_N = NFLAG_16(res);
res = MASK_OUT_ABOVE_16(res);
FLAG_Z |= res;
- m68ki_write_16(ea, res);
+ m68ki_write_16(state, ea, res);
}
M68KMAKE_OP(subx, 32, mm, .)
{
- uint src = OPER_AY_PD_32();
+ uint src = OPER_AY_PD_32(state);
uint ea = EA_AX_PD_32();
- uint dst = m68ki_read_32(ea);
+ uint dst = m68ki_read_32(state, ea);
uint res = dst - src - XFLAG_AS_1();
FLAG_N = NFLAG_32(res);
res = MASK_OUT_ABOVE_32(res);
FLAG_Z |= res;
- m68ki_write_32(ea, res);
+ m68ki_write_32(state, ea, res);
}
M68KMAKE_OP(tas, 8, ., .)
{
uint ea = M68KMAKE_GET_EA_AY_8;
- uint dst = m68ki_read_8(ea);
+ uint dst = m68ki_read_8(state, ea);
uint allow_writeback;
FLAG_Z = dst;
will be needed. */
allow_writeback = m68ki_tas_callback();
- if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
+ if (allow_writeback==1) m68ki_write_8(state, ea, dst | 0x80);
}
M68KMAKE_OP(trap, 0, ., .)
{
/* Trap#n stacks exception frame type 0 */
- m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
+ m68ki_exception_trapN(state, EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
+ m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
// TODO: review this... as mame is not using it...
REG_PC += 2; // JFF else stackframe & return addresses are incorrect
- m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
+ m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
// TODO: review this... as mame is not using it...
REG_PC += 4; // JFF else stackframe & return addresses are incorrect
- m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
+ m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
REG_PC += 2;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
REG_PC += 4;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
if(M68KMAKE_CC)
- m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
+ m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
REG_PC += 2; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
if(M68KMAKE_CC)
{
- m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
+ m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
return;
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
REG_PC += 4; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
if(M68KMAKE_CC)
{
- m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
+ m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
return;
}
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
return;
}
- m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
+ m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCDI_8();
+ uint res = OPER_PCDI_8(state);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCIX_8();
+ uint res = OPER_PCIX_8(state);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_I_8();
+ uint res = OPER_I_8(state);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCDI_16();
+ uint res = OPER_PCDI_16(state);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCIX_16();
+ uint res = OPER_PCIX_16(state);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_I_16();
+ uint res = OPER_I_16(state);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCDI_32();
+ uint res = OPER_PCDI_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCIX_32();
+ uint res = OPER_PCIX_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_I_32();
+ uint res = OPER_I_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
FLAG_C = CFLAG_CLEAR;
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
M68KMAKE_OP(unlk, 32, ., a7)
{
- REG_A[7] = m68ki_read_32(REG_A[7]);
+ REG_A[7] = m68ki_read_32(state, REG_A[7]);
}
uint* r_dst = &AY;
REG_A[7] = *r_dst;
- *r_dst = m68ki_pull_32();
+ *r_dst = m68ki_pull_32(state);
}
uint src = DY;
uint* r_dst = &DX;
- *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state)) & 0xffff);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
/* Note: AX and AY are reversed in Motorola's docs */
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea_dst;
- src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
ea_dst = EA_A7_PD_8();
- m68ki_write_8(ea_dst, src & 0xff);
+ m68ki_write_8(state, ea_dst, src & 0xff);
ea_dst = EA_A7_PD_8();
- m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+ m68ki_write_8(state, ea_dst, (src >> 8) & 0xff);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
/* Note: AX and AY are reversed in Motorola's docs */
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea_dst;
- src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
ea_dst = EA_AX_PD_8();
- m68ki_write_8(ea_dst, src & 0xff);
+ m68ki_write_8(state, ea_dst, src & 0xff);
ea_dst = EA_AX_PD_8();
- m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+ m68ki_write_8(state, ea_dst, (src >> 8) & 0xff);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea_dst;
- src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
ea_dst = EA_A7_PD_8();
- m68ki_write_8(ea_dst, src & 0xff);
+ m68ki_write_8(state, ea_dst, src & 0xff);
ea_dst = EA_A7_PD_8();
- m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+ m68ki_write_8(state, ea_dst, (src >> 8) & 0xff);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
/* Note: AX and AY are reversed in Motorola's docs */
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea_dst;
- src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
ea_dst = EA_AX_PD_8();
- m68ki_write_8(ea_dst, src & 0xff);
+ m68ki_write_8(state, ea_dst, src & 0xff);
ea_dst = EA_AX_PD_8();
- m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+ m68ki_write_8(state, ea_dst, (src >> 8) & 0xff);
return;
}
- m68ki_exception_illegal();
+ m68ki_exception_illegal(state);
}
/* ======================================================================== */
/* ================================ INCLUDES ============================== */
/* ======================================================================== */
-
-extern void m68040_fpu_op0(void);
-extern void m68040_fpu_op1(void);
-extern void m68851_mmu_ops();
+struct m68ki_cpu_core;
+extern void m68040_fpu_op0(struct m68ki_cpu_core *state);
+extern void m68040_fpu_op1(struct m68ki_cpu_core *state);
+extern void m68851_mmu_ops(struct m68ki_cpu_core *state);
extern unsigned char m68ki_cycles[][0x10000];
-extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
extern void m68ki_build_opcode_table(void);
#include "m68kops.h"
return 0;
}
-void m68k_set_reg(m68k_register_t regnum, unsigned int value)
+void m68k_set_reg(void *context, m68k_register_t regnum, unsigned int value)
{
+ m68ki_cpu_core* state = context != NULL ?(m68ki_cpu_core*)context : &m68ki_cpu;
switch(regnum)
{
case M68K_REG_D0: REG_D[0] = MASK_OUT_ABOVE_32(value); return;
case M68K_REG_A5: REG_A[5] = MASK_OUT_ABOVE_32(value); return;
case M68K_REG_A6: REG_A[6] = MASK_OUT_ABOVE_32(value); return;
case M68K_REG_A7: REG_A[7] = MASK_OUT_ABOVE_32(value); return;
- case M68K_REG_PC: m68ki_jump(MASK_OUT_ABOVE_32(value)); return;
- case M68K_REG_SR: m68ki_set_sr_noint_nosp(value); return;
+ case M68K_REG_PC:
+ m68ki_jump(state, MASK_OUT_ABOVE_32(value)); return;
+ case M68K_REG_SR:
+ m68ki_set_sr_noint_nosp(state, value); return;
case M68K_REG_SP: REG_SP = MASK_OUT_ABOVE_32(value); return;
case M68K_REG_USP: if(FLAG_S)
REG_USP = MASK_OUT_ABOVE_32(value);
case M68K_REG_CAAR: REG_CAAR = MASK_OUT_ABOVE_32(value); return;
case M68K_REG_PPC: REG_PPC = MASK_OUT_ABOVE_32(value); return;
case M68K_REG_IR: REG_IR = MASK_OUT_ABOVE_16(value); return;
- case M68K_REG_CPU_TYPE: m68k_set_cpu_type(value); return;
+ case M68K_REG_CPU_TYPE:
+ m68k_set_cpu_type(state, value); return;
default: return;
}
}
}
/* Set the CPU type. */
-void m68k_set_cpu_type(unsigned int cpu_type)
+void m68k_set_cpu_type(struct m68ki_cpu_core *state, unsigned int cpu_type)
{
switch(cpu_type)
{
HAS_FPU = 0;
return;
case M68K_CPU_TYPE_SCC68070:
- m68k_set_cpu_type(M68K_CPU_TYPE_68010);
+ m68k_set_cpu_type(state, M68K_CPU_TYPE_68010);
CPU_ADDRESS_MASK = 0xffffffff;
CPU_TYPE = CPU_TYPE_SCC070;
return;
case M68K_CPU_TYPE_68LC040:
CPU_TYPE = CPU_TYPE_LC040;
CPU_ADDRESS_MASK = 0xffffffff;
- m68ki_cpu.sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
- m68ki_cpu.cyc_instruction = m68ki_cycles[4];
- m68ki_cpu.cyc_exception = m68ki_exception_cycle_table[4];
- m68ki_cpu.cyc_bcc_notake_b = -2;
- m68ki_cpu.cyc_bcc_notake_w = 0;
- m68ki_cpu.cyc_dbcc_f_noexp = 0;
- m68ki_cpu.cyc_dbcc_f_exp = 4;
- m68ki_cpu.cyc_scc_r_true = 0;
- m68ki_cpu.cyc_movem_w = 2;
- m68ki_cpu.cyc_movem_l = 2;
- m68ki_cpu.cyc_shift = 0;
- m68ki_cpu.cyc_reset = 518;
+ state->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
+ state->cyc_instruction = m68ki_cycles[4];
+ state->cyc_exception = m68ki_exception_cycle_table[4];
+ state->cyc_bcc_notake_b = -2;
+ state->cyc_bcc_notake_w = 0;
+ state->cyc_dbcc_f_noexp = 0;
+ state->cyc_dbcc_f_exp = 4;
+ state->cyc_scc_r_true = 0;
+ state->cyc_movem_w = 2;
+ state->cyc_movem_l = 2;
+ state->cyc_shift = 0;
+ state->cyc_reset = 518;
HAS_PMMU = 1;
HAS_FPU = 0;
return;
}
}
-uint m68k_get_address_mask() {
- return m68ki_cpu.address_mask;
+uint m68k_get_address_mask(m68ki_cpu_core *state) {
+ return state->address_mask;
}
/* Execute some instructions until we use up num_cycles clock cycles */
/* ASG: removed per-instruction interrupt checks */
-int m68k_execute(int num_cycles)
+int m68k_execute(m68ki_cpu_core *state, int num_cycles)
{
/* eat up any reset cycles */
if (RESET_CYCLES) {
m68ki_initial_cycles = num_cycles;
/* See if interrupts came in */
- m68ki_check_interrupts();
+ m68ki_check_interrupts(state);
/* Make sure we're not stopped */
if(!CPU_STOPPED)
{
/* Return point if we had an address error */
- m68ki_set_address_error_trap(); /* auto-disable (see m68kcpu.h) */
+ m68ki_set_address_error_trap(state); /* auto-disable (see m68kcpu.h) */
#ifdef M68K_BUSERR_THING
m68ki_check_bus_error_trap();
/* Main loop. Keep going until we run out of clock cycles */
do
{
- /* Set tracing accodring to T1. (T0 is done inside instruction) */
+ /* Set tracing according to T1. (T0 is done inside instruction) */
m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */
/* Set the address space for reads */
#endif
/* Read an instruction and call its handler */
- REG_IR = m68ki_read_imm_16();
- m68ki_instruction_jump_table[REG_IR]();
+ REG_IR = m68ki_read_imm_16(state);
+ m68ki_instruction_jump_table[REG_IR](state);
USE_CYCLES(CYC_INSTRUCTION[REG_IR]);
/* Trace m68k_exception, if necessary */
}
/* Trigger a Bus Error exception */
-void m68k_pulse_bus_error(void)
+void m68k_pulse_bus_error(m68ki_cpu_core *state)
{
- m68ki_exception_bus_error();
+ m68ki_exception_bus_error(state);
}
/* Pulse the RESET line on the CPU */
-void m68k_pulse_reset(void)
+void m68k_pulse_reset(m68ki_cpu_core *state)
{
/* Disable the PMMU/HMMU on reset, if any */
- m68ki_cpu.pmmu_enabled = 0;
-// m68ki_cpu.hmmu_enabled = 0;
+ state->pmmu_enabled = 0;
+// state->hmmu_enabled = 0;
- m68ki_cpu.mmu_tc = 0;
- m68ki_cpu.mmu_tt0 = 0;
- m68ki_cpu.mmu_tt1 = 0;
+ state->mmu_tc = 0;
+ state->mmu_tt0 = 0;
+ state->mmu_tt1 = 0;
/* Clear all stop levels and eat up all remaining cycles */
CPU_STOPPED = 0;
/* Interrupt mask to level 7 */
FLAG_INT_MASK = 0x0700;
CPU_INT_LEVEL = 0;
- m68ki_cpu.virq_state = 0;
+ state->virq_state = 0;
/* Reset VBR */
REG_VBR = 0;
/* Go to supervisor mode */
- m68ki_set_sm_flag(SFLAG_SET | MFLAG_CLEAR);
+ m68ki_set_sm_flag(state, SFLAG_SET | MFLAG_CLEAR);
/* Invalidate the prefetch queue */
#if M68K_EMULATE_PREFETCH
#endif /* M68K_EMULATE_PREFETCH */
/* Read the initial stack pointer and program counter */
- m68ki_jump(0);
- REG_SP = m68ki_read_imm_32();
- REG_PC = m68ki_read_imm_32();
- m68ki_jump(REG_PC);
+ m68ki_jump(state, 0);
+ REG_SP = m68ki_read_imm_32(state);
+ REG_PC = m68ki_read_imm_32(state);
+ m68ki_jump(state, REG_PC);
CPU_RUN_MODE = RUN_MODE_NORMAL;
RESET_CYCLES = CYC_EXCEPTION[EXCEPTION_RESET];
/* flush the MMU's cache */
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
// clear instruction cache
- m68ki_ic_clear();
+ m68ki_ic_clear(state);
}
}
#if M68K_SEPARATE_READS
/* Read data immediately following the PC */
-inline unsigned int m68k_read_immediate_16(unsigned int address) {
+inline unsigned int m68k_read_immediate_16(m68ki_cpu_core *state, unsigned int address) {
#if M68K_EMULATE_PREFETCH == OPT_ON
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
- return be16toh(((unsigned short *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
+ return be16toh(((unsigned short *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
#endif
return m68k_read_memory_16(address);
}
-inline unsigned int m68k_read_immediate_32(unsigned int address) {
+inline unsigned int m68k_read_immediate_32(m68ki_cpu_core *state, unsigned int address) {
#if M68K_EMULATE_PREFETCH == OPT_ON
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
- return be32toh(((unsigned int *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
+ return be32toh(((unsigned int *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
#endif
}
/* Read data relative to the PC */
-inline unsigned int m68k_read_pcrelative_8(unsigned int address) {
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
- return m68ki_cpu.read_data[i][address - m68ki_cpu.read_addr[i]];
+inline unsigned int m68k_read_pcrelative_8(m68ki_cpu_core *state, unsigned int address) {
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
+ return state->read_data[i][address - state->read_addr[i]];
}
}
return m68k_read_memory_8(address);
}
-inline unsigned int m68k_read_pcrelative_16(unsigned int address) {
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
- return be16toh(((unsigned short *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
+inline unsigned int m68k_read_pcrelative_16(m68ki_cpu_core *state, unsigned int address) {
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
+ return be16toh(((unsigned short *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
return m68k_read_memory_16(address);
}
-inline unsigned int m68k_read_pcrelative_32(unsigned int address) {
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
- return be32toh(((unsigned int *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
+inline unsigned int m68k_read_pcrelative_32(m68ki_cpu_core *state, unsigned int address) {
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
+ return be32toh(((unsigned int *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
#endif
-uint m68ki_read_imm6_addr_slowpath(uint32_t pc, address_translation_cache *cache)
+uint m68ki_read_imm16_addr_slowpath(m68ki_cpu_core *state, uint32_t pc, address_translation_cache *cache)
{
uint32_t address = ADDRESS_68K(pc);
uint32_t pc_address_diff = pc - address;
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
- cache->lower = m68ki_cpu.read_addr[i] + pc_address_diff;
- cache->upper = m68ki_cpu.read_upper[i] + pc_address_diff;
- cache->offset = m68ki_cpu.read_data[i] - cache->lower;
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
+ cache->lower = state->read_addr[i] + pc_address_diff;
+ cache->upper = state->read_upper[i] + pc_address_diff;
+ cache->offset = state->read_data[i] - cache->lower;
REG_PC += 2;
- return be16toh(((unsigned short *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
+ return be16toh(((unsigned short *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
- m68ki_cpu.mmu_tmp_fc = FLAG_S | FUNCTION_CODE_USER_PROGRAM;
- m68ki_cpu.mmu_tmp_rw = 1;
- m68ki_cpu.mmu_tmp_sz = M68K_SZ_WORD;
- m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+ state->mmu_tmp_fc = FLAG_S | FUNCTION_CODE_USER_PROGRAM;
+ state->mmu_tmp_rw = 1;
+ state->mmu_tmp_sz = M68K_SZ_WORD;
+ m68ki_check_address_error(state, REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
#if M68K_EMULATE_PREFETCH
{
uint result;
if(REG_PC != CPU_PREF_ADDR)
{
- CPU_PREF_DATA = m68ki_ic_readimm16(REG_PC);
- CPU_PREF_ADDR = m68ki_cpu.mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
+ CPU_PREF_DATA = m68ki_ic_readimm16(state, REG_PC);
+ CPU_PREF_ADDR = state->mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
}
result = MASK_OUT_ABOVE_16(CPU_PREF_DATA);
REG_PC += 2;
- if (!m68ki_cpu.mmu_tmp_buserror_occurred) {
+ if (!state->mmu_tmp_buserror_occurred) {
// prefetch only if no bus error occurred in opcode fetch
- CPU_PREF_DATA = m68ki_ic_readimm16(REG_PC);
- CPU_PREF_ADDR = m68ki_cpu.mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
+ CPU_PREF_DATA = m68ki_ic_readimm16(state, REG_PC);
+ CPU_PREF_ADDR = state->mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
// ignore bus error on prefetch
- m68ki_cpu.mmu_tmp_buserror_occurred = 0;
+ state->mmu_tmp_buserror_occurred = 0;
}
return result;
}
/* ------------------------------ CPU Access ------------------------------ */
/* Access the CPU registers */
-#define CPU_TYPE m68ki_cpu.cpu_type
-
-#define REG_DA m68ki_cpu.dar /* easy access to data and address regs */
-#define REG_DA_SAVE m68ki_cpu.dar_save
-#define REG_D m68ki_cpu.dar
-#define REG_A (m68ki_cpu.dar+8)
-#define REG_PPC m68ki_cpu.ppc
-#define REG_PC m68ki_cpu.pc
-#define REG_SP_BASE m68ki_cpu.sp
-#define REG_USP m68ki_cpu.sp[0]
-#define REG_ISP m68ki_cpu.sp[4]
-#define REG_MSP m68ki_cpu.sp[6]
-#define REG_SP m68ki_cpu.dar[15]
-#define REG_VBR m68ki_cpu.vbr
-#define REG_SFC m68ki_cpu.sfc
-#define REG_DFC m68ki_cpu.dfc
-#define REG_CACR m68ki_cpu.cacr
-#define REG_CAAR m68ki_cpu.caar
-#define REG_IR m68ki_cpu.ir
-
-#define REG_FP m68ki_cpu.fpr
-#define REG_FPCR m68ki_cpu.fpcr
-#define REG_FPSR m68ki_cpu.fpsr
-#define REG_FPIAR m68ki_cpu.fpiar
-
-#define FLAG_T1 m68ki_cpu.t1_flag
-#define FLAG_T0 m68ki_cpu.t0_flag
-#define FLAG_S m68ki_cpu.s_flag
-#define FLAG_M m68ki_cpu.m_flag
-#define FLAG_X m68ki_cpu.x_flag
-#define FLAG_N m68ki_cpu.n_flag
-#define FLAG_Z m68ki_cpu.not_z_flag
-#define FLAG_V m68ki_cpu.v_flag
-#define FLAG_C m68ki_cpu.c_flag
-#define FLAG_INT_MASK m68ki_cpu.int_mask
+#define CPU_TYPE state->cpu_type
+
+#define REG_DA state->dar /* easy access to data and address regs */
+#define REG_DA_SAVE state->dar_save
+#define REG_D state->dar
+#define REG_A (state->dar+8)
+#define REG_PPC state->ppc
+#define REG_PC state->pc
+#define REG_SP_BASE state->sp
+#define REG_USP state->sp[0]
+#define REG_ISP state->sp[4]
+#define REG_MSP state->sp[6]
+#define REG_SP state->dar[15]
+#define REG_VBR state->vbr
+#define REG_SFC state->sfc
+#define REG_DFC state->dfc
+#define REG_CACR state->cacr
+#define REG_CAAR state->caar
+#define REG_IR state->ir
+
+#define REG_FP state->fpr
+#define REG_FPCR state->fpcr
+#define REG_FPSR state->fpsr
+#define REG_FPIAR state->fpiar
+
+#define FLAG_T1 state->t1_flag
+#define FLAG_T0 state->t0_flag
+#define FLAG_S state->s_flag
+#define FLAG_M state->m_flag
+#define FLAG_X state->x_flag
+#define FLAG_N state->n_flag
+#define FLAG_Z state->not_z_flag
+#define FLAG_V state->v_flag
+#define FLAG_C state->c_flag
+#define FLAG_INT_MASK state->int_mask
#define CPU_INT_LEVEL m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */
#define CPU_STOPPED m68ki_cpu.stopped
-#define CPU_PREF_ADDR m68ki_cpu.pref_addr
-#define CPU_PREF_DATA m68ki_cpu.pref_data
-#define CPU_ADDRESS_MASK m68ki_cpu.address_mask
-#define CPU_SR_MASK m68ki_cpu.sr_mask
-#define CPU_INSTR_MODE m68ki_cpu.instr_mode
-#define CPU_RUN_MODE m68ki_cpu.run_mode
-
-#define CYC_INSTRUCTION m68ki_cpu.cyc_instruction
-#define CYC_EXCEPTION m68ki_cpu.cyc_exception
-#define CYC_BCC_NOTAKE_B m68ki_cpu.cyc_bcc_notake_b
-#define CYC_BCC_NOTAKE_W m68ki_cpu.cyc_bcc_notake_w
-#define CYC_DBCC_F_NOEXP m68ki_cpu.cyc_dbcc_f_noexp
-#define CYC_DBCC_F_EXP m68ki_cpu.cyc_dbcc_f_exp
-#define CYC_SCC_R_TRUE m68ki_cpu.cyc_scc_r_true
-#define CYC_MOVEM_W m68ki_cpu.cyc_movem_w
-#define CYC_MOVEM_L m68ki_cpu.cyc_movem_l
-#define CYC_SHIFT m68ki_cpu.cyc_shift
-#define CYC_RESET m68ki_cpu.cyc_reset
-#define HAS_PMMU m68ki_cpu.has_pmmu
-#define HAS_FPU m68ki_cpu.has_fpu
-#define PMMU_ENABLED m68ki_cpu.pmmu_enabled
-#define RESET_CYCLES m68ki_cpu.reset_cycles
+#define CPU_PREF_ADDR state->pref_addr
+#define CPU_PREF_DATA state->pref_data
+#define CPU_ADDRESS_MASK state->address_mask
+#define CPU_SR_MASK state->sr_mask
+#define CPU_INSTR_MODE state->instr_mode
+#define CPU_RUN_MODE state->run_mode
+
+#define CYC_INSTRUCTION state->cyc_instruction
+#define CYC_EXCEPTION state->cyc_exception
+#define CYC_BCC_NOTAKE_B state->cyc_bcc_notake_b
+#define CYC_BCC_NOTAKE_W state->cyc_bcc_notake_w
+#define CYC_DBCC_F_NOEXP state->cyc_dbcc_f_noexp
+#define CYC_DBCC_F_EXP state->cyc_dbcc_f_exp
+#define CYC_SCC_R_TRUE state->cyc_scc_r_true
+#define CYC_MOVEM_W state->cyc_movem_w
+#define CYC_MOVEM_L state->cyc_movem_l
+#define CYC_SHIFT state->cyc_shift
+#define CYC_RESET state->cyc_reset
+#define HAS_PMMU state->has_pmmu
+#define HAS_FPU state->has_fpu
+#define PMMU_ENABLED state->pmmu_enabled
+#define RESET_CYCLES state->reset_cycles
#define CALLBACK_INT_ACK m68ki_cpu.int_ack_callback
#if !M68K_SEPARATE_READS
-#define m68k_read_immediate_16(A) m68ki_read_program_16(A)
-#define m68k_read_immediate_32(A) m68ki_read_program_32(A)
+#define m68k_read_immediate_16(state, A) m68ki_read_program_16(state, A)
+#define m68k_read_immediate_32(state, A) m68ki_read_program_32(state, A)
-#define m68k_read_pcrelative_8(A) m68ki_read_program_8(A)
-#define m68k_read_pcrelative_16(A) m68ki_read_program_16(A)
-#define m68k_read_pcrelative_32(A) m68ki_read_program_32(A)
+#define m68k_read_pcrelative_8(state, A) m68ki_read_program_8(state, A)
+#define m68k_read_pcrelative_16(state, A) m68ki_read_program_16(state, A)
+#define m68k_read_pcrelative_32(state, A) m68ki_read_program_32(state, A)
#endif /* M68K_SEPARATE_READS */
/* sigjmp() on Mac OS X and *BSD in general saves signal contexts and is super-slow, use sigsetjmp() to tell it not to */
#ifdef _BSD_SETJMP_H
extern sigjmp_buf m68ki_aerr_trap;
-#define m68ki_set_address_error_trap(m68k) \
+#define m68ki_set_address_error_trap(state) \
if(sigsetjmp(m68ki_aerr_trap, 0) != 0) \
{ \
- m68ki_exception_address_error(m68k); \
+ m68ki_exception_address_error(state); \
if(CPU_STOPPED) \
{ \
if (m68ki_remaining_cycles > 0) \
} \
}
-#define m68ki_check_address_error(ADDR, WRITE_MODE, FC) \
+#define m68ki_check_address_error(state, ADDR, WRITE_MODE, FC) \
if((ADDR)&1) \
{ \
m68ki_aerr_address = ADDR; \
}
#else
extern jmp_buf m68ki_aerr_trap;
- #define m68ki_set_address_error_trap() \
+ #define m68ki_set_address_error_trap(state) \
if(setjmp(m68ki_aerr_trap) != 0) \
{ \
m68ki_exception_address_error(); \
} \
}
- #define m68ki_check_address_error(ADDR, WRITE_MODE, FC) \
+ #define m68ki_check_address_error(state, ADDR, WRITE_MODE, FC) \
if((ADDR)&1) \
{ \
m68ki_aerr_address = ADDR; \
#endif
#define m68ki_bus_error(ADDR,WRITE_MODE) m68ki_aerr_address=ADDR;m68ki_aerr_write_mode=WRITE_MODE;m68ki_exception_bus_error()
- #define m68ki_check_address_error_010_less(ADDR, WRITE_MODE, FC) \
+ #define m68ki_check_address_error_010_less(state, ADDR, WRITE_MODE, FC) \
if (CPU_TYPE_IS_010_LESS(CPU_TYPE)) \
{ \
- m68ki_check_address_error(ADDR, WRITE_MODE, FC) \
+ m68ki_check_address_error(state, ADDR, WRITE_MODE, FC) \
}
#else
- #define m68ki_set_address_error_trap()
- #define m68ki_check_address_error(ADDR, WRITE_MODE, FC)
- #define m68ki_check_address_error_010_less(ADDR, WRITE_MODE, FC)
+ #define m68ki_set_address_error_trap(state)
+ #define m68ki_check_address_error(state, ADDR, WRITE_MODE, FC)
+ #define m68ki_check_address_error_010_less(state, ADDR, WRITE_MODE, FC)
#endif /* M68K_ADDRESS_ERROR */
/* Logging */
#define EA_AY_PD_8() (--AY) /* predecrement (size = byte) */
#define EA_AY_PD_16() (AY-=2) /* predecrement (size = word) */
#define EA_AY_PD_32() (AY-=4) /* predecrement (size = long) */
-#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */
+#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16(state))) /* displacement */
#define EA_AY_DI_16() EA_AY_DI_8()
#define EA_AY_DI_32() EA_AY_DI_8()
-#define EA_AY_IX_8() m68ki_get_ea_ix(AY) /* indirect + index */
+#define EA_AY_IX_8() m68ki_get_ea_ix(state, AY) /* indirect + index */
#define EA_AY_IX_16() EA_AY_IX_8()
#define EA_AY_IX_32() EA_AY_IX_8()
#define EA_AX_PD_8() (--AX)
#define EA_AX_PD_16() (AX-=2)
#define EA_AX_PD_32() (AX-=4)
-#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16()))
+#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16(state)))
#define EA_AX_DI_16() EA_AX_DI_8()
#define EA_AX_DI_32() EA_AX_DI_8()
-#define EA_AX_IX_8() m68ki_get_ea_ix(AX)
+#define EA_AX_IX_8() m68ki_get_ea_ix(state, AX)
#define EA_AX_IX_16() EA_AX_IX_8()
#define EA_AX_IX_32() EA_AX_IX_8()
#define EA_A7_PI_8() ((REG_A[7]+=2)-2)
#define EA_A7_PD_8() (REG_A[7]-=2)
-#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16()) /* absolute word */
+#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16(state)) /* absolute word */
#define EA_AW_16() EA_AW_8()
#define EA_AW_32() EA_AW_8()
-#define EA_AL_8() m68ki_read_imm_32() /* absolute long */
+#define EA_AL_8() m68ki_read_imm_32(state) /* absolute long */
#define EA_AL_16() EA_AL_8()
#define EA_AL_32() EA_AL_8()
-#define EA_PCDI_8() m68ki_get_ea_pcdi() /* pc indirect + displacement */
+#define EA_PCDI_8() m68ki_get_ea_pcdi(state) /* pc indirect + displacement */
#define EA_PCDI_16() EA_PCDI_8()
#define EA_PCDI_32() EA_PCDI_8()
-#define EA_PCIX_8() m68ki_get_ea_pcix() /* pc indirect + index */
+#define EA_PCIX_8() m68ki_get_ea_pcix(state) /* pc indirect + index */
#define EA_PCIX_16() EA_PCIX_8()
#define EA_PCIX_32() EA_PCIX_8()
-#define OPER_I_8() m68ki_read_imm_8()
-#define OPER_I_16() m68ki_read_imm_16()
-#define OPER_I_32() m68ki_read_imm_32()
+#define OPER_I_8(state) m68ki_read_imm_8(state)
+#define OPER_I_16(state) m68ki_read_imm_16(state)
+#define OPER_I_32(state) m68ki_read_imm_32(state)
/* Get the condition code register */
-#define m68ki_get_ccr() ((COND_XS() >> 4) | \
- (COND_MI() >> 4) | \
- (COND_EQ() << 2) | \
- (COND_VS() >> 6) | \
- (COND_CS() >> 8))
+#define m68ki_get_ccr(state) ((COND_XS() >> 4) | \
+ (COND_MI() >> 4) | \
+ (COND_EQ() << 2) | \
+ (COND_VS() >> 6) | \
+ (COND_CS() >> 8))
/* Get the status register */
-#define m68ki_get_sr() ( FLAG_T1 | \
- FLAG_T0 | \
- (FLAG_S << 11) | \
- (FLAG_M << 11) | \
- FLAG_INT_MASK | \
- m68ki_get_ccr())
+#define m68ki_get_sr(state) ( FLAG_T1 | \
+ FLAG_T0 | \
+ (FLAG_S << 11) | \
+ (FLAG_M << 11) | \
+ FLAG_INT_MASK | \
+ m68ki_get_ccr(state))
/* ----------------------------- Read / Write ----------------------------- */
/* Read from the current address space */
-#define m68ki_read_8(A) m68ki_read_8_fc (A, FLAG_S | m68ki_get_address_space())
-#define m68ki_read_16(A) m68ki_read_16_fc(A, FLAG_S | m68ki_get_address_space())
-#define m68ki_read_32(A) m68ki_read_32_fc(A, FLAG_S | m68ki_get_address_space())
+#define m68ki_read_8(state, A) m68ki_read_8_fc (state, A, FLAG_S | m68ki_get_address_space())
+#define m68ki_read_16(state, A) m68ki_read_16_fc(state, A, FLAG_S | m68ki_get_address_space())
+#define m68ki_read_32(state, A) m68ki_read_32_fc(state, A, FLAG_S | m68ki_get_address_space())
/* Write to the current data space */
-#define m68ki_write_8(A, V) m68ki_write_8_fc (A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
-#define m68ki_write_16(A, V) m68ki_write_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
-#define m68ki_write_32(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#define m68ki_write_8(state, A, V) m68ki_write_8_fc (state, A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#define m68ki_write_16(state, A, V) m68ki_write_16_fc(state, A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#define m68ki_write_32(state, A, V) m68ki_write_32_fc(state, A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
#if M68K_SIMULATE_PD_WRITES
#define m68ki_write_32_pd(A, V) m68ki_write_32_pd_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
#else
-#define m68ki_write_32_pd(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#define m68ki_write_32_pd(state, A, V) m68ki_write_32_fc(state, A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
#endif
/* Map PC-relative reads */
-#define m68ki_read_pcrel_8(A) m68k_read_pcrelative_8(A)
-#define m68ki_read_pcrel_16(A) m68k_read_pcrelative_16(A)
-#define m68ki_read_pcrel_32(A) m68k_read_pcrelative_32(A)
+#define m68ki_read_pcrel_8(state, A) m68k_read_pcrelative_8(state, A)
+#define m68ki_read_pcrel_16(state, A) m68k_read_pcrelative_16(state, A)
+#define m68ki_read_pcrel_32(state, A) m68k_read_pcrelative_32(state, A)
/* Read from the program space */
-#define m68ki_read_program_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
-#define m68ki_read_program_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
-#define m68ki_read_program_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
+#define m68ki_read_program_8(state, A) m68ki_read_8_fc(state, A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
+#define m68ki_read_program_16(state, A) m68ki_read_16_fc(state, A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
+#define m68ki_read_program_32(state, A) m68ki_read_32_fc(state, A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
/* Read from the data space */
-#define m68ki_read_data_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)
-#define m68ki_read_data_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)
-#define m68ki_read_data_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)
+#define m68ki_read_data_8(state, A) m68ki_read_8_fc(state, A, FLAG_S | FUNCTION_CODE_USER_DATA)
+#define m68ki_read_data_16(state, A) m68ki_read_16_fc(state, A, FLAG_S | FUNCTION_CODE_USER_DATA)
+#define m68ki_read_data_32(state, A) m68ki_read_32_fc(state, A, FLAG_S | FUNCTION_CODE_USER_DATA)
-typedef struct
+typedef struct m68ki_cpu_core
{
uint cpu_type; /* CPU Type: 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, or 68040 */
uint dar[16]; /* Data and Address Registers */
extern uint m68ki_aerr_fc;
/* Forward declarations to keep some of the macros happy */
-static inline uint m68ki_read_16_fc (uint address, uint fc);
-static inline uint m68ki_read_32_fc (uint address, uint fc);
-static inline uint m68ki_get_ea_ix(uint An);
-static inline void m68ki_check_interrupts(void); /* ASG: check for interrupts */
+static inline uint m68ki_read_16_fc(m68ki_cpu_core *state, uint address, uint fc);
+static inline uint m68ki_read_32_fc(m68ki_cpu_core *state, uint address, uint fc);
+static inline uint m68ki_get_ea_ix(m68ki_cpu_core *state, uint An);
+static inline void m68ki_check_interrupts(m68ki_cpu_core *state); /* ASG: check for interrupts */
/* quick disassembly (used for logging) */
char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type);
/* ---------------------------- Read Immediate ---------------------------- */
// clear the instruction cache
-inline void m68ki_ic_clear()
+inline void m68ki_ic_clear(m68ki_cpu_core *state)
{
int i;
for (i=0; i< M68K_IC_SIZE; i++) {
- m68ki_cpu.ic_address[i] = ~0;
+ state->ic_address[i] = ~0;
}
}
-extern uint32 pmmu_translate_addr(uint32 addr_in, const uint16 rw);
+extern uint32 pmmu_translate_addr(m68ki_cpu_core *state, uint32 addr_in, uint16 rw);
// read immediate word using the instruction cache
-static inline uint32 m68ki_ic_readimm16(uint32 address)
+static inline uint32 m68ki_ic_readimm16(m68ki_cpu_core *state, uint32 address)
{
- if (m68ki_cpu.cacr & M68K_CACR_EI)
+ if (state->cacr & M68K_CACR_EI)
{
// 68020 series I-cache (MC68020 User's Manual, Section 4 - On-Chip Cache Memory)
if (CPU_TYPE & (CPU_TYPE_EC020 | CPU_TYPE_020))
{
- uint32 tag = (address >> 8) | (m68ki_cpu.s_flag ? 0x1000000 : 0);
+ uint32 tag = (address >> 8) | (state->s_flag ? 0x1000000 : 0);
int idx = (address >> 2) & 0x3f; // 1-of-64 select
// do a cache fill if the line is invalid or the tags don't match
- if ((!m68ki_cpu.ic_valid[idx]) || (m68ki_cpu.ic_address[idx] != tag))
+ if ((!state->ic_valid[idx]) || (state->ic_address[idx] != tag))
{
// if the cache is frozen, don't update it
- if (m68ki_cpu.cacr & M68K_CACR_FI)
+ if (state->cacr & M68K_CACR_FI)
{
- return m68k_read_immediate_16(address);
+ return m68k_read_immediate_16(state, address);
}
- uint32 data = m68ki_read_32(address & ~3);
+ uint32 data = m68ki_read_32(state, address & ~3);
//printf("m68k: doing cache fill at %08x (tag %08x idx %d)\n", address, tag, idx);
// if no buserror occurred, validate the tag
- if (!m68ki_cpu.mmu_tmp_buserror_occurred)
+ if (!state->mmu_tmp_buserror_occurred)
{
- m68ki_cpu.ic_address[idx] = tag;
- m68ki_cpu.ic_data[idx] = data;
- m68ki_cpu.ic_valid[idx] = 1;
+ state->ic_address[idx] = tag;
+ state->ic_data[idx] = data;
+ state->ic_valid[idx] = 1;
}
else
{
- return m68k_read_immediate_16(address);
+ return m68k_read_immediate_16(state, address);
}
}
// a hit or because we just filled it.
if (address & 2)
{
- return m68ki_cpu.ic_data[idx] & 0xffff;
+ return state->ic_data[idx] & 0xffff;
}
else
{
- return m68ki_cpu.ic_data[idx] >> 16;
+ return state->ic_data[idx] >> 16;
}
}
}
- return m68k_read_immediate_16(address);
+ return m68k_read_immediate_16(state, address);
}
/* Handles all immediate reads, does address error check, function code setting,
* and prefetching if they are enabled in m68kconf.h
*/
-uint m68ki_read_imm6_addr_slowpath(uint32_t pc, address_translation_cache *cache);
+uint m68ki_read_imm16_addr_slowpath(m68ki_cpu_core *state, uint32_t pc, address_translation_cache *cache);
-static inline uint m68ki_read_imm_16(void)
+static inline uint m68ki_read_imm_16(m68ki_cpu_core *state)
{
uint32_t pc = REG_PC;
- address_translation_cache *cache = &m68ki_cpu.code_translation_cache;
+ address_translation_cache *cache = &state->code_translation_cache;
if(pc >= cache->lower && pc < cache->upper)
{
REG_PC += 2;
return be16toh(((unsigned short *)(cache->offset + pc))[0]);
}
- return m68ki_read_imm6_addr_slowpath(pc, cache);
+ return m68ki_read_imm16_addr_slowpath(state, pc, cache);
}
-static inline uint m68ki_read_imm_8(void)
+static inline uint m68ki_read_imm_8(m68ki_cpu_core *state)
{
/* map read immediate 8 to read immediate 16 */
- return MASK_OUT_ABOVE_8(m68ki_read_imm_16());
+ return MASK_OUT_ABOVE_8(m68ki_read_imm_16(state));
}
-static inline uint m68ki_read_imm_32(void)
+static inline uint m68ki_read_imm_32(m68ki_cpu_core *state)
{
#if M68K_SEPARATE_READS
#if M68K_EMULATE_PMMU
#endif
#endif
uint32_t address = ADDRESS_68K(REG_PC);
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
REG_PC += 4;
- return be32toh(((unsigned int *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
+ return be32toh(((unsigned int *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
uint temp_val;
m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
- m68ki_cpu.mmu_tmp_fc = FLAG_S | FUNCTION_CODE_USER_PROGRAM;
- m68ki_cpu.mmu_tmp_rw = 1;
- m68ki_cpu.mmu_tmp_sz = M68K_SZ_LONG;
- m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+ state->mmu_tmp_fc = FLAG_S | FUNCTION_CODE_USER_PROGRAM;
+ state->mmu_tmp_rw = 1;
+ state->mmu_tmp_sz = M68K_SZ_LONG;
+ m68ki_check_address_error(state, REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
if(REG_PC != CPU_PREF_ADDR)
{
CPU_PREF_ADDR = REG_PC;
- CPU_PREF_DATA = m68ki_ic_readimm16(ADDRESS_68K(CPU_PREF_ADDR));
+ CPU_PREF_DATA = m68ki_ic_readimm16(state, ADDRESS_68K(CPU_PREF_ADDR));
}
temp_val = MASK_OUT_ABOVE_16(CPU_PREF_DATA);
REG_PC += 2;
CPU_PREF_ADDR = REG_PC;
- CPU_PREF_DATA = m68ki_ic_readimm16(ADDRESS_68K(CPU_PREF_ADDR));
+ CPU_PREF_DATA = m68ki_ic_readimm16(state, ADDRESS_68K(CPU_PREF_ADDR));
temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | MASK_OUT_ABOVE_16(CPU_PREF_DATA));
REG_PC += 2;
- CPU_PREF_DATA = m68ki_ic_readimm16(REG_PC);
- CPU_PREF_ADDR = m68ki_cpu.mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
+ CPU_PREF_DATA = m68ki_ic_readimm16(state, REG_PC);
+ CPU_PREF_ADDR = state->mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
return temp_val;
#else
* code if they are enabled in m68kconf.h.
*/
-static inline uint m68ki_read_8_fc(uint address, uint fc)
+static inline uint m68ki_read_8_fc(m68ki_cpu_core *state, uint address, uint fc)
{
(void)fc;
m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
- m68ki_cpu.mmu_tmp_fc = fc;
- m68ki_cpu.mmu_tmp_rw = 1;
- m68ki_cpu.mmu_tmp_sz = M68K_SZ_BYTE;
+ state->mmu_tmp_fc = fc;
+ state->mmu_tmp_rw = 1;
+ state->mmu_tmp_sz = M68K_SZ_BYTE;
#if M68K_EMULATE_PMMU
if (PMMU_ENABLED)
address = pmmu_translate_addr(address,1);
#endif
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
- return m68ki_cpu.read_data[i][address - m68ki_cpu.read_addr[i]];
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
+ return state->read_data[i][address - state->read_addr[i]];
}
}
return m68k_read_memory_8(ADDRESS_68K(address));
}
-static inline uint m68ki_read_16_fc(uint address, uint fc)
+static inline uint m68ki_read_16_fc(m68ki_cpu_core *state, uint address, uint fc)
{
m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
- m68ki_cpu.mmu_tmp_fc = fc;
- m68ki_cpu.mmu_tmp_rw = 1;
- m68ki_cpu.mmu_tmp_sz = M68K_SZ_WORD;
- m68ki_check_address_error_010_less(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */
+ state->mmu_tmp_fc = fc;
+ state->mmu_tmp_rw = 1;
+ state->mmu_tmp_sz = M68K_SZ_WORD;
+ m68ki_check_address_error_010_less(state, address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */
#if M68K_EMULATE_PMMU
if (PMMU_ENABLED)
- address = pmmu_translate_addr(address,1);
+ address = pmmu_translate_addr(state, address,1);
#endif
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
- return be16toh(((unsigned short *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
+ return be16toh(((unsigned short *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
return m68k_read_memory_16(ADDRESS_68K(address));
}
-static inline uint m68ki_read_32_fc(uint address, uint fc)
+static inline uint m68ki_read_32_fc(m68ki_cpu_core *state, uint address, uint fc)
{
m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
- m68ki_cpu.mmu_tmp_fc = fc;
- m68ki_cpu.mmu_tmp_rw = 1;
- m68ki_cpu.mmu_tmp_sz = M68K_SZ_LONG;
- m68ki_check_address_error_010_less(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */
+ state->mmu_tmp_fc = fc;
+ state->mmu_tmp_rw = 1;
+ state->mmu_tmp_sz = M68K_SZ_LONG;
+ m68ki_check_address_error_010_less(state, address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */
#if M68K_EMULATE_PMMU
if (PMMU_ENABLED)
- address = pmmu_translate_addr(address,1);
+ address = pmmu_translate_addr(state, address,1);
#endif
- for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
- if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
- return be32toh(((unsigned int *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
+ for (int i = 0; i < state->read_ranges; i++) {
+ if(address >= state->read_addr[i] && address < state->read_upper[i]) {
+ return be32toh(((unsigned int *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
return m68k_read_memory_32(ADDRESS_68K(address));
}
-static inline void m68ki_write_8_fc(uint address, uint fc, uint value)
+static inline void m68ki_write_8_fc(m68ki_cpu_core *state, uint address, uint fc, uint value)
{
m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
- m68ki_cpu.mmu_tmp_fc = fc;
- m68ki_cpu.mmu_tmp_rw = 0;
- m68ki_cpu.mmu_tmp_sz = M68K_SZ_BYTE;
+ state->mmu_tmp_fc = fc;
+ state->mmu_tmp_rw = 0;
+ state->mmu_tmp_sz = M68K_SZ_BYTE;
#if M68K_EMULATE_PMMU
if (PMMU_ENABLED)
address = pmmu_translate_addr(address,0);
#endif
- for (int i = 0; i < m68ki_cpu.write_ranges; i++) {
- if(address >= m68ki_cpu.write_addr[i] && address < m68ki_cpu.write_upper[i]) {
- m68ki_cpu.write_data[i][address - m68ki_cpu.write_addr[i]] = (unsigned char)value;
+ for (int i = 0; i < state->write_ranges; i++) {
+ if(address >= state->write_addr[i] && address < state->write_upper[i]) {
+ state->write_data[i][address - state->write_addr[i]] = (unsigned char)value;
return;
}
}
m68k_write_memory_8(ADDRESS_68K(address), value);
}
-static inline void m68ki_write_16_fc(uint address, uint fc, uint value)
+static inline void m68ki_write_16_fc(m68ki_cpu_core *state, uint address, uint fc, uint value)
{
m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
- m68ki_cpu.mmu_tmp_fc = fc;
- m68ki_cpu.mmu_tmp_rw = 0;
- m68ki_cpu.mmu_tmp_sz = M68K_SZ_WORD;
- m68ki_check_address_error_010_less(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */
+ state->mmu_tmp_fc = fc;
+ state->mmu_tmp_rw = 0;
+ state->mmu_tmp_sz = M68K_SZ_WORD;
+ m68ki_check_address_error_010_less(state, address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */
#if M68K_EMULATE_PMMU
if (PMMU_ENABLED)
address = pmmu_translate_addr(address,0);
#endif
- for (int i = 0; i < m68ki_cpu.write_ranges; i++) {
- if(address >= m68ki_cpu.write_addr[i] && address < m68ki_cpu.write_upper[i]) {
- ((short *)(m68ki_cpu.write_data[i] + (address - m68ki_cpu.write_addr[i])))[0] = htobe16(value);
+ for (int i = 0; i < state->write_ranges; i++) {
+ if(address >= state->write_addr[i] && address < state->write_upper[i]) {
+ ((short *)(state->write_data[i] + (address - state->write_addr[i])))[0] = htobe16(value);
return;
}
}
m68k_write_memory_16(ADDRESS_68K(address), value);
}
-static inline void m68ki_write_32_fc(uint address, uint fc, uint value)
+static inline void m68ki_write_32_fc(m68ki_cpu_core *state, uint address, uint fc, uint value)
{
m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
- m68ki_cpu.mmu_tmp_fc = fc;
- m68ki_cpu.mmu_tmp_rw = 0;
- m68ki_cpu.mmu_tmp_sz = M68K_SZ_LONG;
- m68ki_check_address_error_010_less(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */
+ state->mmu_tmp_fc = fc;
+ state->mmu_tmp_rw = 0;
+ state->mmu_tmp_sz = M68K_SZ_LONG;
+ m68ki_check_address_error_010_less(state, address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */
#if M68K_EMULATE_PMMU
if (PMMU_ENABLED)
address = pmmu_translate_addr(address,0);
#endif
- for (int i = 0; i < m68ki_cpu.write_ranges; i++) {
- if(address >= m68ki_cpu.write_addr[i] && address < m68ki_cpu.write_upper[i]) {
- ((int *)(m68ki_cpu.write_data[i] + (address - m68ki_cpu.write_addr[i])))[0] = htobe32(value);
+ for (int i = 0; i < state->write_ranges; i++) {
+ if(address >= state->write_addr[i] && address < state->write_upper[i]) {
+ ((int *)(state->write_data[i] + (address - state->write_addr[i])))[0] = htobe32(value);
return;
}
}
static inline void m68ki_write_32_pd_fc(uint address, uint fc, uint value)
{
m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
- m68ki_cpu.mmu_tmp_fc = fc;
- m68ki_cpu.mmu_tmp_rw = 0;
- m68ki_cpu.mmu_tmp_sz = M68K_SZ_LONG;
- m68ki_check_address_error_010_less(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */
+ state->mmu_tmp_fc = fc;
+ state->mmu_tmp_rw = 0;
+ state->mmu_tmp_sz = M68K_SZ_LONG;
+ m68ki_check_address_error_010_less(state, address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */
#if M68K_EMULATE_PMMU
if (PMMU_ENABLED)
/* The program counter relative addressing modes cause operands to be
* retrieved from program space, not data space.
*/
-static inline uint m68ki_get_ea_pcdi(void)
+static inline uint m68ki_get_ea_pcdi(m68ki_cpu_core *state)
{
uint old_pc = REG_PC;
m68ki_use_program_space(); /* auto-disable */
- return old_pc + MAKE_INT_16(m68ki_read_imm_16());
+ return old_pc + MAKE_INT_16(m68ki_read_imm_16(state));
}
-static inline uint m68ki_get_ea_pcix(void)
+static inline uint m68ki_get_ea_pcix(m68ki_cpu_core *state)
{
m68ki_use_program_space(); /* auto-disable */
- return m68ki_get_ea_ix(REG_PC);
+ return m68ki_get_ea_ix(state, REG_PC);
}
/* Indexed addressing modes are encoded as follows:
* 1 011 mem indir with long outer
* 1 100-111 reserved
*/
-static inline uint m68ki_get_ea_ix(uint An)
+static inline uint m68ki_get_ea_ix(m68ki_cpu_core *state, uint An)
{
/* An = base register */
- uint extension = m68ki_read_imm_16();
+ uint extension = m68ki_read_imm_16(state);
uint Xn = 0; /* Index register */
uint bd = 0; /* Base Displacement */
uint od = 0; /* Outer Displacement */
/* Check if base displacement is present */
if(BIT_5(extension)) /* BD SIZE */
- bd = BIT_4(extension) ? m68ki_read_imm_32() : (uint32)MAKE_INT_16(m68ki_read_imm_16());
+ bd = BIT_4(extension) ? m68ki_read_imm_32(state) : (uint32)MAKE_INT_16(m68ki_read_imm_16(state));
/* If no indirect action, we are done */
if(!(extension&7)) /* No Memory Indirect */
/* Check if outer displacement is present */
if(BIT_1(extension)) /* I/IS: od */
- od = BIT_0(extension) ? m68ki_read_imm_32() : (uint32)MAKE_INT_16(m68ki_read_imm_16());
+ od = BIT_0(extension) ? m68ki_read_imm_32(state) : (uint32)MAKE_INT_16(m68ki_read_imm_16(state));
/* Postindex */
if(BIT_2(extension)) /* I/IS: 0 = preindex, 1 = postindex */
- return m68ki_read_32(An + bd) + Xn + od;
+ return m68ki_read_32(state, An + bd) + Xn + od;
/* Preindex */
- return m68ki_read_32(An + bd + Xn) + od;
+ return m68ki_read_32(state, An + bd + Xn) + od;
}
/* Fetch operands */
-static inline uint OPER_AY_AI_8(void) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AY_PI_8(void) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AY_PD_8(void) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AY_DI_8(void) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AY_IX_8(void) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);}
-
-static inline uint OPER_AX_AI_8(void) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AX_PI_8(void) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AX_PD_8(void) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AX_DI_8(void) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AX_IX_8(void) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);}
-
-static inline uint OPER_A7_PI_8(void) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_A7_PD_8(void) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); }
-
-static inline uint OPER_AW_8(void) {uint ea = EA_AW_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AW_16(void) {uint ea = EA_AW_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AW_32(void) {uint ea = EA_AW_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AL_8(void) {uint ea = EA_AL_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AL_16(void) {uint ea = EA_AL_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AL_32(void) {uint ea = EA_AL_32(); return m68ki_read_32(ea);}
-static inline uint OPER_PCDI_8(void) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); }
-static inline uint OPER_PCDI_16(void) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);}
-static inline uint OPER_PCDI_32(void) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);}
-static inline uint OPER_PCIX_8(void) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); }
-static inline uint OPER_PCIX_16(void) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);}
-static inline uint OPER_PCIX_32(void) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);}
+static inline uint OPER_AY_AI_8(m68ki_cpu_core *state) {uint ea = EA_AY_AI_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AY_AI_16(m68ki_cpu_core *state) {uint ea = EA_AY_AI_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AY_AI_32(m68ki_cpu_core *state) {uint ea = EA_AY_AI_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_AY_PI_8(m68ki_cpu_core *state) {uint ea = EA_AY_PI_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AY_PI_16(m68ki_cpu_core *state) {uint ea = EA_AY_PI_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AY_PI_32(m68ki_cpu_core *state) {uint ea = EA_AY_PI_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_AY_PD_8(m68ki_cpu_core *state) {uint ea = EA_AY_PD_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AY_PD_16(m68ki_cpu_core *state) {uint ea = EA_AY_PD_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AY_PD_32(m68ki_cpu_core *state) {uint ea = EA_AY_PD_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_AY_DI_8(m68ki_cpu_core *state) {uint ea = EA_AY_DI_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AY_DI_16(m68ki_cpu_core *state) {uint ea = EA_AY_DI_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AY_DI_32(m68ki_cpu_core *state) {uint ea = EA_AY_DI_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_AY_IX_8(m68ki_cpu_core *state) {uint ea = EA_AY_IX_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AY_IX_16(m68ki_cpu_core *state) {uint ea = EA_AY_IX_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AY_IX_32(m68ki_cpu_core *state) {uint ea = EA_AY_IX_32(); return m68ki_read_32(state, ea);}
+
+static inline uint OPER_AX_AI_8(m68ki_cpu_core *state) {uint ea = EA_AX_AI_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AX_AI_16(m68ki_cpu_core *state) {uint ea = EA_AX_AI_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AX_AI_32(m68ki_cpu_core *state) {uint ea = EA_AX_AI_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_AX_PI_8(m68ki_cpu_core *state) {uint ea = EA_AX_PI_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AX_PI_16(m68ki_cpu_core *state) {uint ea = EA_AX_PI_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AX_PI_32(m68ki_cpu_core *state) {uint ea = EA_AX_PI_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_AX_PD_8(m68ki_cpu_core *state) {uint ea = EA_AX_PD_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AX_PD_16(m68ki_cpu_core *state) {uint ea = EA_AX_PD_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AX_PD_32(m68ki_cpu_core *state) {uint ea = EA_AX_PD_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_AX_DI_8(m68ki_cpu_core *state) {uint ea = EA_AX_DI_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AX_DI_16(m68ki_cpu_core *state) {uint ea = EA_AX_DI_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AX_DI_32(m68ki_cpu_core *state) {uint ea = EA_AX_DI_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_AX_IX_8(m68ki_cpu_core *state) {uint ea = EA_AX_IX_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AX_IX_16(m68ki_cpu_core *state) {uint ea = EA_AX_IX_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AX_IX_32(m68ki_cpu_core *state) {uint ea = EA_AX_IX_32(); return m68ki_read_32(state, ea);}
+
+static inline uint OPER_A7_PI_8(m68ki_cpu_core *state) {uint ea = EA_A7_PI_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_A7_PD_8(m68ki_cpu_core *state) {uint ea = EA_A7_PD_8(); return m68ki_read_8(state, ea); }
+
+static inline uint OPER_AW_8(m68ki_cpu_core *state) {uint ea = EA_AW_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AW_16(m68ki_cpu_core *state) {uint ea = EA_AW_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AW_32(m68ki_cpu_core *state) {uint ea = EA_AW_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_AL_8(m68ki_cpu_core *state) {uint ea = EA_AL_8(); return m68ki_read_8(state, ea); }
+static inline uint OPER_AL_16(m68ki_cpu_core *state) {uint ea = EA_AL_16(); return m68ki_read_16(state, ea);}
+static inline uint OPER_AL_32(m68ki_cpu_core *state) {uint ea = EA_AL_32(); return m68ki_read_32(state, ea);}
+static inline uint OPER_PCDI_8(m68ki_cpu_core *state) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(state, ea);}
+static inline uint OPER_PCDI_16(m68ki_cpu_core *state) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(state, ea);}
+static inline uint OPER_PCDI_32(m68ki_cpu_core *state) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(state, ea);}
+static inline uint OPER_PCIX_8(m68ki_cpu_core *state) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(state, ea);}
+static inline uint OPER_PCIX_16(m68ki_cpu_core *state) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(state, ea);}
+static inline uint OPER_PCIX_32(m68ki_cpu_core *state) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(state, ea);}
/* ---------------------------- Stack Functions --------------------------- */
/* Push/pull data from the stack */
-static inline void m68ki_push_16(uint value)
+static inline void m68ki_push_16(m68ki_cpu_core *state, uint value)
{
REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);
- m68ki_write_16(REG_SP, value);
+ m68ki_write_16(state, REG_SP, value);
}
-static inline void m68ki_push_32(uint value)
+static inline void m68ki_push_32(m68ki_cpu_core *state, uint value)
{
REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);
- m68ki_write_32(REG_SP, value);
+ m68ki_write_32(state, REG_SP, value);
}
-static inline uint m68ki_pull_16(void)
+static inline uint m68ki_pull_16(m68ki_cpu_core *state)
{
REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);
- return m68ki_read_16(REG_SP-2);
+ return m68ki_read_16(state, REG_SP - 2);
}
-static inline uint m68ki_pull_32(void)
+static inline uint m68ki_pull_32(m68ki_cpu_core *state)
{
REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);
- return m68ki_read_32(REG_SP-4);
+ return m68ki_read_32(state, REG_SP - 4);
}
/* Increment/decrement the stack as if doing a push/pull but
* don't do any memory access.
*/
-static inline void m68ki_fake_push_16(void)
+static inline void m68ki_fake_push_16(m68ki_cpu_core *state)
{
REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);
}
-static inline void m68ki_fake_push_32(void)
+static inline void m68ki_fake_push_32(m68ki_cpu_core *state)
{
REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);
}
-static inline void m68ki_fake_pull_16(void)
+static inline void m68ki_fake_pull_16(m68ki_cpu_core *state)
{
REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);
}
-static inline void m68ki_fake_pull_32(void)
+static inline void m68ki_fake_pull_32(m68ki_cpu_core *state)
{
REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);
}
* These functions will also call the pc_changed callback if it was enabled
* in m68kconf.h.
*/
-static inline void m68ki_jump(uint new_pc)
+static inline void m68ki_jump(m68ki_cpu_core *state, uint new_pc)
{
REG_PC = new_pc;
m68ki_pc_changed(REG_PC);
}
-static inline void m68ki_jump_vector(uint vector)
+static inline void m68ki_jump_vector(m68ki_cpu_core *state, uint vector)
{
REG_PC = (vector<<2) + REG_VBR;
- REG_PC = m68ki_read_data_32(REG_PC);
+ REG_PC = m68ki_read_data_32(state, REG_PC);
m68ki_pc_changed(REG_PC);
}
* So far I've found no problems with not calling pc_changed for 8 or 16
* bit branches.
*/
-static inline void m68ki_branch_8(uint offset)
+static inline void m68ki_branch_8(m68ki_cpu_core *state, uint offset)
{
REG_PC += MAKE_INT_8(offset);
}
-static inline void m68ki_branch_16(uint offset)
+static inline void m68ki_branch_16(m68ki_cpu_core *state, uint offset)
{
REG_PC += MAKE_INT_16(offset);
}
-static inline void m68ki_branch_32(uint offset)
+static inline void m68ki_branch_32(m68ki_cpu_core *state, uint offset)
{
REG_PC += offset;
m68ki_pc_changed(REG_PC);
/* Set the S flag and change the active stack pointer.
* Note that value MUST be 4 or 0.
*/
-static inline void m68ki_set_s_flag(uint value)
+static inline void m68ki_set_s_flag(m68ki_cpu_core *state, uint value)
{
/* Backup the old stack pointer */
REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP;
/* Set the S and M flags and change the active stack pointer.
* Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M).
*/
-static inline void m68ki_set_sm_flag(uint value)
+static inline void m68ki_set_sm_flag(m68ki_cpu_core *state, uint value)
{
/* Backup the old stack pointer */
REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP;
}
/* Set the S and M flags. Don't touch the stack pointer. */
-static inline void m68ki_set_sm_flag_nosp(uint value)
+static inline void m68ki_set_sm_flag_nosp(m68ki_cpu_core *state, uint value)
{
/* Set the S and M flags */
FLAG_S = value & SFLAG_SET;
/* Set the condition code register */
-static inline void m68ki_set_ccr(uint value)
+static inline void m68ki_set_ccr(m68ki_cpu_core *state, uint value)
{
FLAG_X = BIT_4(value) << 4;
FLAG_N = BIT_3(value) << 4;
}
/* Set the status register but don't check for interrupts */
-static inline void m68ki_set_sr_noint(uint value)
+static inline void m68ki_set_sr_noint(m68ki_cpu_core *state, uint value)
{
/* Mask out the "unimplemented" bits */
value &= CPU_SR_MASK;
FLAG_T1 = BIT_F(value);
FLAG_T0 = BIT_E(value);
FLAG_INT_MASK = value & 0x0700;
- m68ki_set_ccr(value);
- m68ki_set_sm_flag((value >> 11) & 6);
+ m68ki_set_ccr(state, value);
+ m68ki_set_sm_flag(state, (value >> 11) & 6);
}
/* Set the status register but don't check for interrupts nor
* change the stack pointer
*/
-static inline void m68ki_set_sr_noint_nosp(uint value)
+static inline void m68ki_set_sr_noint_nosp(m68ki_cpu_core *state, uint value)
{
/* Mask out the "unimplemented" bits */
value &= CPU_SR_MASK;
FLAG_T1 = BIT_F(value);
FLAG_T0 = BIT_E(value);
FLAG_INT_MASK = value & 0x0700;
- m68ki_set_ccr(value);
- m68ki_set_sm_flag_nosp((value >> 11) & 6);
+ m68ki_set_ccr(state, value);
+ m68ki_set_sm_flag_nosp(state, (value >> 11) & 6);
}
/* Set the status register and check for interrupts */
-static inline void m68ki_set_sr(uint value)
+static inline void m68ki_set_sr(m68ki_cpu_core *state, uint value)
{
- m68ki_set_sr_noint(value);
- m68ki_check_interrupts();
+ m68ki_set_sr_noint(state, value);
+ m68ki_check_interrupts(state);
}
/* ------------------------- Exception Processing ------------------------- */
/* Initiate exception processing */
-static inline uint m68ki_init_exception(void)
+static inline uint m68ki_init_exception(m68ki_cpu_core *state)
{
/* Save the old status register */
uint sr = m68ki_get_sr();
FLAG_T1 = FLAG_T0 = 0;
m68ki_clear_trace();
/* Enter supervisor mode */
- m68ki_set_s_flag(SFLAG_SET);
+ m68ki_set_s_flag(state, SFLAG_SET);
return sr;
}
/* 3 word stack frame (68000 only) */
-static inline void m68ki_stack_frame_3word(uint pc, uint sr)
+static inline void m68ki_stack_frame_3word(m68ki_cpu_core *state, uint pc, uint sr)
{
- m68ki_push_32(pc);
- m68ki_push_16(sr);
+ m68ki_push_32(state, pc);
+ m68ki_push_16(state, sr);
}
/* Format 0 stack frame.
* This is the standard stack frame for 68010+.
*/
-static inline void m68ki_stack_frame_0000(uint pc, uint sr, uint vector)
+static inline void m68ki_stack_frame_0000(m68ki_cpu_core *state, uint pc, uint sr, uint vector)
{
/* Stack a 3-word frame if we are 68000 */
if(CPU_TYPE == CPU_TYPE_000)
{
- m68ki_stack_frame_3word(pc, sr);
+ m68ki_stack_frame_3word(state, pc, sr);
return;
}
- m68ki_push_16(vector<<2);
- m68ki_push_32(pc);
- m68ki_push_16(sr);
+ m68ki_push_16(state, vector << 2);
+ m68ki_push_32(state, pc);
+ m68ki_push_16(state, sr);
}
/* Format 1 stack frame (68020).
* For 68020, this is the 4 word throwaway frame.
*/
-static inline void m68ki_stack_frame_0001(uint pc, uint sr, uint vector)
+static inline void m68ki_stack_frame_0001(m68ki_cpu_core *state, uint pc, uint sr, uint vector)
{
- m68ki_push_16(0x1000 | (vector<<2));
- m68ki_push_32(pc);
- m68ki_push_16(sr);
+ m68ki_push_16(state, 0x1000 | (vector << 2));
+ m68ki_push_32(state, pc);
+ m68ki_push_16(state, sr);
}
/* Format 2 stack frame.
* This is used only by 68020 for trap exceptions.
*/
-static inline void m68ki_stack_frame_0010(uint sr, uint vector)
+static inline void m68ki_stack_frame_0010(m68ki_cpu_core *state, uint sr, uint vector)
{
- m68ki_push_32(REG_PPC);
- m68ki_push_16(0x2000 | (vector<<2));
- m68ki_push_32(REG_PC);
- m68ki_push_16(sr);
+ m68ki_push_32(state, REG_PPC);
+ m68ki_push_16(state, 0x2000 | (vector << 2));
+ m68ki_push_32(state, REG_PC);
+ m68ki_push_16(state, sr);
}
/* Bus error stack frame (68000 only).
*/
-static inline void m68ki_stack_frame_buserr(uint sr)
+static inline void m68ki_stack_frame_buserr(m68ki_cpu_core *state, uint sr)
{
- m68ki_push_32(REG_PC);
- m68ki_push_16(sr);
- m68ki_push_16(REG_IR);
- m68ki_push_32(m68ki_aerr_address); /* access address */
+ m68ki_push_32(state, REG_PC);
+ m68ki_push_16(state, sr);
+ m68ki_push_16(state, REG_IR);
+ m68ki_push_32(state, m68ki_aerr_address); /* access address */
/* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC
* R/W 0 = write, 1 = read
* I/N 0 = instruction, 1 = not
* FC 3-bit function code
*/
- m68ki_push_16(m68ki_aerr_write_mode | CPU_INSTR_MODE | m68ki_aerr_fc);
+ m68ki_push_16(state, m68ki_aerr_write_mode | CPU_INSTR_MODE | m68ki_aerr_fc);
}
/* Format 8 stack frame (68010).
* 68010 only. This is the 29 word bus/address error frame.
*/
-static inline void m68ki_stack_frame_1000(uint pc, uint sr, uint vector)
+static inline void m68ki_stack_frame_1000(m68ki_cpu_core *state, uint pc, uint sr, uint vector)
{
/* VERSION
* NUMBER
* INTERNAL INFORMATION, 16 WORDS
*/
- m68ki_fake_push_32();
- m68ki_fake_push_32();
- m68ki_fake_push_32();
- m68ki_fake_push_32();
- m68ki_fake_push_32();
- m68ki_fake_push_32();
- m68ki_fake_push_32();
- m68ki_fake_push_32();
+ m68ki_fake_push_32(state);
+ m68ki_fake_push_32(state);
+ m68ki_fake_push_32(state);
+ m68ki_fake_push_32(state);
+ m68ki_fake_push_32(state);
+ m68ki_fake_push_32(state);
+ m68ki_fake_push_32(state);
+ m68ki_fake_push_32(state);
/* INSTRUCTION INPUT BUFFER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* UNUSED, RESERVED (not written) */
- m68ki_fake_push_16();
+ m68ki_fake_push_16(state);
/* DATA INPUT BUFFER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* UNUSED, RESERVED (not written) */
- m68ki_fake_push_16();
+ m68ki_fake_push_16(state);
/* DATA OUTPUT BUFFER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* UNUSED, RESERVED (not written) */
- m68ki_fake_push_16();
+ m68ki_fake_push_16(state);
/* FAULT ADDRESS */
- m68ki_push_32(0);
+ m68ki_push_32(state, 0);
/* SPECIAL STATUS WORD */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* 1000, VECTOR OFFSET */
- m68ki_push_16(0x8000 | (vector<<2));
+ m68ki_push_16(state, 0x8000 | (vector << 2));
/* PROGRAM COUNTER */
- m68ki_push_32(pc);
+ m68ki_push_32(state, pc);
/* STATUS REGISTER */
- m68ki_push_16(sr);
+ m68ki_push_16(state, sr);
}
/* Format A stack frame (short bus fault).
* if the error happens at an instruction boundary.
* PC stacked is address of next instruction.
*/
-static inline void m68ki_stack_frame_1010(uint sr, uint vector, uint pc, uint fault_address)
+static inline void m68ki_stack_frame_1010(m68ki_cpu_core *state, uint sr, uint vector, uint pc, uint fault_address)
{
- int orig_rw = m68ki_cpu.mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
- int orig_fc = m68ki_cpu.mmu_tmp_buserror_fc;
- int orig_sz = m68ki_cpu.mmu_tmp_buserror_sz;
+ int orig_rw = state->mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
+ int orig_fc = state->mmu_tmp_buserror_fc;
+ int orig_sz = state->mmu_tmp_buserror_sz;
/* INTERNAL REGISTER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* INTERNAL REGISTER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* DATA OUTPUT BUFFER (2 words) */
- m68ki_push_32(0);
+ m68ki_push_32(state, 0);
/* INTERNAL REGISTER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* INTERNAL REGISTER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* DATA CYCLE FAULT ADDRESS (2 words) */
- m68ki_push_32(fault_address);
+ m68ki_push_32(state, fault_address);
/* INSTRUCTION PIPE STAGE B */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* INSTRUCTION PIPE STAGE C */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* SPECIAL STATUS REGISTER */
// set bit for: Rerun Faulted bus Cycle, or run pending prefetch
// set FC
- m68ki_push_16(0x0100 | orig_fc | orig_rw<<6 | orig_sz<<4);
+ m68ki_push_16(state, 0x0100 | orig_fc | orig_rw << 6 | orig_sz << 4);
/* INTERNAL REGISTER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* 1010, VECTOR OFFSET */
- m68ki_push_16(0xa000 | (vector<<2));
+ m68ki_push_16(state, 0xa000 | (vector << 2));
/* PROGRAM COUNTER */
- m68ki_push_32(pc);
+ m68ki_push_32(state, pc);
/* STATUS REGISTER */
- m68ki_push_16(sr);
+ m68ki_push_16(state, sr);
}
/* Format B stack frame (long bus fault).
* if the error happens during instruction execution.
* PC stacked is address of instruction in progress.
*/
-static inline void m68ki_stack_frame_1011(uint sr, uint vector, uint pc, uint fault_address)
+static inline void m68ki_stack_frame_1011(m68ki_cpu_core *state, uint sr, uint vector, uint pc, uint fault_address)
{
- int orig_rw = m68ki_cpu.mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
- int orig_fc = m68ki_cpu.mmu_tmp_buserror_fc;
- int orig_sz = m68ki_cpu.mmu_tmp_buserror_sz;
+ int orig_rw = state->mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
+ int orig_fc = state->mmu_tmp_buserror_fc;
+ int orig_sz = state->mmu_tmp_buserror_sz;
/* INTERNAL REGISTERS (18 words) */
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
/* VERSION# (4 bits), INTERNAL INFORMATION */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* INTERNAL REGISTERS (3 words) */
- m68ki_push_32(0);
- m68ki_push_16(0);
+ m68ki_push_32(state, 0);
+ m68ki_push_16(state, 0);
/* DATA INTPUT BUFFER (2 words) */
- m68ki_push_32(0);
+ m68ki_push_32(state, 0);
/* INTERNAL REGISTERS (2 words) */
- m68ki_push_32(0);
+ m68ki_push_32(state, 0);
/* STAGE B ADDRESS (2 words) */
- m68ki_push_32(0);
+ m68ki_push_32(state, 0);
/* INTERNAL REGISTER (4 words) */
- m68ki_push_32(0);
- m68ki_push_32(0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
/* DATA OUTPUT BUFFER (2 words) */
- m68ki_push_32(0);
+ m68ki_push_32(state, 0);
/* INTERNAL REGISTER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* INTERNAL REGISTER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* DATA CYCLE FAULT ADDRESS (2 words) */
- m68ki_push_32(fault_address);
+ m68ki_push_32(state, fault_address);
/* INSTRUCTION PIPE STAGE B */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* INSTRUCTION PIPE STAGE C */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* SPECIAL STATUS REGISTER */
- m68ki_push_16(0x0100 | orig_fc | (orig_rw<<6) | (orig_sz<<4));
+ m68ki_push_16(state, 0x0100 | orig_fc | (orig_rw << 6) | (orig_sz << 4));
/* INTERNAL REGISTER */
- m68ki_push_16(0);
+ m68ki_push_16(state, 0);
/* 1011, VECTOR OFFSET */
- m68ki_push_16(0xb000 | (vector<<2));
+ m68ki_push_16(state, 0xb000 | (vector << 2));
/* PROGRAM COUNTER */
- m68ki_push_32(pc);
+ m68ki_push_32(state, pc);
/* STATUS REGISTER */
- m68ki_push_16(sr);
+ m68ki_push_16(state, sr);
}
/* Type 7 stack frame (access fault).
* This is used by the 68040 for bus fault and mmu trap
* 30 words
*/
-static inline void m68ki_stack_frame_0111(uint sr, uint vector, uint pc, uint fault_address, uint8 in_mmu)
+static inline void
+m68ki_stack_frame_0111(m68ki_cpu_core *state, uint sr, uint vector, uint pc, uint fault_address, uint8 in_mmu)
{
- int orig_rw = m68ki_cpu.mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
- int orig_fc = m68ki_cpu.mmu_tmp_buserror_fc;
+ int orig_rw = state->mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
+ int orig_fc = state->mmu_tmp_buserror_fc;
/* INTERNAL REGISTERS (18 words) */
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
- m68ki_push_32(0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
+ m68ki_push_32(state, 0);
/* FAULT ADDRESS (2 words) */
- m68ki_push_32(fault_address);
+ m68ki_push_32(state, fault_address);
/* INTERNAL REGISTERS (3 words) */
- m68ki_push_32(0);
- m68ki_push_16(0);
+ m68ki_push_32(state, 0);
+ m68ki_push_16(state, 0);
/* SPECIAL STATUS REGISTER (1 word) */
- m68ki_push_16((in_mmu ? 0x400 : 0) | orig_fc | (orig_rw<<8));
+ m68ki_push_16(state, (in_mmu ? 0x400 : 0) | orig_fc | (orig_rw << 8));
/* EFFECTIVE ADDRESS (2 words) */
- m68ki_push_32(fault_address);
+ m68ki_push_32(state, fault_address);
/* 0111, VECTOR OFFSET (1 word) */
- m68ki_push_16(0x7000 | (vector<<2));
+ m68ki_push_16(state, 0x7000 | (vector << 2));
/* PROGRAM COUNTER (2 words) */
- m68ki_push_32(pc);
+ m68ki_push_32(state, pc);
/* STATUS REGISTER (1 word) */
- m68ki_push_16(sr);
+ m68ki_push_16(state, sr);
}
/* Used for Group 2 exceptions.
* These stack a type 2 frame on the 020.
*/
-static inline void m68ki_exception_trap(uint vector)
+static inline void m68ki_exception_trap(m68ki_cpu_core *state, uint vector)
{
- uint sr = m68ki_init_exception();
+ uint sr = m68ki_init_exception(state);
if(CPU_TYPE_IS_010_LESS(CPU_TYPE))
- m68ki_stack_frame_0000(REG_PC, sr, vector);
+ m68ki_stack_frame_0000(state, REG_PC, sr, vector);
else
- m68ki_stack_frame_0010(sr, vector);
+ m68ki_stack_frame_0010(state, sr, vector);
- m68ki_jump_vector(vector);
+ m68ki_jump_vector(state, vector);
/* Use up some clock cycles and undo the instruction's cycles */
USE_CYCLES(CYC_EXCEPTION[vector] - CYC_INSTRUCTION[REG_IR]);
}
/* Trap#n stacks a 0 frame but behaves like group2 otherwise */
-static inline void m68ki_exception_trapN(uint vector)
+static inline void m68ki_exception_trapN(m68ki_cpu_core *state, uint vector)
{
- uint sr = m68ki_init_exception();
- m68ki_stack_frame_0000(REG_PC, sr, vector);
- m68ki_jump_vector(vector);
+ uint sr = m68ki_init_exception(state);
+ m68ki_stack_frame_0000(state, REG_PC, sr, vector);
+ m68ki_jump_vector(state, vector);
/* Use up some clock cycles and undo the instruction's cycles */
USE_CYCLES(CYC_EXCEPTION[vector] - CYC_INSTRUCTION[REG_IR]);
}
/* Exception for trace mode */
-static inline void m68ki_exception_trace(void)
+static inline void m68ki_exception_trace(m68ki_cpu_core *state)
{
- uint sr = m68ki_init_exception();
+ uint sr = m68ki_init_exception(state);
if(CPU_TYPE_IS_010_LESS(CPU_TYPE))
{
CPU_INSTR_MODE = INSTRUCTION_NO;
}
#endif /* M68K_EMULATE_ADDRESS_ERROR */
- m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_TRACE);
+ m68ki_stack_frame_0000(state, REG_PC, sr, EXCEPTION_TRACE);
}
else
- m68ki_stack_frame_0010(sr, EXCEPTION_TRACE);
+ m68ki_stack_frame_0010(state, sr, EXCEPTION_TRACE);
- m68ki_jump_vector(EXCEPTION_TRACE);
+ m68ki_jump_vector(state, EXCEPTION_TRACE);
/* Trace nullifies a STOP instruction */
CPU_STOPPED &= ~STOP_LEVEL_STOP;
}
/* Exception for privilege violation */
-static inline void m68ki_exception_privilege_violation(void)
+static inline void m68ki_exception_privilege_violation(m68ki_cpu_core *state)
{
- uint sr = m68ki_init_exception();
+ uint sr = m68ki_init_exception(state);
#if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
if(CPU_TYPE_IS_000(CPU_TYPE))
}
#endif /* M68K_EMULATE_ADDRESS_ERROR */
- m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_PRIVILEGE_VIOLATION);
- m68ki_jump_vector(EXCEPTION_PRIVILEGE_VIOLATION);
+ m68ki_stack_frame_0000(state, REG_PPC, sr, EXCEPTION_PRIVILEGE_VIOLATION);
+ m68ki_jump_vector(state, EXCEPTION_PRIVILEGE_VIOLATION);
/* Use up some clock cycles and undo the instruction's cycles */
USE_CYCLES(CYC_EXCEPTION[EXCEPTION_PRIVILEGE_VIOLATION] - CYC_INSTRUCTION[REG_IR]);
#define m68ki_check_bus_error_trap() setjmp(m68ki_bus_error_jmp_buf)
/* Exception for bus error */
-static inline void m68ki_exception_bus_error(void)
+static inline void m68ki_exception_bus_error(m68ki_cpu_core *state)
{
int i;
REG_DA[i] = REG_DA_SAVE[i];
}
- uint sr = m68ki_init_exception();
- m68ki_stack_frame_1000(REG_PPC, sr, EXCEPTION_BUS_ERROR);
+ uint sr = m68ki_init_exception(state);
+ m68ki_stack_frame_1000(state, REG_PPC, sr, EXCEPTION_BUS_ERROR);
- m68ki_jump_vector(EXCEPTION_BUS_ERROR);
+ m68ki_jump_vector(state, EXCEPTION_BUS_ERROR);
longjmp(m68ki_bus_error_jmp_buf, 1);
}
extern int cpu_log_enabled;
/* Exception for A-Line instructions */
-static inline void m68ki_exception_1010(void)
+static inline void m68ki_exception_1010(m68ki_cpu_core *state)
{
uint sr;
#if M68K_LOG_1010_1111 == OPT_ON
m68ki_disassemble_quick(ADDRESS_68K(REG_PPC),CPU_TYPE)));
#endif
- sr = m68ki_init_exception();
- m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1010);
- m68ki_jump_vector(EXCEPTION_1010);
+ sr = m68ki_init_exception(state);
+ m68ki_stack_frame_0000(state, REG_PPC, sr, EXCEPTION_1010);
+ m68ki_jump_vector(state, EXCEPTION_1010);
/* Use up some clock cycles and undo the instruction's cycles */
USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1010] - CYC_INSTRUCTION[REG_IR]);
}
/* Exception for F-Line instructions */
-static inline void m68ki_exception_1111(void)
+static inline void m68ki_exception_1111(m68ki_cpu_core *state)
{
uint sr;
m68ki_disassemble_quick(ADDRESS_68K(REG_PPC),CPU_TYPE)));
#endif
- sr = m68ki_init_exception();
- m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1111);
- m68ki_jump_vector(EXCEPTION_1111);
+ sr = m68ki_init_exception(state);
+ m68ki_stack_frame_0000(state, REG_PPC, sr, EXCEPTION_1111);
+ m68ki_jump_vector(state, EXCEPTION_1111);
/* Use up some clock cycles and undo the instruction's cycles */
USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1111] - CYC_INSTRUCTION[REG_IR]);
#endif
/* Exception for illegal instructions */
-static inline void m68ki_exception_illegal(void)
+static inline void m68ki_exception_illegal(m68ki_cpu_core *state)
{
uint sr;
if (m68ki_illg_callback(REG_IR))
return;
- sr = m68ki_init_exception();
+ sr = m68ki_init_exception(state);
#if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
if(CPU_TYPE_IS_000(CPU_TYPE))
}
#endif /* M68K_EMULATE_ADDRESS_ERROR */
- m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_ILLEGAL_INSTRUCTION);
- m68ki_jump_vector(EXCEPTION_ILLEGAL_INSTRUCTION);
+ m68ki_stack_frame_0000(state, REG_PPC, sr, EXCEPTION_ILLEGAL_INSTRUCTION);
+ m68ki_jump_vector(state, EXCEPTION_ILLEGAL_INSTRUCTION);
/* Use up some clock cycles and undo the instruction's cycles */
USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION] - CYC_INSTRUCTION[REG_IR]);
}
/* Exception for format errror in RTE */
-static inline void m68ki_exception_format_error(void)
+static inline void m68ki_exception_format_error(m68ki_cpu_core *state)
{
- uint sr = m68ki_init_exception();
- m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_FORMAT_ERROR);
- m68ki_jump_vector(EXCEPTION_FORMAT_ERROR);
+ uint sr = m68ki_init_exception(state);
+ m68ki_stack_frame_0000(state, REG_PC, sr, EXCEPTION_FORMAT_ERROR);
+ m68ki_jump_vector(state, EXCEPTION_FORMAT_ERROR);
/* Use up some clock cycles and undo the instruction's cycles */
USE_CYCLES(CYC_EXCEPTION[EXCEPTION_FORMAT_ERROR] - CYC_INSTRUCTION[REG_IR]);
}
/* Exception for address error */
-static inline void m68ki_exception_address_error(void)
+static inline void m68ki_exception_address_error(m68ki_cpu_core *state)
{
- uint32 sr = m68ki_init_exception();
+ uint32 sr = m68ki_init_exception(state);
/* If we were processing a bus error, address error, or reset,
* this is a catastrophic failure.
if (CPU_TYPE_IS_000(CPU_TYPE))
{
/* Note: This is implemented for 68000 only! */
- m68ki_stack_frame_buserr(sr);
+ m68ki_stack_frame_buserr(state, sr);
}
else if (CPU_TYPE_IS_010(CPU_TYPE))
{
/* only the 68010 throws this unique type-1000 frame */
- m68ki_stack_frame_1000(REG_PPC, sr, EXCEPTION_BUS_ERROR);
+ m68ki_stack_frame_1000(state, REG_PPC, sr, EXCEPTION_BUS_ERROR);
}
- else if (m68ki_cpu.mmu_tmp_buserror_address == REG_PPC)
+ else if (state->mmu_tmp_buserror_address == REG_PPC)
{
- m68ki_stack_frame_1010(sr, EXCEPTION_BUS_ERROR, REG_PPC, m68ki_cpu.mmu_tmp_buserror_address);
+ m68ki_stack_frame_1010(state, sr, EXCEPTION_BUS_ERROR, REG_PPC, state->mmu_tmp_buserror_address);
}
else
{
- m68ki_stack_frame_1011(sr, EXCEPTION_BUS_ERROR, REG_PPC, m68ki_cpu.mmu_tmp_buserror_address);
+ m68ki_stack_frame_1011(state, sr, EXCEPTION_BUS_ERROR, REG_PPC, state->mmu_tmp_buserror_address);
}
- m68ki_jump_vector(EXCEPTION_ADDRESS_ERROR);
+ m68ki_jump_vector(state, EXCEPTION_ADDRESS_ERROR);
- m68ki_cpu.run_mode = RUN_MODE_BERR_AERR_RESET;
+ state->run_mode = RUN_MODE_BERR_AERR_RESET;
/* Use up some clock cycles. Note that we don't need to undo the
instruction's cycles here as we've longjmp:ed directly from the
/* Service an interrupt request and start exception processing */
-static inline void m68ki_exception_interrupt(uint int_level)
+static inline void m68ki_exception_interrupt(m68ki_cpu_core *state, uint int_level)
{
uint vector;
uint sr;
}
/* Start exception processing */
- sr = m68ki_init_exception();
+ sr = m68ki_init_exception(state);
/* Set the interrupt mask to the level of the one being serviced */
FLAG_INT_MASK = int_level<<8;
/* Get the new PC */
- new_pc = m68ki_read_data_32((vector<<2) + REG_VBR);
+ new_pc = m68ki_read_data_32(state, (vector << 2) + REG_VBR);
/* If vector is uninitialized, call the uninitialized interrupt vector */
if(new_pc == 0)
- new_pc = m68ki_read_data_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + REG_VBR);
+ new_pc = m68ki_read_data_32(state, (EXCEPTION_UNINITIALIZED_INTERRUPT << 2) + REG_VBR);
/* Generate a stack frame */
- m68ki_stack_frame_0000(REG_PC, sr, vector);
+ m68ki_stack_frame_0000(state, REG_PC, sr, vector);
if(FLAG_M && CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
/* Create throwaway frame */
- m68ki_set_sm_flag(FLAG_S); /* clear M */
+ m68ki_set_sm_flag(state, FLAG_S); /* clear M */
sr |= 0x2000; /* Same as SR in master stack frame except S is forced high */
- m68ki_stack_frame_0001(REG_PC, sr, vector);
+ m68ki_stack_frame_0001(state, REG_PC, sr, vector);
}
- m68ki_jump(new_pc);
+ m68ki_jump(state, new_pc);
/* Defer cycle counting until later */
USE_CYCLES(CYC_EXCEPTION[vector]);
/* ASG: Check for interrupts */
-static inline void m68ki_check_interrupts(void)
+static inline void m68ki_check_interrupts(m68ki_cpu_core *state)
{
- if(m68ki_cpu.nmi_pending)
+ if(state->nmi_pending)
{
- m68ki_cpu.nmi_pending = FALSE;
- m68ki_exception_interrupt(7);
+ state->nmi_pending = FALSE;
+ m68ki_exception_interrupt(state, 7);
}
else if(CPU_INT_LEVEL > FLAG_INT_MASK)
- m68ki_exception_interrupt(CPU_INT_LEVEL>>8);
+ m68ki_exception_interrupt(state, CPU_INT_LEVEL >> 8);
}
#include <stdarg.h>
#include "softfloat/softfloat.h"
+#include "m68kcpu.h"
+
float_status status;
extern void exit(int);
return float64_to_floatx80(*d, &status);
}
-static inline floatx80 load_extended_float80(uint32 ea)
+static inline floatx80 load_extended_float80(m68ki_cpu_core *state, uint32 ea)
{
uint32 d1,d2;
uint16 d3;
floatx80 fp;
- d3 = m68ki_read_16(ea);
- d1 = m68ki_read_32(ea+4);
- d2 = m68ki_read_32(ea+8);
+ d3 = m68ki_read_16(state, ea);
+ d1 = m68ki_read_32(state, ea + 4);
+ d2 = m68ki_read_32(state, ea + 8);
fp.high = d3;
fp.low = ((uint64)d1<<32) | (d2 & 0xffffffff);
return fp;
}
-static inline void store_extended_float80(uint32 ea, floatx80 fpr)
+static inline void store_extended_float80(m68ki_cpu_core *state, uint32 ea, floatx80 fpr)
{
- m68ki_write_16(ea+0, fpr.high);
- m68ki_write_16(ea+2, 0);
- m68ki_write_32(ea+4, (fpr.low>>32)&0xffffffff);
- m68ki_write_32(ea+8, fpr.low&0xffffffff);
+ m68ki_write_16(state, ea + 0, fpr.high);
+ m68ki_write_16(state, ea + 2, 0);
+ m68ki_write_32(state, ea + 4, (fpr.low >> 32) & 0xffffffff);
+ m68ki_write_32(state, ea + 8, fpr.low & 0xffffffff);
}
-static inline floatx80 load_pack_float80(uint32 ea)
+static inline floatx80 load_pack_float80(m68ki_cpu_core *state, uint32 ea)
{
uint32 dw1, dw2, dw3;
floatx80 result;
double tmp;
char str[128], *ch;
- dw1 = m68ki_read_32(ea);
- dw2 = m68ki_read_32(ea+4);
- dw3 = m68ki_read_32(ea+8);
+ dw1 = m68ki_read_32(state, ea);
+ dw2 = m68ki_read_32(state, ea + 4);
+ dw3 = m68ki_read_32(state, ea + 8);
ch = &str[0];
if (dw1 & 0x80000000) // mantissa sign
return result;
}
-static inline void store_pack_float80(uint32 ea, int k, floatx80 fpr)
+static inline void store_pack_float80(m68ki_cpu_core *state, uint32 ea, int k, floatx80 fpr)
{
uint32 dw1, dw2, dw3;
char str[128], *ch;
{
dw2 &= pkmask2[17];
dw3 &= pkmask3[17];
-// m68ki_cpu.fpcr |= (need to set OPERR bit)
+// state->fpcr |= (need to set OPERR bit)
}
}
dw1 |= (j << 16);
}
- m68ki_write_32(ea, dw1);
- m68ki_write_32(ea+4, dw2);
- m68ki_write_32(ea+8, dw3);
+ m68ki_write_32(state, ea, dw1);
+ m68ki_write_32(state, ea + 4, dw2);
+ m68ki_write_32(state, ea + 8, dw3);
}
-static inline void SET_CONDITION_CODES(floatx80 reg)
+static inline void SET_CONDITION_CODES(m68ki_cpu_core *state, floatx80 reg)
{
// u64 *regi;
}
}
-static inline int TEST_CONDITION(int condition)
+static inline int TEST_CONDITION(m68ki_cpu_core *state, int condition)
{
int n = (REG_FPSR & FPCC_N) != 0;
int z = (REG_FPSR & FPCC_Z) != 0;
return r;
}
-static uint8 READ_EA_8(int ea)
+static uint8 READ_EA_8(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
case 2: // (An)
{
uint32 ea = REG_A[reg];
- return m68ki_read_8(ea);
+ return m68ki_read_8(state, ea);
}
case 3: // (An)+
{
uint32 ea = EA_AY_PI_8();
- return m68ki_read_8(ea);
+ return m68ki_read_8(state, ea);
}
case 4: // -(An)
{
uint32 ea = EA_AY_PD_8();
- return m68ki_read_8(ea);
+ return m68ki_read_8(state, ea);
}
case 5: // (d16, An)
{
uint32 ea = EA_AY_DI_8();
- return m68ki_read_8(ea);
+ return m68ki_read_8(state, ea);
}
case 6: // (An) + (Xn) + d8
{
uint32 ea = EA_AY_IX_8();
- return m68ki_read_8(ea);
+ return m68ki_read_8(state, ea);
}
case 7:
{
{
case 0: // (xxx).W
{
- uint32 ea = (uint32)OPER_I_16();
- return m68ki_read_8(ea);
+ uint32 ea = (uint32) OPER_I_16(state);
+ return m68ki_read_8(state, ea);
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
- return m68ki_read_8(ea);
+ return m68ki_read_8(state, ea);
}
case 2: // (d16, PC)
{
uint32 ea = EA_PCDI_8();
- return m68ki_read_8(ea);
+ return m68ki_read_8(state, ea);
}
case 3: // (PC) + (Xn) + d8
{
- uint32 ea = EA_PCIX_8();
- return m68ki_read_8(ea);
+ uint32 ea = EA_PCIX_8();
+ return m68ki_read_8(state, ea);
}
case 4: // #<data>
{
- return OPER_I_8();
+ return OPER_I_8(state);
}
default: fatalerror("M68kFPU: READ_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
return 0;
}
-static uint16 READ_EA_16(int ea)
+static uint16 READ_EA_16(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
case 2: // (An)
{
uint32 ea = REG_A[reg];
- return m68ki_read_16(ea);
+ return m68ki_read_16(state, ea);
}
case 3: // (An)+
{
uint32 ea = EA_AY_PI_16();
- return m68ki_read_16(ea);
+ return m68ki_read_16(state, ea);
}
case 4: // -(An)
{
uint32 ea = EA_AY_PD_16();
- return m68ki_read_16(ea);
+ return m68ki_read_16(state, ea);
}
case 5: // (d16, An)
{
uint32 ea = EA_AY_DI_16();
- return m68ki_read_16(ea);
+ return m68ki_read_16(state, ea);
}
case 6: // (An) + (Xn) + d8
{
uint32 ea = EA_AY_IX_16();
- return m68ki_read_16(ea);
+ return m68ki_read_16(state, ea);
}
case 7:
{
{
case 0: // (xxx).W
{
- uint32 ea = (uint32)OPER_I_16();
- return m68ki_read_16(ea);
+ uint32 ea = (uint32) OPER_I_16(state);
+ return m68ki_read_16(state, ea);
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
- return m68ki_read_16(ea);
+ return m68ki_read_16(state, ea);
}
case 2: // (d16, PC)
{
uint32 ea = EA_PCDI_16();
- return m68ki_read_16(ea);
+ return m68ki_read_16(state, ea);
}
case 3: // (PC) + (Xn) + d8
{
uint32 ea = EA_PCIX_16();
- return m68ki_read_16(ea);
+ return m68ki_read_16(state, ea);
}
case 4: // #<data>
{
- return OPER_I_16();
+ return OPER_I_16(state);
}
default: fatalerror("M68kFPU: READ_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
return 0;
}
-static uint32 READ_EA_32(int ea)
+static uint32 READ_EA_32(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
case 2: // (An)
{
uint32 ea = REG_A[reg];
- return m68ki_read_32(ea);
+ return m68ki_read_32(state, ea);
}
case 3: // (An)+
{
uint32 ea = EA_AY_PI_32();
- return m68ki_read_32(ea);
+ return m68ki_read_32(state, ea);
}
case 4: // -(An)
{
uint32 ea = EA_AY_PD_32();
- return m68ki_read_32(ea);
+ return m68ki_read_32(state, ea);
}
case 5: // (d16, An)
{
uint32 ea = EA_AY_DI_32();
- return m68ki_read_32(ea);
+ return m68ki_read_32(state, ea);
}
case 6: // (An) + (Xn) + d8
{
uint32 ea = EA_AY_IX_32();
- return m68ki_read_32(ea);
+ return m68ki_read_32(state, ea);
}
case 7:
{
{
case 0: // (xxx).W
{
- uint32 ea = (uint32)OPER_I_16();
- return m68ki_read_32(ea);
+ uint32 ea = (uint32) OPER_I_16(state);
+ return m68ki_read_32(state, ea);
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
- return m68ki_read_32(ea);
+ return m68ki_read_32(state, ea);
}
case 2: // (d16, PC)
{
uint32 ea = EA_PCDI_32();
- return m68ki_read_32(ea);
+ return m68ki_read_32(state, ea);
}
case 3: // (PC) + (Xn) + d8
{
uint32 ea = EA_PCIX_32();
- return m68ki_read_32(ea);
+ return m68ki_read_32(state, ea);
}
case 4: // #<data>
{
- return OPER_I_32();
+ return OPER_I_32(state);
}
default: fatalerror("M68kFPU: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
return 0;
}
-static uint64 READ_EA_64(int ea)
+static uint64 READ_EA_64(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
case 2: // (An)
{
uint32 ea = REG_A[reg];
- h1 = m68ki_read_32(ea+0);
- h2 = m68ki_read_32(ea+4);
+ h1 = m68ki_read_32(state, ea + 0);
+ h2 = m68ki_read_32(state, ea + 4);
return (uint64)(h1) << 32 | (uint64)(h2);
}
case 3: // (An)+
{
uint32 ea = REG_A[reg];
REG_A[reg] += 8;
- h1 = m68ki_read_32(ea+0);
- h2 = m68ki_read_32(ea+4);
+ h1 = m68ki_read_32(state, ea + 0);
+ h2 = m68ki_read_32(state, ea + 4);
return (uint64)(h1) << 32 | (uint64)(h2);
}
case 4: // -(An)
{
uint32 ea = REG_A[reg]-8;
REG_A[reg] -= 8;
- h1 = m68ki_read_32(ea+0);
- h2 = m68ki_read_32(ea+4);
+ h1 = m68ki_read_32(state, ea + 0);
+ h2 = m68ki_read_32(state, ea + 4);
return (uint64)(h1) << 32 | (uint64)(h2);
}
case 5: // (d16, An)
{
uint32 ea = EA_AY_DI_32();
- h1 = m68ki_read_32(ea+0);
- h2 = m68ki_read_32(ea+4);
+ h1 = m68ki_read_32(state, ea + 0);
+ h2 = m68ki_read_32(state, ea + 4);
return (uint64)(h1) << 32 | (uint64)(h2);
}
case 6: // (An) + (Xn) + d8
{
uint32 ea = EA_AY_IX_32();
- h1 = m68ki_read_32(ea+0);
- h2 = m68ki_read_32(ea+4);
+ h1 = m68ki_read_32(state, ea + 0);
+ h2 = m68ki_read_32(state, ea + 4);
return (uint64)(h1) << 32 | (uint64)(h2);
}
case 7:
{
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
- return (uint64)(m68ki_read_32(ea)) << 32 | (uint64)(m68ki_read_32(ea+4));
+ return (uint64)(m68ki_read_32(state, ea)) << 32 | (uint64)(m68ki_read_32(state, ea + 4));
}
case 3: // (PC) + (Xn) + d8
{
uint32 ea = EA_PCIX_32();
- h1 = m68ki_read_32(ea+0);
- h2 = m68ki_read_32(ea+4);
+ h1 = m68ki_read_32(state, ea + 0);
+ h2 = m68ki_read_32(state, ea + 4);
return (uint64)(h1) << 32 | (uint64)(h2);
}
case 4: // #<data>
{
- h1 = OPER_I_32();
- h2 = OPER_I_32();
+ h1 = OPER_I_32(state);
+ h2 = OPER_I_32(state);
return (uint64)(h1) << 32 | (uint64)(h2);
}
case 2: // (d16, PC)
{
uint32 ea = EA_PCDI_32();
- h1 = m68ki_read_32(ea+0);
- h2 = m68ki_read_32(ea+4);
+ h1 = m68ki_read_32(state, ea + 0);
+ h2 = m68ki_read_32(state, ea + 4);
return (uint64)(h1) << 32 | (uint64)(h2);
}
default: fatalerror("M68kFPU: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
-static floatx80 READ_EA_FPE(uint32 ea)
+static floatx80 READ_EA_FPE(m68ki_cpu_core *state, uint32 ea)
{
floatx80 fpr;
int mode = (ea >> 3) & 0x7;
case 2: // (An)
{
uint32 ea = REG_A[reg];
- fpr = load_extended_float80(ea);
+ fpr = load_extended_float80(state, ea);
break;
}
{
uint32 ea = REG_A[reg];
REG_A[reg] += 12;
- fpr = load_extended_float80(ea);
+ fpr = load_extended_float80(state, ea);
break;
}
case 4: // -(An)
{
uint32 ea = REG_A[reg]-12;
REG_A[reg] -= 12;
- fpr = load_extended_float80(ea);
+ fpr = load_extended_float80(state, ea);
break;
}
case 5: // (d16, An)
{
// FIXME: will fail for fmovem
uint32 ea = EA_AY_DI_32();
- fpr = load_extended_float80(ea);
+ fpr = load_extended_float80(state, ea);
break;
}
case 6: // (An) + (Xn) + d8
{
// FIXME: will fail for fmovem
uint32 ea = EA_AY_IX_32();
- fpr = load_extended_float80(ea);
+ fpr = load_extended_float80(state, ea);
break;
}
{
case 1: // (xxx)
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
- fpr = load_extended_float80(ea);
+ fpr = load_extended_float80(state, ea);
}
break;
case 2: // (d16, PC)
{
uint32 ea = EA_PCDI_32();
- fpr = load_extended_float80(ea);
+ fpr = load_extended_float80(state, ea);
}
break;
case 3: // (d16,PC,Dx.w)
{
uint32 ea = EA_PCIX_32();
- fpr = load_extended_float80(ea);
+ fpr = load_extended_float80(state, ea);
}
break;
case 4: // immediate (JFF)
{
uint32 ea = REG_PC;
- fpr = load_extended_float80(ea);
+ fpr = load_extended_float80(state, ea);
REG_PC += 12;
}
break;
return fpr;
}
-static floatx80 READ_EA_PACK(int ea)
+static floatx80 READ_EA_PACK(m68ki_cpu_core *state, int ea)
{
floatx80 fpr;
int mode = (ea >> 3) & 0x7;
case 2: // (An)
{
uint32 ea = REG_A[reg];
- fpr = load_pack_float80(ea);
+ fpr = load_pack_float80(state, ea);
break;
}
{
uint32 ea = REG_A[reg];
REG_A[reg] += 12;
- fpr = load_pack_float80(ea);
+ fpr = load_pack_float80(state, ea);
break;
}
case 3: // (d16,PC,Dx.w)
{
uint32 ea = EA_PCIX_32();
- fpr = load_pack_float80(ea);
+ fpr = load_pack_float80(state, ea);
}
break;
return fpr;
}
-static void WRITE_EA_8(int ea, uint8 data)
+static void WRITE_EA_8(m68ki_cpu_core *state, int ea, uint8 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
case 2: // (An)
{
uint32 ea = REG_A[reg];
- m68ki_write_8(ea, data);
+ m68ki_write_8(state, ea, data);
break;
}
case 3: // (An)+
{
uint32 ea = EA_AY_PI_8();
- m68ki_write_8(ea, data);
+ m68ki_write_8(state, ea, data);
break;
}
case 4: // -(An)
{
uint32 ea = EA_AY_PD_8();
- m68ki_write_8(ea, data);
+ m68ki_write_8(state, ea, data);
break;
}
case 5: // (d16, An)
{
uint32 ea = EA_AY_DI_8();
- m68ki_write_8(ea, data);
+ m68ki_write_8(state, ea, data);
break;
}
case 6: // (An) + (Xn) + d8
{
uint32 ea = EA_AY_IX_8();
- m68ki_write_8(ea, data);
+ m68ki_write_8(state, ea, data);
break;
}
case 7:
{
case 1: // (xxx).B
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
- m68ki_write_8(ea, data);
+ m68ki_write_8(state, ea, data);
break;
}
case 2: // (d16, PC)
{
uint32 ea = EA_PCDI_16();
- m68ki_write_8(ea, data);
+ m68ki_write_8(state, ea, data);
break;
}
default: fatalerror("M68kFPU: WRITE_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
}
-static void WRITE_EA_16(int ea, uint16 data)
+static void WRITE_EA_16(m68ki_cpu_core *state, int ea, uint16 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
case 2: // (An)
{
uint32 ea = REG_A[reg];
- m68ki_write_16(ea, data);
+ m68ki_write_16(state, ea, data);
break;
}
case 3: // (An)+
{
uint32 ea = EA_AY_PI_16();
- m68ki_write_16(ea, data);
+ m68ki_write_16(state, ea, data);
break;
}
case 4: // -(An)
{
uint32 ea = EA_AY_PD_16();
- m68ki_write_16(ea, data);
+ m68ki_write_16(state, ea, data);
break;
}
case 5: // (d16, An)
{
uint32 ea = EA_AY_DI_16();
- m68ki_write_16(ea, data);
+ m68ki_write_16(state, ea, data);
break;
}
case 6: // (An) + (Xn) + d8
{
uint32 ea = EA_AY_IX_16();
- m68ki_write_16(ea, data);
+ m68ki_write_16(state, ea, data);
break;
}
case 7:
{
case 1: // (xxx).W
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
- m68ki_write_16(ea, data);
+ m68ki_write_16(state, ea, data);
break;
}
case 2: // (d16, PC)
{
uint32 ea = EA_PCDI_16();
- m68ki_write_16(ea, data);
+ m68ki_write_16(state, ea, data);
break;
}
default: fatalerror("M68kFPU: WRITE_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
}
-static void WRITE_EA_32(int ea, uint32 data)
+static void WRITE_EA_32(m68ki_cpu_core *state, int ea, uint32 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
case 2: // (An)
{
uint32 ea = REG_A[reg];
- m68ki_write_32(ea, data);
+ m68ki_write_32(state, ea, data);
break;
}
case 3: // (An)+
{
uint32 ea = EA_AY_PI_32();
- m68ki_write_32(ea, data);
+ m68ki_write_32(state, ea, data);
break;
}
case 4: // -(An)
{
uint32 ea = EA_AY_PD_32();
- m68ki_write_32(ea, data);
+ m68ki_write_32(state, ea, data);
break;
}
case 5: // (d16, An)
{
uint32 ea = EA_AY_DI_32();
- m68ki_write_32(ea, data);
+ m68ki_write_32(state, ea, data);
break;
}
case 6: // (An) + (Xn) + d8
{
uint32 ea = EA_AY_IX_32();
- m68ki_write_32(ea, data);
+ m68ki_write_32(state, ea, data);
break;
}
case 7:
{
case 0: // (xxx).W
{
- uint32 ea = OPER_I_16();
- m68ki_write_32(ea, data);
+ uint32 ea = OPER_I_16(state);
+ m68ki_write_32(state, ea, data);
break;
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
- m68ki_write_32(ea, data);
+ m68ki_write_32(state, ea, data);
break;
}
case 2: // (d16, PC)
{
uint32 ea = EA_PCDI_32();
- m68ki_write_32(ea, data);
+ m68ki_write_32(state, ea, data);
break;
}
default: fatalerror("M68kFPU: WRITE_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
}
-static void WRITE_EA_64(int ea, uint64 data)
+static void WRITE_EA_64(m68ki_cpu_core *state, int ea, uint64 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
case 2: // (An)
{
uint32 ea = REG_A[reg];
- m68ki_write_32(ea, (uint32)(data >> 32));
- m68ki_write_32(ea+4, (uint32)(data));
+ m68ki_write_32(state, ea, (uint32) (data >> 32));
+ m68ki_write_32(state, ea + 4, (uint32) (data));
break;
}
case 3: // (An)+
{
uint32 ea = REG_A[reg];
REG_A[reg] += 8;
- m68ki_write_32(ea+0, (uint32)(data >> 32));
- m68ki_write_32(ea+4, (uint32)(data));
+ m68ki_write_32(state, ea + 0, (uint32) (data >> 32));
+ m68ki_write_32(state, ea + 4, (uint32) (data));
break;
}
case 4: // -(An)
uint32 ea;
REG_A[reg] -= 8;
ea = REG_A[reg];
- m68ki_write_32(ea+0, (uint32)(data >> 32));
- m68ki_write_32(ea+4, (uint32)(data));
+ m68ki_write_32(state, ea + 0, (uint32) (data >> 32));
+ m68ki_write_32(state, ea + 4, (uint32) (data));
break;
}
case 5: // (d16, An)
{
uint32 ea = EA_AY_DI_32();
- m68ki_write_32(ea+0, (uint32)(data >> 32));
- m68ki_write_32(ea+4, (uint32)(data));
+ m68ki_write_32(state, ea + 0, (uint32) (data >> 32));
+ m68ki_write_32(state, ea + 4, (uint32) (data));
break;
}
case 6: // (An) + (Xn) + d8
{
uint32 ea = EA_AY_IX_32();
- m68ki_write_32(ea+0, (uint32)(data >> 32));
- m68ki_write_32(ea+4, (uint32)(data));
+ m68ki_write_32(state, ea + 0, (uint32) (data >> 32));
+ m68ki_write_32(state, ea + 4, (uint32) (data));
break;
}
case 7:
{
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
- m68ki_write_32(ea+0, (uint32)(data >> 32));
- m68ki_write_32(ea+4, (uint32)(data));
+ m68ki_write_32(state, ea + 0, (uint32) (data >> 32));
+ m68ki_write_32(state, ea + 4, (uint32) (data));
break;
}
case 2: // (d16, PC)
{
uint32 ea = EA_PCDI_32();
- m68ki_write_32(ea+0, (uint32)(data >> 32));
- m68ki_write_32(ea+4, (uint32)(data));
+ m68ki_write_32(state, ea + 0, (uint32) (data >> 32));
+ m68ki_write_32(state, ea + 4, (uint32) (data));
break;
}
default: fatalerror("M68kFPU: WRITE_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
}
-static void WRITE_EA_FPE(uint32 ea, floatx80 fpr)
+static void WRITE_EA_FPE(m68ki_cpu_core *state, uint32 ea, floatx80 fpr)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
uint32 ea;
ea = REG_A[reg];
- store_extended_float80(ea, fpr);
+ store_extended_float80(state, ea, fpr);
break;
}
{
uint32 ea;
ea = REG_A[reg];
- store_extended_float80(ea, fpr);
+ store_extended_float80(state, ea, fpr);
REG_A[reg] += 12;
break;
}
uint32 ea;
REG_A[reg] -= 12;
ea = REG_A[reg];
- store_extended_float80(ea, fpr);
+ store_extended_float80(state, ea, fpr);
break;
}
case 5: // (d16, An)
{
uint32 ea = EA_AY_DI_32();
- store_extended_float80(ea, fpr);
+ store_extended_float80(state, ea, fpr);
break;
}
}
}
-static void WRITE_EA_PACK(int ea, int k, floatx80 fpr)
+static void WRITE_EA_PACK(m68ki_cpu_core *state, int ea, int k, floatx80 fpr)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
uint32 ea;
ea = REG_A[reg];
- store_pack_float80(ea, k, fpr);
+ store_pack_float80(state, ea, k, fpr);
break;
}
{
uint32 ea;
ea = REG_A[reg];
- store_pack_float80(ea, k, fpr);
+ store_pack_float80(state, ea, k, fpr);
REG_A[reg] += 12;
break;
}
uint32 ea;
REG_A[reg] -= 12;
ea = REG_A[reg];
- store_pack_float80(ea, k, fpr);
+ store_pack_float80(state, ea, k, fpr);
break;
}
}
-static void fpgen_rm_reg(uint16 w2)
+static void fpgen_rm_reg(m68ki_cpu_core *state, uint16 w2)
{
int ea = REG_IR & 0x3f;
int rm = (w2 >> 14) & 0x1;
{
case 0: // Long-Word Integer
{
- sint32 d = READ_EA_32(ea);
+ sint32 d = READ_EA_32(state, ea);
source = int32_to_floatx80(d);
break;
}
case 1: // Single-precision Real
{
- uint32 d = READ_EA_32(ea);
+ uint32 d = READ_EA_32(state, ea);
source = float32_to_floatx80(d, &status);
break;
}
case 2: // Extended-precision Real
{
- source = READ_EA_FPE(ea);
+ source = READ_EA_FPE(state, ea);
break;
}
case 3: // Packed-decimal Real
{
- source = READ_EA_PACK(ea);
+ source = READ_EA_PACK(state, ea);
break;
}
case 4: // Word Integer
{
- sint16 d = READ_EA_16(ea);
+ sint16 d = READ_EA_16(state, ea);
source = int32_to_floatx80((sint32)d);
break;
}
case 5: // Double-precision Real
{
- uint64 d = READ_EA_64(ea);
+ uint64 d = READ_EA_64(state, ea);
source = float64_to_floatx80(d, &status);
break;
}
case 6: // Byte Integer
{
- sint8 d = READ_EA_8(ea);
+ sint8 d = READ_EA_8(state, ea);
source = int32_to_floatx80((sint32)d);
break;
}
// handle it right here, the usual opmode bits aren't valid in the FMOVECR case
REG_FP[dst] = source;
//FIXME mame doesn't use SET_CONDITION_CODES here
- SET_CONDITION_CODES(REG_FP[dst]); // JFF when destination is a register, we HAVE to update FPCR
+ SET_CONDITION_CODES(state, REG_FP[dst]); // JFF when destination is a register, we HAVE to update FPCR
USE_CYCLES(4);
return;
}
case 0x00: // FMOVE
{
REG_FP[dst] = source;
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(4);
break;
}
temp = floatx80_to_int32(source, &status);
REG_FP[dst] = int32_to_floatx80(temp);
//FIXME mame doesn't use SET_CONDITION_CODES here
- SET_CONDITION_CODES(REG_FP[dst]); // JFF needs update condition codes
+ SET_CONDITION_CODES(state, REG_FP[dst]); // JFF needs update condition codes
USE_CYCLES(4);
break;
}
case 0x02: // FSINH
{
REG_FP[dst] = floatx80_sinh(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
temp = floatx80_to_int32_round_to_zero(source, &status);
REG_FP[dst] = int32_to_floatx80(temp);
//FIXME mame doesn't use SET_CONDITION_CODES here
- SET_CONDITION_CODES(REG_FP[dst]); // JFF needs update condition codes
+ SET_CONDITION_CODES(state, REG_FP[dst]); // JFF needs update condition codes
break;
}
case 0x45: // FDSQRT
case 0x05: // FSQRT
{
REG_FP[dst] = floatx80_sqrt(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(109);
break;
}
case 0x07: // FLOGNP1
{
REG_FP[dst] = floatx80_lognp1 (source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(594); // for MC68881
break;
}
case 0x08: // FETOXM1
{
REG_FP[dst] = floatx80_etoxm1(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(6);
break;
}
case 0x09: // FTANH
{
REG_FP[dst] = floatx80_tanh(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x0b: // FATAN
{
REG_FP[dst] = floatx80_atan(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x0c: // FASIN
{
REG_FP[dst] = floatx80_asin(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x0d: // FATANH
{
REG_FP[dst] = floatx80_atanh(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x0e: // FSIN
{
REG_FP[dst] = floatx80_sin(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x0f: // FTAN
{
REG_FP[dst] = floatx80_tan(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x10: // FETOX
{
REG_FP[dst] = floatx80_etox(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x11: // FTWOTOX
{
REG_FP[dst] = floatx80_twotox(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x13: // FTENTOX
{
REG_FP[dst] = floatx80_tentox(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x14: // FLOGN
{
REG_FP[dst] = floatx80_logn(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(548); // for MC68881
break;
}
case 0x15: // FLOG10
{
REG_FP[dst] = floatx80_log10(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(604); // for MC68881
break;
}
case 0x17: // FLOG2
{
REG_FP[dst] = floatx80_log2(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(604); // for MC68881
break;
}
{
REG_FP[dst] = source;
REG_FP[dst].high &= 0x7fff;
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(3);
break;
}
case 0x19: // FCOSH
{
REG_FP[dst] = floatx80_cosh(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(64);
break;
}
{
REG_FP[dst] = source;
REG_FP[dst].high ^= 0x8000;
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(3);
break;
}
case 0x1c: // FACOS
{
REG_FP[dst] = floatx80_acos(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(604); // for MC68881
break;
break;
case 0x1d: // FCOS
{
REG_FP[dst] = floatx80_cos(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
}
case 0x1e: // FGETEXP
{
REG_FP[dst] = floatx80_getexp(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(6);
break;
}
case 0x1f: // FGETMAN
{
REG_FP[dst] = floatx80_getman(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(6);
break;
}
{
REG_FP[dst] = floatx80_div(REG_FP[dst], source, &status);
//FIXME mame doesn't use SET_CONDITION_CODES here
- SET_CONDITION_CODES(REG_FP[dst]); // JFF
+ SET_CONDITION_CODES(state, REG_FP[dst]); // JFF
USE_CYCLES(43);
break;
}
uint64_t q;
flag s;
REG_FP[dst] = floatx80_rem(REG_FP[dst], source, &q, &s, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
status.float_rounding_mode = mode;
USE_CYCLES(43); // guess
break;
case 0x22: // FADD
{
REG_FP[dst] = floatx80_add(REG_FP[dst], source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(9);
break;
}
case 0x23: // FMUL
{
REG_FP[dst] = floatx80_mul(REG_FP[dst], source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(11);
break;
}
uint64_t q;
flag s;
REG_FP[dst] = floatx80_rem(REG_FP[dst], source, &q, &s, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
status.float_rounding_mode = mode;
USE_CYCLES(43); // guess
break;
case 0x26: // FSCALE
{
REG_FP[dst] = floatx80_scale(REG_FP[dst], source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(46); // (better?) guess
break;
}
case 0x27: // FSGLMUL
{
REG_FP[dst] = floatx80_sglmul(REG_FP[dst], source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(11); // ? (value is from FMUL)
break;
}
case 0x2f: // FSUB
{
REG_FP[dst] = floatx80_sub(REG_FP[dst], source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(9);
break;
}
{
REG_FP[dst] = floatx80_cos(source, &status);
REG_FP[w2&7] = floatx80_sin(source, &status);
- SET_CONDITION_CODES(REG_FP[dst]);
+ SET_CONDITION_CODES(state, REG_FP[dst]);
USE_CYCLES(75);
break;
{
floatx80 res;
res = floatx80_sub(REG_FP[dst], source, &status);
- SET_CONDITION_CODES(res);
+ SET_CONDITION_CODES(state, res);
USE_CYCLES(7);
break;
}
{
floatx80 res;
res = source;
- SET_CONDITION_CODES(res);
+ SET_CONDITION_CODES(state, res);
USE_CYCLES(7);
break;
}
}
}
-static void fmove_reg_mem(uint16 w2)
+static void fmove_reg_mem(m68ki_cpu_core *state, uint16 w2)
{
int ea = REG_IR & 0x3f;
int src = (w2 >> 7) & 0x7;
case 0: // Long-Word Integer
{
sint32 d = (sint32)floatx80_to_int32(REG_FP[src], &status);
- WRITE_EA_32(ea, d);
+ WRITE_EA_32(state, ea, d);
break;
}
case 1: // Single-precision Real
{
uint32 d = floatx80_to_float32(REG_FP[src], &status);
- WRITE_EA_32(ea, d);
+ WRITE_EA_32(state, ea, d);
break;
}
case 2: // Extended-precision Real
{
- WRITE_EA_FPE(ea, REG_FP[src]);
+ WRITE_EA_FPE(state, ea, REG_FP[src]);
break;
}
case 3: // Packed-decimal Real with Static K-factor
{
// sign-extend k
k = (k & 0x40) ? (k | 0xffffff80) : (k & 0x7f);
- WRITE_EA_PACK(ea, k, REG_FP[src]);
+ WRITE_EA_PACK(state, ea, k, REG_FP[src]);
break;
}
case 4: // Word Integer
{
REG_FPSR |= FPES_OE | FPAE_IOP;
}
- WRITE_EA_16(ea, (sint16)value);
+ WRITE_EA_16(state, ea, (sint16) value);
break;
}
case 5: // Double-precision Real
d = floatx80_to_float64(REG_FP[src], &status);
- WRITE_EA_64(ea, d);
+ WRITE_EA_64(state, ea, d);
break;
}
case 6: // Byte Integer
{
REG_FPSR |= FPES_OE | FPAE_IOP;
}
- WRITE_EA_8(ea, (sint8)value);
+ WRITE_EA_8(state, ea, (sint8) value);
break;
}
case 7: // Packed-decimal Real with Dynamic K-factor
{
- WRITE_EA_PACK(ea, REG_D[k>>4], REG_FP[src]);
+ WRITE_EA_PACK(state, ea, REG_D[k >> 4], REG_FP[src]);
break;
}
}
USE_CYCLES(12);
}
-static void fmove_fpcr(uint16 w2)
+static void fmove_fpcr(m68ki_cpu_core *state, uint16 w2)
{
int ea = REG_IR & 0x3f;
int dir = (w2 >> 13) & 0x1;
if (dir) // From system control reg to <ea>
{
- if (regsel & 4) { m68ki_write_32(address, REG_FPCR); address += 4; }
- if (regsel & 2) { m68ki_write_32(address, REG_FPSR); address += 4; }
- if (regsel & 1) { m68ki_write_32(address, REG_FPIAR); address += 4; }
+ if (regsel & 4) { m68ki_write_32(state, address, REG_FPCR); address += 4; }
+ if (regsel & 2) { m68ki_write_32(state, address, REG_FPSR); address += 4; }
+ if (regsel & 1) { m68ki_write_32(state, address, REG_FPIAR); address += 4; }
}
else // From <ea> to system control reg
{
- if (regsel & 4) { REG_FPCR = m68ki_read_32(address); address += 4; }
- if (regsel & 2) { REG_FPSR = m68ki_read_32(address); address += 4; }
- if (regsel & 1) { REG_FPIAR = m68ki_read_32(address); address += 4; }
+ if (regsel & 4) { REG_FPCR = m68ki_read_32(state, address); address += 4; }
+ if (regsel & 2) { REG_FPSR = m68ki_read_32(state, address); address += 4; }
+ if (regsel & 1) { REG_FPIAR = m68ki_read_32(state, address); address += 4; }
}
}
else
{
if (dir) // From system control reg to <ea>
{
- if (regsel & 4) WRITE_EA_32(ea, REG_FPCR);
- if (regsel & 2) WRITE_EA_32(ea, REG_FPSR);
- if (regsel & 1) WRITE_EA_32(ea, REG_FPIAR);
+ if (regsel & 4) WRITE_EA_32(state, ea, REG_FPCR);
+ if (regsel & 2) WRITE_EA_32(state, ea, REG_FPSR);
+ if (regsel & 1) WRITE_EA_32(state, ea, REG_FPIAR);
}
else // From <ea> to system control reg
{
- if (regsel & 4) REG_FPCR = READ_EA_32(ea);
- if (regsel & 2) REG_FPSR = READ_EA_32(ea);
- if (regsel & 1) REG_FPIAR = READ_EA_32(ea);
+ if (regsel & 4) REG_FPCR = READ_EA_32(state, ea);
+ if (regsel & 2) REG_FPSR = READ_EA_32(state, ea);
+ if (regsel & 1) REG_FPIAR = READ_EA_32(state, ea);
}
}
USE_CYCLES(10);
}
-static void fmovem(uint16 w2)
+static void fmovem(m68ki_cpu_core *state, uint16 w2)
{
int i;
int ea = REG_IR & 0x3f;
{
case 5: // (d16, An)
case 6: // (An) + (Xn) + d8
- store_extended_float80(mem_addr, REG_FP[i]);
+ store_extended_float80(state, mem_addr, REG_FP[i]);
mem_addr += 12;
break;
default:
- WRITE_EA_FPE(ea, REG_FP[i]);
+ WRITE_EA_FPE(state, ea, REG_FP[i]);
break;
}
{
case 5: // (d16, An)
case 6: // (An) + (Xn) + d8
- store_extended_float80(mem_addr, REG_FP[7-i]);
+ store_extended_float80(state, mem_addr, REG_FP[7 - i]);
mem_addr += 12;
break;
default:
- WRITE_EA_FPE(ea, REG_FP[7-i]);
+ WRITE_EA_FPE(state, ea, REG_FP[7 - i]);
break;
}
{
case 5: // (d16, An)
case 6: // (An) + (Xn) + d8
- REG_FP[7-i] = load_extended_float80(mem_addr);
+ REG_FP[7-i] = load_extended_float80(state, mem_addr);
mem_addr += 12;
break;
default:
- REG_FP[7-i] = READ_EA_FPE(ea);
+ REG_FP[7-i] = READ_EA_FPE(state, ea);
break;
}
USE_CYCLES(2);
}
}
-static void fscc()
+static void fscc(m68ki_cpu_core *state)
{
int ea = REG_IR & 0x3f;
- int condition = (sint16)(OPER_I_16());
+ int condition = (sint16)(OPER_I_16(state));
- WRITE_EA_8(ea, TEST_CONDITION(condition) ? 0xff : 0);
+ WRITE_EA_8(state, ea, TEST_CONDITION(state, condition) ? 0xff : 0);
USE_CYCLES(7); // ???
}
-static void fbcc16(void)
+static void fbcc16(m68ki_cpu_core *state)
{
sint32 offset;
int condition = REG_IR & 0x3f;
- offset = (sint16)(OPER_I_16());
+ offset = (sint16)(OPER_I_16(state));
// TODO: condition and jump!!!
- if (TEST_CONDITION(condition))
+ if (TEST_CONDITION(state, condition))
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_16(offset-2);
+ m68ki_branch_16(state, offset - 2);
}
USE_CYCLES(7);
}
-static void fbcc32(void)
+static void fbcc32(m68ki_cpu_core *state)
{
sint32 offset;
int condition = REG_IR & 0x3f;
- offset = OPER_I_32();
+ offset = OPER_I_32(state);
// TODO: condition and jump!!!
- if (TEST_CONDITION(condition))
+ if (TEST_CONDITION(state, condition))
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_branch_32(offset-4);
+ m68ki_branch_32(state, offset - 4);
}
USE_CYCLES(7);
}
-void m68040_fpu_op0()
+void m68040_fpu_op0(m68ki_cpu_core *state)
{
- m68ki_cpu.fpu_just_reset = 0;
+ state->fpu_just_reset = 0;
switch ((REG_IR >> 6) & 0x3)
{
case 0:
{
- uint16 w2 = OPER_I_16();
+ uint16 w2 = OPER_I_16(state);
switch ((w2 >> 13) & 0x7)
{
case 0x0: // FPU ALU FP, FP
case 0x2: // FPU ALU ea, FP
{
- fpgen_rm_reg(w2);
+ fpgen_rm_reg(state, w2);
break;
}
case 0x3: // FMOVE FP, ea
{
- fmove_reg_mem(w2);
+ fmove_reg_mem(state, w2);
break;
}
case 0x4: // FMOVEM ea, FPCR
case 0x5: // FMOVEM FPCR, ea
{
- fmove_fpcr(w2);
+ fmove_fpcr(state, w2);
break;
}
case 0x6: // FMOVEM ea, list
case 0x7: // FMOVEM list, ea
{
- fmovem(w2);
+ fmovem(state, w2);
break;
}
printf("M68kFPU: unimplemented FDBcc main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4);
break;
default: // FScc (?)
- fscc();
+ fscc(state);
return;
}
fatalerror("M68kFPU: unimplemented main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4);
}
case 2: // FBcc disp16
{
- fbcc16();
+ fbcc16(state);
break;
}
case 3: // FBcc disp32
{
- fbcc32();
+ fbcc32(state);
break;
}
}
}
-static int perform_fsave(uint32 addr, int inc)
+static int perform_fsave(m68ki_cpu_core *state, uint32 addr, int inc)
{
- if(m68ki_cpu.cpu_type & CPU_TYPE_040)
+ if(state->cpu_type & CPU_TYPE_040)
{
if(inc)
{
- m68ki_write_32(addr, 0x41000000);
+ m68ki_write_32(state, addr, 0x41000000);
return 4 -4;
}
else
{
- m68ki_write_32(addr, 0x41000000);
+ m68ki_write_32(state, addr, 0x41000000);
return -4 +4;
}
}
if (inc)
{
// 68881 IDLE, version 0x1f
- m68ki_write_32(addr, 0x1f180000);
- m68ki_write_32(addr+4, 0);
- m68ki_write_32(addr+8, 0);
- m68ki_write_32(addr+12, 0);
- m68ki_write_32(addr+16, 0);
- m68ki_write_32(addr+20, 0);
- m68ki_write_32(addr+24, 0x70000000);
+ m68ki_write_32(state, addr, 0x1f180000);
+ m68ki_write_32(state, addr + 4, 0);
+ m68ki_write_32(state, addr + 8, 0);
+ m68ki_write_32(state, addr + 12, 0);
+ m68ki_write_32(state, addr + 16, 0);
+ m68ki_write_32(state, addr + 20, 0);
+ m68ki_write_32(state, addr + 24, 0x70000000);
return 7*4 -4;
}
else
{
- m68ki_write_32(addr+4-4, 0x70000000);
- m68ki_write_32(addr+4-8, 0);
- m68ki_write_32(addr+4-12, 0);
- m68ki_write_32(addr+4-16, 0);
- m68ki_write_32(addr+4-20, 0);
- m68ki_write_32(addr+4-24, 0);
- m68ki_write_32(addr+4-28, 0x1f180000);
+ m68ki_write_32(state, addr + 4 - 4, 0x70000000);
+ m68ki_write_32(state, addr + 4 - 8, 0);
+ m68ki_write_32(state, addr + 4 - 12, 0);
+ m68ki_write_32(state, addr + 4 - 16, 0);
+ m68ki_write_32(state, addr + 4 - 20, 0);
+ m68ki_write_32(state, addr + 4 - 24, 0);
+ m68ki_write_32(state, addr + 4 - 28, 0x1f180000);
return -7*4 +4;
}
}
// FRESTORE on a NULL frame reboots the FPU - all registers to NaN, the 3 status regs to 0
-static void do_frestore_null(void)
+static void do_frestore_null(m68ki_cpu_core *state)
{
int i;
// Mac IIci at 408458e6 wants an FSAVE of a just-restored NULL frame to also be NULL
// The PRM says it's possible to generate a NULL frame, but not how/when/why. (need the 68881/68882 manual!)
- m68ki_cpu.fpu_just_reset = 1;
+ state->fpu_just_reset = 1;
}
-void m68040_do_fsave(uint32 addr, int reg, int inc)
+void m68040_do_fsave(m68ki_cpu_core *state, uint32 addr, int reg, int inc)
{
- if (m68ki_cpu.fpu_just_reset)
+ if (state->fpu_just_reset)
{
- m68ki_write_32(addr, 0);
+ m68ki_write_32(state, addr, 0);
}
else
{
// we normally generate an IDLE frame
- int delta = perform_fsave(addr, inc);
+ int delta = perform_fsave(state, addr, inc);
if(reg != -1)
REG_A[reg] += delta;
}
}
-void m68040_do_frestore(uint32 addr, int reg)
+void m68040_do_frestore(m68ki_cpu_core *state, uint32 addr, int reg)
{
- uint32 temp = m68ki_read_32(addr);
+ uint32 temp = m68ki_read_32(state, addr);
// check for nullptr frame
if (temp & 0xff000000)
{
// we don't handle non-nullptr frames
- m68ki_cpu.fpu_just_reset = 0;
+ state->fpu_just_reset = 0;
if (reg != -1)
{
- uint8 m40 = !!(m68ki_cpu.cpu_type & CPU_TYPE_040);
+ uint8 m40 = !!(state->cpu_type & CPU_TYPE_040);
// how about an IDLE frame?
if (!m40 && ((temp & 0x00ff0000) == 0x00180000))
{
}
else
{
- do_frestore_null();
+ do_frestore_null(state);
}
}
-void m68040_fpu_op1()
+void m68040_fpu_op1(m68ki_cpu_core *state)
{
int ea = REG_IR & 0x3f;
int mode = (ea >> 3) & 0x7;
{
case 2: // (An)
addr = REG_A[reg];
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
case 3: // (An)+
addr = EA_AY_PI_32();
printf("FSAVE mode %d, reg A%d=0x%08x\n",mode,reg,REG_A[reg]);
- m68040_do_fsave(addr, -1, 1); // FIXME: -1 was reg
+ m68040_do_fsave(state, addr, -1, 1); // FIXME: -1 was reg
break;
case 4: // -(An)
addr = EA_AY_PD_32();
- m68040_do_fsave(addr, reg, 0); // FIXME: -1 was reg
+ m68040_do_fsave(state, addr, reg, 0); // FIXME: -1 was reg
break;
case 5: // (D16, An)
addr = EA_AY_DI_16();
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
case 6: // (An) + (Xn) + d8
addr = EA_AY_IX_16();
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
case 7: //
case 1: // (abs32)
{
addr = EA_AL_32();
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
}
case 2: // (d16, PC)
{
addr = EA_PCDI_16();
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
}
default:
{
case 2: // (An)
addr = REG_A[reg];
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
case 3: // (An)+
addr = EA_AY_PI_32();
- m68040_do_frestore(addr, reg);
+ m68040_do_frestore(state, addr, reg);
break;
case 5: // (D16, An)
addr = EA_AY_DI_16();
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
case 6: // (An) + (Xn) + d8
addr = EA_AY_IX_16();
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
case 7: //
case 1: // (abs32)
{
addr = EA_AL_32();
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
}
case 2: // (d16, PC)
{
addr = EA_PCDI_16();
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
}
default:
}
}
-void m68881_ftrap()
+void m68881_ftrap(m68ki_cpu_core *state)
{
- uint16 w2 = OPER_I_16();
+ uint16 w2 = OPER_I_16(state);
// now check the condition
- if (TEST_CONDITION(w2 & 0x3f))
+ if (TEST_CONDITION(state, w2 & 0x3f))
{
// trap here
- m68ki_exception_trap(EXCEPTION_TRAPV);
+ m68ki_exception_trap(state, EXCEPTION_TRAPV);
}
else // fall through, requires eating the operand
{
switch (REG_IR & 0x7)
{
case 2: // word operand
- OPER_I_16();
+ OPER_I_16(state);
break;
case 3: // long word operand
- OPER_I_32();
+ OPER_I_32(state);
break;
case 4: // no operand
/* Write the name of an opcode handler function */
void write_function_name(FILE* filep, char* base_name)
{
- fprintf(filep, "static void %s(void)\n", base_name);
+ fprintf(filep, "static void %s(m68ki_cpu_core *state)\n", base_name);
}
void add_opcode_output_table_entry(opcode_struct* op, char* name)
add_replace_string(replace, ID_OPHANDLER_EA_AY_16, str);
sprintf(str, "EA_%s_32()", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_EA_AY_32, str);
- sprintf(str, "OPER_%s_8()", g_ea_info_table[ea_mode].ea_add);
+ sprintf(str, "OPER_%s_8(state)", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_OPER_AY_8, str);
- sprintf(str, "OPER_%s_16()", g_ea_info_table[ea_mode].ea_add);
+ sprintf(str, "OPER_%s_16(state)", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_OPER_AY_16, str);
- sprintf(str, "OPER_%s_32()", g_ea_info_table[ea_mode].ea_add);
+ sprintf(str, "OPER_%s_32(state)", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_OPER_AY_32, str);
}
// MMU status register bit definitions
+
+
+struct m68ki_cpu_core;
#if 0
#define MMULOG(A) printf A
#else
#define m_side_effects_disabled 0
/* decodes the effective address */
-uint32 DECODE_EA_32(int ea)
+uint32 DECODE_EA_32(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 0: // (xxx).W
{
- uint32 ea = OPER_I_16();
+ uint32 ea = OPER_I_16(state);
return ea;
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
return ea;
}
return 0;
}
-void pmmu_set_buserror(uint32 addr_in)
+void pmmu_set_buserror(m68ki_cpu_core *state, uint32 addr_in)
{
- if (!m_side_effects_disabled && ++m68ki_cpu.mmu_tmp_buserror_occurred == 1)
+ if (!m_side_effects_disabled && ++state->mmu_tmp_buserror_occurred == 1)
{
- m68ki_cpu.mmu_tmp_buserror_address = addr_in;
- m68ki_cpu.mmu_tmp_buserror_rw = m68ki_cpu.mmu_tmp_rw;
- m68ki_cpu.mmu_tmp_buserror_fc = m68ki_cpu.mmu_tmp_fc;
- m68ki_cpu.mmu_tmp_buserror_sz = m68ki_cpu.mmu_tmp_sz;
+ state->mmu_tmp_buserror_address = addr_in;
+ state->mmu_tmp_buserror_rw = state->mmu_tmp_rw;
+ state->mmu_tmp_buserror_fc = state->mmu_tmp_fc;
+ state->mmu_tmp_buserror_sz = state->mmu_tmp_sz;
}
}
// pmmu_atc_add: adds this address to the ATC
-void pmmu_atc_add(uint32 logical, uint32 physical, int fc, int rw)
+void pmmu_atc_add(m68ki_cpu_core *state, uint32 logical, uint32 physical, int fc, int rw)
{
// get page size (i.e. # of bits to ignore); is 10 for Apollo
- int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
+ int ps = (state->mmu_tc >> 20) & 0xf;
uint32 atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | ((logical >> ps) << (ps - 8));
uint32 atc_data = (physical >> ps) << (ps - 8);
- if (m68ki_cpu.mmu_tmp_sr & (M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY))
+ if (state->mmu_tmp_sr & (M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY))
{
atc_data |= M68K_MMU_ATC_BUSERROR;
}
- if (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)
+ if (state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)
{
atc_data |= M68K_MMU_ATC_WRITE_PR;
}
- if (!rw && !(m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
+ if (!rw && !(state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
{
atc_data |= M68K_MMU_ATC_MODIFIED;
}
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
// if tag bits and function code match, don't add
- if (m68ki_cpu.mmu_atc_tag[i] == atc_tag)
+ if (state->mmu_atc_tag[i] == atc_tag)
{
- MMULOG(("%s: hit, old %08x new %08x\n", __func__, m68ki_cpu.mmu_atc_data[i], atc_data));
- m68ki_cpu.mmu_atc_data[i] = atc_data;
+ MMULOG(("%s: hit, old %08x new %08x\n", __func__, state->mmu_atc_data[i], atc_data));
+ state->mmu_atc_data[i] = atc_data;
return;
}
}
int found = -1;
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
- if (!(m68ki_cpu.mmu_atc_tag[i] & M68K_MMU_ATC_VALID))
+ if (!(state->mmu_atc_tag[i] & M68K_MMU_ATC_VALID))
{
found = i;
break;
// did we find an entry? steal one by round-robin then
if (found == -1)
{
- found = m68ki_cpu.mmu_atc_rr++;
+ found = state->mmu_atc_rr++;
- if (m68ki_cpu.mmu_atc_rr >= MMU_ATC_ENTRIES)
+ if (state->mmu_atc_rr >= MMU_ATC_ENTRIES)
{
- m68ki_cpu.mmu_atc_rr = 0;
+ state->mmu_atc_rr = 0;
}
}
// add the entry
MMULOG(("ATC[%2d] add: log %08x -> phys %08x (fc=%d) data=%08x\n",
found, (logical >> ps) << ps, (physical >> ps) << ps, fc, atc_data));
- m68ki_cpu.mmu_atc_tag[found] = atc_tag;
- m68ki_cpu.mmu_atc_data[found] = atc_data;
+ state->mmu_atc_tag[found] = atc_tag;
+ state->mmu_atc_data[found] = atc_data;
}
// pmmu_atc_flush: flush entire ATC
// 7fff0003 001ffd10 80f05750 is what should load
-void pmmu_atc_flush()
+void pmmu_atc_flush(m68ki_cpu_core *state)
{
- MMULOG(("ATC flush: pc=%08x\n", m68ki_cpu.ppc));
-// std::fill(std::begin(m68ki_cpu.mmu_atc_tag), std::end(m68ki_cpu.mmu_atc_tag), 0);
+ MMULOG(("ATC flush: pc=%08x\n", state->ppc));
+// std::fill(std::begin(state->mmu_atc_tag), std::end(state->mmu_atc_tag), 0);
for(int i=0;i<MMU_ATC_ENTRIES;i++)
- m68ki_cpu.mmu_atc_tag[i]=0;
- m68ki_cpu.mmu_atc_rr = 0;
+ state->mmu_atc_tag[i]=0;
+ state->mmu_atc_rr = 0;
}
-int fc_from_modes(uint16 modes);
+int fc_from_modes(m68ki_cpu_core *state, uint16 modes);
-void pmmu_atc_flush_fc_ea(uint16 modes)
+void pmmu_atc_flush_fc_ea(m68ki_cpu_core *state, uint16 modes)
{
unsigned int fcmask = (modes >> 5) & 7;
- unsigned int fc = fc_from_modes(modes) & fcmask;
- unsigned int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
+ unsigned int fc = fc_from_modes(state, modes) & fcmask;
+ unsigned int ps = (state->mmu_tc >> 20) & 0xf;
unsigned int mode = (modes >> 10) & 7;
uint32 ea;
{
case 1: // PFLUSHA
MMULOG(("PFLUSHA: mode %d\n", mode));
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
break;
case 4: // flush by fc
MMULOG(("flush by fc: %d, mask %d\n", fc, fcmask));
for(int i=0,e;i<MMU_ATC_ENTRIES;i++)
{
- e=m68ki_cpu.mmu_atc_tag[i];
+ e=state->mmu_atc_tag[i];
if ((e & M68K_MMU_ATC_VALID) && ((e >> 24) & fcmask) == fc)
{
MMULOG(("flushing entry %08x\n", e));
- m68ki_cpu.mmu_atc_tag[i] = 0;
+ state->mmu_atc_tag[i] = 0;
}
}
break;
case 6: // flush by fc + ea
- ea = DECODE_EA_32(m68ki_cpu.ir);
+ ea = DECODE_EA_32(state, state->ir);
MMULOG(("flush by fc/ea: fc %d, mask %d, ea %08x\n", fc, fcmask, ea));
for(unsigned int i=0,e;i<MMU_ATC_ENTRIES;i++)
{
- e=m68ki_cpu.mmu_atc_tag[i];
+ e=state->mmu_atc_tag[i];
if ((e & M68K_MMU_ATC_VALID) &&
(((e >> 24) & fcmask) == fc) &&
// (((e >> ps) << (ps - 8)) == ((ea >> ps) << (ps - 8))))
( (e << ps) == (ea >> 8 << ps) ))
{
MMULOG(("flushing entry %08x\n", e));
- m68ki_cpu.mmu_atc_tag[i] = 0;
+ state->mmu_atc_tag[i] = 0;
}
}
break;
}
//template<bool ptest>
-uint16 pmmu_atc_lookup(uint32 addr_in, int fc, uint16 rw,
- uint32 *addr_out,int ptest)
+uint16 pmmu_atc_lookup(m68ki_cpu_core *state, uint32 addr_in, int fc, uint16 rw, uint32 *addr_out, int ptest)
{
MMULOG(("%s: LOOKUP addr_in=%08x, fc=%d, ptest=%d, rw=%d\n", __func__, addr_in, fc, ptest,rw));
- unsigned int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
+ unsigned int ps = (state->mmu_tc >> 20) & 0xf;
uint32 atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | ((addr_in >> ps) << (ps - 8));
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
- if (m68ki_cpu.mmu_atc_tag[i] != atc_tag)
+ if (state->mmu_atc_tag[i] != atc_tag)
{
continue;
}
- uint32 atc_data = m68ki_cpu.mmu_atc_data[i];
+ uint32 atc_data = state->mmu_atc_data[i];
if (!ptest && !rw)
{
// entry, and creating a new entry with the M bit set.
if (!(atc_data & M68K_MMU_ATC_MODIFIED))
{
- m68ki_cpu.mmu_atc_tag[i] = 0;
+ state->mmu_atc_tag[i] = 0;
continue;
}
}
- m68ki_cpu.mmu_tmp_sr = 0;
+ state->mmu_tmp_sr = 0;
if (atc_data & M68K_MMU_ATC_MODIFIED)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
+ state->mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
}
if (atc_data & M68K_MMU_ATC_WRITE_PR)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
+ state->mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
}
if (atc_data & M68K_MMU_ATC_BUSERROR)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
+ state->mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
}
*addr_out = (atc_data << 8) | (addr_in & ~(((uint32)~0) << ps));
MMULOG(("%s: addr_in=%08x, addr_out=%08x, MMU SR %04x\n",
- __func__, addr_in, *addr_out, m68ki_cpu.mmu_tmp_sr));
+ __func__, addr_in, *addr_out, state->mmu_tmp_sr));
return 1;
}
MMULOG(("%s: lookup failed\n", __func__));
if (ptest)
{
- m68ki_cpu.mmu_tmp_sr = M68K_MMU_SR_INVALID;
+ state->mmu_tmp_sr = M68K_MMU_SR_INVALID;
}
return 0;
}
-uint16 pmmu_match_tt(uint32 addr_in, int fc, uint32 tt, uint16 rw)
+uint16 pmmu_match_tt(m68ki_cpu_core *state, uint32 addr_in, int fc, uint32 tt, uint16 rw)
{
if (!(tt & M68K_MMU_TT_ENABLE))
{
return 0;
}
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_TRANSPARENT;
+ state->mmu_tmp_sr |= M68K_MMU_SR_TRANSPARENT;
return 1;
}
-void update_descriptor(uint32 tptr, int type, uint32 entry, int16 rw)
+void update_descriptor(m68ki_cpu_core *state, uint32 tptr, int type, uint32 entry, int16 rw)
{
if (type == M68K_MMU_DF_DT_PAGE && !rw &&
!(entry & M68K_MMU_DF_MODIFIED) &&
//template<bool _long>
-void update_sr(int type, uint32 tbl_entry, int fc,uint16 _long)
+void update_sr(m68ki_cpu_core *state, int type, uint32 tbl_entry, int fc, uint16 _long)
{
if (m_side_effects_disabled)
{
case M68K_MMU_DF_DT_PAGE:
if (tbl_entry & M68K_MMU_DF_MODIFIED)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
+ state->mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
}
/* FALLTHROUGH */
if (tbl_entry & M68K_MMU_DF_WP)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
+ state->mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
}
if (_long && !(fc & 4) && (tbl_entry & M68K_MMU_DF_SUPERVISOR))
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_SUPERVISOR_ONLY;
+ state->mmu_tmp_sr |= M68K_MMU_SR_SUPERVISOR_ONLY;
}
break;
default:
}
//template<bool ptest>
-uint16 pmmu_walk_tables(uint32 addr_in, int type, uint32 table, uint8 fc,
- int limit, uint16 rw, uint32 *addr_out, int ptest)
+uint16 pmmu_walk_tables(m68ki_cpu_core *state, uint32 addr_in, int type, uint32 table, uint8 fc, int limit, uint16 rw,
+ uint32 *addr_out, int ptest)
{
int level = 0;
- uint32 bits = m68ki_cpu.mmu_tc & 0xffff;
- int pagesize = (m68ki_cpu.mmu_tc >> 20) & 0xf;
- int is = (m68ki_cpu.mmu_tc >> 16) & 0xf;
+ uint32 bits = state->mmu_tc & 0xffff;
+ int pagesize = (state->mmu_tc >> 20) & 0xf;
+ int is = (state->mmu_tc >> 16) & 0xf;
int bitpos = 12;
int resolved = 0;
int pageshift = is;
addr_in <<= is;
- m68ki_cpu.mmu_tablewalk = 1;
+ state->mmu_tablewalk = 1;
- if (m68ki_cpu.mmu_tc & M68K_MMU_TC_FCL)
+ if (state->mmu_tc & M68K_MMU_TC_FCL)
{
bitpos = 16;
}
switch(type)
{
case M68K_MMU_DF_DT_INVALID: // invalid, will cause MMU exception
- m68ki_cpu.mmu_tmp_sr = M68K_MMU_SR_INVALID;
- MMULOG(("PMMU: DT0 PC=%x (addr_in %08x -> %08x)\n", m68ki_cpu.ppc, addr_in, *addr_out));
+ state->mmu_tmp_sr = M68K_MMU_SR_INVALID;
+ MMULOG(("PMMU: DT0 PC=%x (addr_in %08x -> %08x)\n", state->ppc, addr_in, *addr_out));
resolved = 1;
break;
table = tbl_entry & M68K_MMU_DF_ADDR_MASK;
if (!m_side_effects_disabled)
{
- update_sr(type, tbl_entry, fc,0);
+ update_sr(state, type, tbl_entry, fc, 0);
if (!ptest)
{
- update_descriptor(*addr_out, type, tbl_entry, rw);
+ update_descriptor(state, *addr_out, type, tbl_entry, rw);
}
}
break;
table = tbl_entry2 & M68K_MMU_DF_ADDR_MASK;
if (!m_side_effects_disabled)
{
- update_sr(type, tbl_entry, fc,1);
+ update_sr(state, type, tbl_entry, fc, 1);
if (!ptest)
{
- update_descriptor(*addr_out, type, tbl_entry, rw);
+ update_descriptor(state, *addr_out, type, tbl_entry, rw);
}
}
break;
}
- if (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR)
+ if (state->mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR)
{
// Bus error during page table walking is always fatal
resolved = 1;
if (!ptest && !m_side_effects_disabled)
{
- if (!rw && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
+ if (!rw && (state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
{
resolved = 1;
break;
}
- if (!(fc & 4) && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY))
+ if (!(fc & 4) && (state->mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY))
{
resolved = 1;
break;
} while(level < limit && !resolved);
- m68ki_cpu.mmu_tmp_sr &= 0xfff0;
- m68ki_cpu.mmu_tmp_sr |= level;
- MMULOG(("MMU SR after walk: %04X\n", m68ki_cpu.mmu_tmp_sr));
- m68ki_cpu.mmu_tablewalk = 0;
+ state->mmu_tmp_sr &= 0xfff0;
+ state->mmu_tmp_sr |= level;
+ MMULOG(("MMU SR after walk: %04X\n", state->mmu_tmp_sr));
+ state->mmu_tablewalk = 0;
return resolved;
}
// pmmu_translate_addr_with_fc: perform 68851/68030-style PMMU address translation
//template<bool ptest, bool pload>
-uint32 pmmu_translate_addr_with_fc(uint32 addr_in, uint8 fc, uint16 rw, int limit,int ptest,int pload)
+uint32 pmmu_translate_addr_with_fc(m68ki_cpu_core *state, uint32 addr_in, uint8 fc, uint16 rw, int limit, int ptest,
+ int pload)
{
uint32 addr_out = 0;
MMULOG(("%s: addr_in=%08x, fc=%d, ptest=%d, rw=%d, limit=%d, pload=%d\n",
__func__, addr_in, fc, ptest, rw, limit, pload));
- m68ki_cpu.mmu_tmp_sr = 0;
+ state->mmu_tmp_sr = 0;
- m68ki_cpu.mmu_last_logical_addr = addr_in;
+ state->mmu_last_logical_addr = addr_in;
- if (pmmu_match_tt(addr_in, fc, m68ki_cpu.mmu_tt0, rw) ||
- pmmu_match_tt(addr_in, fc, m68ki_cpu.mmu_tt1, rw) ||
+ if (pmmu_match_tt(state, addr_in, fc, state->mmu_tt0, rw) ||
+ pmmu_match_tt(state, addr_in, fc, state->mmu_tt1, rw) ||
fc == 7)
{
return addr_in;
if (ptest && limit == 0)
{
- pmmu_atc_lookup(addr_in, fc, rw, &addr_out, 1);
+ pmmu_atc_lookup(state, addr_in, fc, rw, &addr_out, 1);
return addr_out;
}
- if (!ptest && !pload && pmmu_atc_lookup(addr_in, fc, rw, &addr_out, 0))
+ if (!ptest && !pload && pmmu_atc_lookup(state, addr_in, fc, rw, &addr_out, 0))
{
- if ((m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR) || (!rw && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)))
+ if ((state->mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR) || (!rw && (state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)))
{
MMULOG(("set atc hit buserror: addr_in=%08x, addr_out=%x, rw=%x, fc=%d, sz=%d\n",
- addr_in, addr_out, m68ki_cpu.mmu_tmp_rw, m68ki_cpu.mmu_tmp_fc, m68ki_cpu.mmu_tmp_sz));
- pmmu_set_buserror(addr_in);
+ addr_in, addr_out, state->mmu_tmp_rw, state->mmu_tmp_fc, state->mmu_tmp_sz));
+ pmmu_set_buserror(state, addr_in);
}
return addr_out;
}
int type;
uint32 tbl_addr;
// if SRP is enabled and we're in supervisor mode, use it
- if ((m68ki_cpu.mmu_tc & M68K_MMU_TC_SRE) && (fc & 4))
+ if ((state->mmu_tc & M68K_MMU_TC_SRE) && (fc & 4))
{
- tbl_addr = m68ki_cpu.mmu_srp_aptr & M68K_MMU_DF_ADDR_MASK;
- type = m68ki_cpu.mmu_srp_limit & M68K_MMU_DF_DT;
+ tbl_addr = state->mmu_srp_aptr & M68K_MMU_DF_ADDR_MASK;
+ type = state->mmu_srp_limit & M68K_MMU_DF_DT;
}
else // else use the CRP
{
- tbl_addr = m68ki_cpu.mmu_crp_aptr & M68K_MMU_DF_ADDR_MASK;
- type = m68ki_cpu.mmu_crp_limit & M68K_MMU_DF_DT;
+ tbl_addr = state->mmu_crp_aptr & M68K_MMU_DF_ADDR_MASK;
+ type = state->mmu_crp_limit & M68K_MMU_DF_DT;
}
- if (!pmmu_walk_tables(addr_in, type, tbl_addr, fc, limit, rw, &addr_out, ptest))
+ if (!pmmu_walk_tables(state, addr_in, type, tbl_addr, fc, limit, rw, &addr_out, ptest))
{
MMULOG(("%s: addr_in=%08x, type=%x, tbl_addr=%x, fc=%d, limit=%x, rw=%x, addr_out=%x, ptest=%d\n",
__func__, addr_in, type, tbl_addr, fc, limit, rw, addr_out, ptest));
return addr_out;
}
- if ((m68ki_cpu.mmu_tmp_sr & (M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY)) ||
- ((m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT) && !rw))
+ if ((state->mmu_tmp_sr & (M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY)) ||
+ ((state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT) && !rw))
{
if (!pload)
{
- MMULOG(("%s: set buserror (SR %04X)\n", __func__, m68ki_cpu.mmu_tmp_sr));
- pmmu_set_buserror(addr_in);
+ MMULOG(("%s: set buserror (SR %04X)\n", __func__, state->mmu_tmp_sr));
+ pmmu_set_buserror(state, addr_in);
}
}
// between RW and the root type
if (!m_side_effects_disabled)
{
- pmmu_atc_add(addr_in, addr_out, fc, rw && type != 1);
+ pmmu_atc_add(state, addr_in, addr_out, fc, rw && type != 1);
}
- MMULOG(("PMMU: [%08x] => [%08x] (SR %04x)\n", addr_in, addr_out, m68ki_cpu.mmu_tmp_sr));
+ MMULOG(("PMMU: [%08x] => [%08x] (SR %04x)\n", addr_in, addr_out, state->mmu_tmp_sr));
return addr_out;
}
// FC bits: 2 = supervisor, 1 = program, 0 = data
// the 68040 is a subset of the 68851 and 68030 PMMUs - the page table sizes are fixed, there is no early termination, etc, etc.
-uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest)
+uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, uint8 fc, uint8 ptest)
{
uint32 addr_out, tt0, tt1;
addr_out = addr_in;
- m68ki_cpu.mmu_tmp_sr = 0;
+ state->mmu_tmp_sr = 0;
// transparent translation registers are always in force even if the PMMU itself is disabled
// they don't do much in emulation because we never write out of order, but the write-protect and cache control features
// are emulatable, and apparently transparent translation regions skip the page table lookup.
if (fc & 1) // data, use DTT0/DTT1
{
- tt0 = m68ki_cpu.mmu_dtt0;
- tt1 = m68ki_cpu.mmu_dtt1;
+ tt0 = state->mmu_dtt0;
+ tt1 = state->mmu_dtt1;
}
else if (fc & 2) // program, use ITT0/ITT1
{
- tt0 = m68ki_cpu.mmu_itt0;
- tt1 = m68ki_cpu.mmu_itt1;
+ tt0 = state->mmu_itt0;
+ tt1 = state->mmu_itt1;
}
else
{
if ((addr_in & mask) == (tt0 & mask) && (fc & fcmask[(tt0 >> 13) & 3]) == fcmatch[(tt0 >> 13) & 3])
{
MMULOG(("TT0 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt0, mask));
- if ((tt0 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect?
+ if ((tt0 & 4) && !state->mmu_tmp_rw && !ptest) // write protect?
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
return addr_in;
if ((addr_in & mask) == (tt1 & mask) && (fc & fcmask[(tt1 >> 13) & 3]) == fcmatch[(tt1 >> 13) & 3])
{
MMULOG(("TT1 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt1, mask));
- if ((tt1 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect?
+ if ((tt1 & 4) && !state->mmu_tmp_rw && !ptest) // write protect?
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
return addr_in;
}
}
- if (m68ki_cpu.pmmu_enabled)
+ if (state->pmmu_enabled)
{
uint32 root_idx = (addr_in >> 25) & 0x7f;
uint32 ptr_idx = (addr_in >> 18) & 0x7f;
// select supervisor or user root pointer
if (fc & 4)
{
- root_ptr = m68ki_cpu.mmu_srp_aptr + (root_idx<<2);
+ root_ptr = state->mmu_srp_aptr + (root_idx<<2);
}
else
{
- root_ptr = m68ki_cpu.mmu_urp_aptr + (root_idx<<2);
+ root_ptr = state->mmu_urp_aptr + (root_idx<<2);
}
// get the root entry
// PTEST: any write protect bits set in the search tree will set W in SR
if ((ptest) && (root_entry & 4))
{
- m68ki_cpu.mmu_tmp_sr |= 4;
+ state->mmu_tmp_sr |= 4;
}
pointer_ptr = (root_entry & ~0x1ff) + (ptr_idx<<2);
// PTEST: any write protect bits set in the search tree will set W in SR
if ((ptest) && (pointer_entry & 4))
{
- m68ki_cpu.mmu_tmp_sr |= 4;
+ state->mmu_tmp_sr |= 4;
}
// update U bit on this pointer entry too
MMULOG(("pointer entry = %08x\n", pointer_entry));
// write protected by the root or pointer entries?
- if ((((root_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((pointer_entry & 4) && !m68ki_cpu.mmu_tmp_rw)) && !ptest)
+ if ((((root_entry & 4) && !state->mmu_tmp_rw) || ((pointer_entry & 4) && !state->mmu_tmp_rw)) && !ptest)
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
return addr_in;
}
// is UDT valid on the pointer entry?
if (!(pointer_entry & 2) && !ptest)
{
- logerror("Invalid pointer entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in);
- pmmu_set_buserror(addr_in);
+ logerror("Invalid pointer entry! PC=%x, addr=%x\n", state->ppc, addr_in);
+ pmmu_set_buserror(state, addr_in);
return addr_in;
}
}
else // throw an error
{
- logerror("Invalid root entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in);
+ logerror("Invalid root entry! PC=%x, addr=%x\n", state->ppc, addr_in);
if (!ptest)
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
return addr_in;
}
// now do the page lookup
- if (m68ki_cpu.mmu_tc & 0x4000) // 8k pages?
+ if (state->mmu_tc & 0x4000) // 8k pages?
{
page_idx = (addr_in >> 13) & 0x1f;
page = addr_in & 0x1fff;
page_ptr = pointer_entry + (page_idx<<2);
page_entry = m68k_read_memory_32(page_ptr);
- m68ki_cpu.mmu_last_page_entry_addr = page_ptr;
+ state->mmu_last_page_entry_addr = page_ptr;
MMULOG(("page_entry = %08x\n", page_entry));
while ((page_entry & 3) == 2)
{
page_entry = m68k_read_memory_32(page_entry & ~0x3);
- m68ki_cpu.mmu_last_page_entry_addr = (page_entry & ~0x3);
+ state->mmu_last_page_entry_addr = (page_entry & ~0x3);
}
- m68ki_cpu.mmu_last_page_entry = page_entry;
+ state->mmu_last_page_entry = page_entry;
// is the page write protected or supervisor protected?
- if ((((page_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((page_entry & 0x80) && !(fc & 4))) && !ptest)
+ if ((((page_entry & 4) && !state->mmu_tmp_rw) || ((page_entry & 0x80) && !(fc & 4))) && !ptest)
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
return addr_in;
}
switch (page_entry & 3)
{
case 0: // invalid
- MMULOG(("Invalid page entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in));
+ MMULOG(("Invalid page entry! PC=%x, addr=%x\n", state->ppc, addr_in));
if (!ptest)
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
return addr_in;
case 1:
case 3: // normal
- if (m68ki_cpu.mmu_tc & 0x4000) // 8k pages?
+ if (state->mmu_tc & 0x4000) // 8k pages?
{
addr_out = (page_entry & ~0x1fff) | page;
}
page_entry |= 0x8; // always set the U bit
// if we're writing, the M bit comes into play
- if (!m68ki_cpu.mmu_tmp_rw)
+ if (!state->mmu_tmp_rw)
{
page_entry |= 0x10; // set Modified
}
// if these updates resulted in a change, write the entry back where we found it
- if (page_entry != m68ki_cpu.mmu_last_page_entry && !m_side_effects_disabled)
+ if (page_entry != state->mmu_last_page_entry && !m_side_effects_disabled)
{
- m68ki_cpu.mmu_last_page_entry = page_entry;
- m68k_write_memory_32(m68ki_cpu.mmu_last_page_entry_addr, m68ki_cpu.mmu_last_page_entry);
+ state->mmu_last_page_entry = page_entry;
+ m68k_write_memory_32(state->mmu_last_page_entry_addr, state->mmu_last_page_entry);
}
}
else
{
// page entry: UR G U1 U0 S CM CM M U W PDT
// SR: B G U1 U0 S CM CM M 0 W T R
- m68ki_cpu.mmu_tmp_sr |= ((addr_out & ~0xfff) || (page_entry & 0x7f4));
+ state->mmu_tmp_sr |= ((addr_out & ~0xfff) || (page_entry & 0x7f4));
}
break;
}
// pmmu_translate_addr: perform 68851/68030-style PMMU address translation
-uint32 pmmu_translate_addr(uint32 addr_in, uint16 rw)
+uint32 pmmu_translate_addr(m68ki_cpu_core *state, uint32 addr_in, uint16 rw)
{
uint32 addr_out;
- if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
+ if (CPU_TYPE_IS_040_PLUS(state->cpu_type))
{
- addr_out = pmmu_translate_addr_with_fc_040(addr_in, m68ki_cpu.mmu_tmp_fc, 0);
+ addr_out = pmmu_translate_addr_with_fc_040(state, addr_in, state->mmu_tmp_fc, 0);
}
else
{
- addr_out = pmmu_translate_addr_with_fc(addr_in, m68ki_cpu.mmu_tmp_fc, rw,7,0,0);
+ addr_out = pmmu_translate_addr_with_fc(state, addr_in, state->mmu_tmp_fc, rw, 7, 0, 0);
MMULOG(("ADDRIN %08X, ADDROUT %08X\n", addr_in, addr_out));
}
return addr_out;
}
-int fc_from_modes(uint16 modes)
+int fc_from_modes(m68ki_cpu_core *state, uint16 modes)
{
if ((modes & 0x1f) == 0)
{
- return m68ki_cpu.sfc;
+ return state->sfc;
}
if ((modes & 0x1f) == 1)
{
- return m68ki_cpu.dfc;
+ return state->dfc;
}
- if (m68ki_cpu.cpu_type & CPU_TYPE_030)
+ if (state->cpu_type & CPU_TYPE_030)
{
// 68030 has 3 bits fc, but 68851 4 bits
if (((modes >> 3) & 3) == 1)
return 0;
}
-void m68851_pload(uint32 ea, uint16 modes)
+void m68851_pload(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
- uint32 ltmp = DECODE_EA_32(ea);
- int fc = fc_from_modes(modes);
+ uint32 ltmp = DECODE_EA_32(state, ea);
+ int fc = fc_from_modes(state, modes);
uint16 rw = !!(modes & 0x200);
MMULOG(("%s: PLOAD%c addr=%08x, fc=%d\n", __func__, rw ? 'R' : 'W', ltmp, fc));
// MC68851 traps if MMU is not enabled, 030 not
- if (m68ki_cpu.pmmu_enabled || (m68ki_cpu.cpu_type & CPU_TYPE_030))
+ if (state->pmmu_enabled || (state->cpu_type & CPU_TYPE_030))
{
- if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
+ if (CPU_TYPE_IS_040_PLUS(state->cpu_type))
{
- pmmu_translate_addr_with_fc_040(ltmp, fc, 0);
+ pmmu_translate_addr_with_fc_040(state, ltmp, fc, 0);
}
else
{
- pmmu_translate_addr_with_fc(ltmp, fc, rw , 7, 0, 1);
+ pmmu_translate_addr_with_fc(state, ltmp, fc, rw, 7, 0, 1);
}
}
else
{
MMULOG(("PLOAD with MMU disabled on MC68851\n"));
- m68ki_exception_trap(57);
+ m68ki_exception_trap(state, 57);
return;
}
}
-void m68851_ptest(uint32 ea, uint16 modes)
+void m68851_ptest(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
- uint32 v_addr = DECODE_EA_32(ea);
+ uint32 v_addr = DECODE_EA_32(state, ea);
uint32 p_addr;
int level = (modes >> 10) & 7;
uint16 rw = !!(modes & 0x200);
- int fc = fc_from_modes(modes);
+ int fc = fc_from_modes(state, modes);
MMULOG(("PMMU: PTEST%c (%04X) pc=%08x sp=%08x va=%08x fc=%x level=%x a=%d, areg=%d\n",
- rw ? 'R' : 'W', modes, m68ki_cpu.ppc, REG_A[7], v_addr, fc, level,
+ rw ? 'R' : 'W', modes, state->ppc, REG_A[7], v_addr, fc, level,
(modes & 0x100) ? 1 : 0, (modes >> 5) & 7));
- if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
+ if (CPU_TYPE_IS_040_PLUS(state->cpu_type))
{
- p_addr = pmmu_translate_addr_with_fc_040(v_addr, fc, 1);
+ p_addr = pmmu_translate_addr_with_fc_040(state, v_addr, fc, 1);
}
else
{
- p_addr = pmmu_translate_addr_with_fc(v_addr, fc, rw, level, 1, 0);
+ p_addr = pmmu_translate_addr_with_fc(state, v_addr, fc, rw, level, 1, 0);
}
- m68ki_cpu.mmu_sr = m68ki_cpu.mmu_tmp_sr;
+ state->mmu_sr = state->mmu_tmp_sr;
- MMULOG(("PMMU: PTEST result: %04x pa=%08x\n", m68ki_cpu.mmu_sr, p_addr));
+ MMULOG(("PMMU: PTEST result: %04x pa=%08x\n", state->mmu_sr, p_addr));
if (modes & 0x100)
{
int areg = (modes >> 5) & 7;
- WRITE_EA_32(0x08 | areg, p_addr);
+ WRITE_EA_32(state, 0x08 | areg, p_addr);
}
}
-void m68851_pmove_get(uint32 ea, uint16 modes)
+void m68851_pmove_get(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
switch ((modes>>10) & 0x3f)
{
case 0x02: // transparent translation register 0
- WRITE_EA_32(ea, m68ki_cpu.mmu_tt0);
- MMULOG(("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt0));
+ WRITE_EA_32(state, ea, state->mmu_tt0);
+ MMULOG(("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", state->ppc, state->mmu_tt0));
break;
case 0x03: // transparent translation register 1
- WRITE_EA_32(ea, m68ki_cpu.mmu_tt1);
- MMULOG(("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt1));
+ WRITE_EA_32(state, ea, state->mmu_tt1);
+ MMULOG(("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", state->ppc, state->mmu_tt1));
break;
case 0x10: // translation control register
- WRITE_EA_32(ea, m68ki_cpu.mmu_tc);
- MMULOG(("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tc));
+ WRITE_EA_32(state, ea, state->mmu_tc);
+ MMULOG(("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", state->ppc, state->mmu_tc));
break;
case 0x12: // supervisor root pointer
- WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_srp_limit<<32 | (uint64)m68ki_cpu.mmu_srp_aptr);
- MMULOG(("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr));
+ WRITE_EA_64(state, ea, (uint64)state->mmu_srp_limit<<32 | (uint64)state->mmu_srp_aptr);
+ MMULOG(("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", state->ppc, state->mmu_srp_limit, state->mmu_srp_aptr));
break;
case 0x13: // CPU root pointer
- WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_crp_limit<<32 | (uint64)m68ki_cpu.mmu_crp_aptr);
- MMULOG(("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr));
+ WRITE_EA_64(state, ea, (uint64)state->mmu_crp_limit<<32 | (uint64)state->mmu_crp_aptr);
+ MMULOG(("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", state->ppc, state->mmu_crp_limit, state->mmu_crp_aptr));
break;
default:
- logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68ki_cpu.pc);
+ logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, state->pc);
return;
}
if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP, TT with FD bit clear
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
}
-void m68851_pmove_put(uint32 ea, uint16 modes)
+void m68851_pmove_put(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
uint64 temp64;
switch ((modes>>13) & 7)
{
case 0:
{
- uint32 temp = READ_EA_32(ea);
+ uint32 temp = READ_EA_32(state, ea);
if (((modes >> 10) & 7) == 2)
{
- MMULOG(("WRITE TT0 = 0x%08x\n", m68ki_cpu.mmu_tt0));
- m68ki_cpu.mmu_tt0 = temp;
+ MMULOG(("WRITE TT0 = 0x%08x\n", state->mmu_tt0));
+ state->mmu_tt0 = temp;
}
else if (((modes >> 10) & 7) == 3)
{
- MMULOG(("WRITE TT1 = 0x%08x\n", m68ki_cpu.mmu_tt1));
- m68ki_cpu.mmu_tt1 = temp;
+ MMULOG(("WRITE TT1 = 0x%08x\n", state->mmu_tt1));
+ state->mmu_tt1 = temp;
}
break;
// FIXME: unreachable
if (!(modes & 0x100))
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
}
/* fall through */
/* no break */
case 1:
- logerror("680x0: unknown PMOVE case 1, PC %x\n", m68ki_cpu.pc);
+ logerror("680x0: unknown PMOVE case 1, PC %x\n", state->pc);
break;
case 2:
switch ((modes >> 10) & 7)
{
case 0: // translation control register
- m68ki_cpu.mmu_tc = READ_EA_32(ea);
- MMULOG(("PMMU: TC = %08x\n", m68ki_cpu.mmu_tc));
+ state->mmu_tc = READ_EA_32(state, ea);
+ MMULOG(("PMMU: TC = %08x\n", state->mmu_tc));
- if (m68ki_cpu.mmu_tc & 0x80000000)
+ if (state->mmu_tc & 0x80000000)
{
int bits = 0;
for (int shift = 20; shift >= 0; shift -= 4)
{
- bits += (m68ki_cpu.mmu_tc >> shift) & 0x0f;
+ bits += (state->mmu_tc >> shift) & 0x0f;
}
- if (bits != 32 || !((m68ki_cpu.mmu_tc >> 23) & 1))
+ if (bits != 32 || !((state->mmu_tc >> 23) & 1))
{
logerror("MMU: TC invalid!\n");
- m68ki_cpu.mmu_tc &= ~0x80000000;
- m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
+ state->mmu_tc &= ~0x80000000;
+ m68ki_exception_trap(state, EXCEPTION_MMU_CONFIGURATION);
} else {
- m68ki_cpu.pmmu_enabled = 1;
+ state->pmmu_enabled = 1;
}
MMULOG(("PMMU enabled\n"));
}
else
{
- m68ki_cpu.pmmu_enabled = 0;
+ state->pmmu_enabled = 0;
MMULOG(("PMMU disabled\n"));
}
if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP with FD bit clear
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
break;
case 2: // supervisor root pointer
- temp64 = READ_EA_64(ea);
- m68ki_cpu.mmu_srp_limit = (temp64 >> 32) & 0xffffffff;
- m68ki_cpu.mmu_srp_aptr = temp64 & 0xffffffff;
- MMULOG(("PMMU: SRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr));
+ temp64 = READ_EA_64(state, ea);
+ state->mmu_srp_limit = (temp64 >> 32) & 0xffffffff;
+ state->mmu_srp_aptr = temp64 & 0xffffffff;
+ MMULOG(("PMMU: SRP limit = %08x aptr = %08x\n", state->mmu_srp_limit, state->mmu_srp_aptr));
// SRP type 0 is not allowed
- if ((m68ki_cpu.mmu_srp_limit & 3) == 0)
+ if ((state->mmu_srp_limit & 3) == 0)
{
- m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
+ m68ki_exception_trap(state, EXCEPTION_MMU_CONFIGURATION);
return;
}
if (!(modes & 0x100))
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
break;
case 3: // CPU root pointer
- temp64 = READ_EA_64(ea);
- m68ki_cpu.mmu_crp_limit = (temp64 >> 32) & 0xffffffff;
- m68ki_cpu.mmu_crp_aptr = temp64 & 0xffffffff;
- MMULOG(("PMMU: CRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr));
+ temp64 = READ_EA_64(state, ea);
+ state->mmu_crp_limit = (temp64 >> 32) & 0xffffffff;
+ state->mmu_crp_aptr = temp64 & 0xffffffff;
+ MMULOG(("PMMU: CRP limit = %08x aptr = %08x\n", state->mmu_crp_limit, state->mmu_crp_aptr));
// CRP type 0 is not allowed
- if ((m68ki_cpu.mmu_crp_limit & 3) == 0)
+ if ((state->mmu_crp_limit & 3) == 0)
{
- m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
+ m68ki_exception_trap(state, EXCEPTION_MMU_CONFIGURATION);
return;
}
if (!(modes & 0x100))
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
break;
case 7: // MC68851 Access Control Register
- if (m68ki_cpu.cpu_type == CPU_TYPE_020)
+ if (state->cpu_type == CPU_TYPE_020)
{
// DomainOS on Apollo DN3000 will only reset this to 0
- uint16 mmu_ac = READ_EA_16(ea);
+ uint16 mmu_ac = READ_EA_16(state, ea);
if (mmu_ac != 0)
{
MMULOG(("680x0 PMMU: pc=%x PMOVE to mmu_ac=%08x\n",
- m68ki_cpu.ppc, mmu_ac));
+ state->ppc, mmu_ac));
}
break;
}
/* fall through */
/* no break */
default:
- logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68ki_cpu.pc);
+ logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, state->pc);
break;
}
break;
case 3: // MMU status
{
- uint32 temp = READ_EA_32(ea);
- logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68ki_cpu.pc);
+ uint32 temp = READ_EA_32(state, ea);
+ logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, state->pc);
}
break;
}
}
-void m68851_pmove(uint32 ea, uint16 modes)
+void m68851_pmove(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
switch ((modes>>13) & 0x7)
{
case 2: // MC68851 form, FD never set
if (modes & 0x200)
{
- m68851_pmove_get(ea, modes);
+ m68851_pmove_get(state, ea, modes);
break;
}
else // top 3 bits of modes: 010 for this, 011 for status, 000 for transparent translation regs
{
- m68851_pmove_put(ea, modes);
+ m68851_pmove_put(state, ea, modes);
break;
}
case 3: // MC68030 to/from status reg
if (modes & 0x200)
{
- MMULOG(("%s: read SR = %04x\n", __func__, m68ki_cpu.mmu_sr));
- WRITE_EA_16(ea, m68ki_cpu.mmu_sr);
+ MMULOG(("%s: read SR = %04x\n", __func__, state->mmu_sr));
+ WRITE_EA_16(state, ea, state->mmu_sr);
}
else
{
- m68ki_cpu.mmu_sr = READ_EA_16(ea);
- MMULOG(("%s: write SR = %04X\n", __func__, m68ki_cpu.mmu_sr));
+ state->mmu_sr = READ_EA_16(state, ea);
+ MMULOG(("%s: write SR = %04X\n", __func__, state->mmu_sr));
}
break;
default:
- logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes >> 13) & 0x7, modes, m68ki_cpu.pc);
+ logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes >> 13) & 0x7, modes, state->pc);
break;
}
}
-void m68851_mmu_ops()
+void m68851_mmu_ops(m68ki_cpu_core *state)
{
uint16 modes;
- uint32 ea = m68ki_cpu.ir & 0x3f;
+ uint32 ea = state->ir & 0x3f;
// catch the 2 "weird" encodings up front (PBcc)
- if ((m68ki_cpu.ir & 0xffc0) == 0xf0c0)
+ if ((state->ir & 0xffc0) == 0xf0c0)
{
logerror("680x0: unhandled PBcc\n");
return;
}
- else if ((m68ki_cpu.ir & 0xffc0) == 0xf080)
+ else if ((state->ir & 0xffc0) == 0xf080)
{
logerror("680x0: unhandled PBcc\n");
return;
}
- else if ((m68ki_cpu.ir & 0xffe0) == 0xf500)
+ else if ((state->ir & 0xffe0) == 0xf500)
{
- MMULOG(("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", REG_PC-4, m68ki_cpu.ir, (m68ki_cpu.ir >> 3) & 3, m68ki_cpu.ir & 7));
- pmmu_atc_flush();
+ MMULOG(("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", REG_PC-4, state->ir, (state->ir >> 3) & 3, state->ir & 7));
+ pmmu_atc_flush(state);
}
else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
{
- switch ((m68ki_cpu.ir>>9) & 0x7)
+ switch ((state->ir>>9) & 0x7)
{
case 0:
- modes = OPER_I_16();
+ modes = OPER_I_16(state);
if ((modes & 0xfde0) == 0x2000) // PLOAD
{
- m68851_pload(ea, modes);
+ m68851_pload(state, ea, modes);
return;
}
else if ((modes & 0xe200) == 0x2000) // PFLUSH
{
- pmmu_atc_flush_fc_ea(modes);
+ pmmu_atc_flush_fc_ea(state, modes);
return;
}
else if (modes == 0xa000) // PFLUSHR
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
return;
}
else if (modes == 0x2800) // PVALID (FORMAT 1)
}
else if ((modes & 0xe000) == 0x8000) // PTEST
{
- m68851_ptest(ea, modes);
+ m68851_ptest(state, ea, modes);
return;
}
else
{
- m68851_pmove(ea, modes);
+ m68851_pmove(state, ea, modes);
}
break;
default:
- logerror("680x0: unknown PMMU instruction group %d\n", (m68ki_cpu.ir>>9) & 0x7);
+ logerror("680x0: unknown PMMU instruction group %d\n", (state->ir>>9) & 0x7);
break;
}
}
addr_out = addr_in;
// check if LC 24-bit mode is enabled - this simply blanks out A31, the V8 ignores A30-24 always
- if (m68ki_cpu.hmmu_enabled == M68K_HMMU_ENABLE_LC)
+ if (state->hmmu_enabled == M68K_HMMU_ENABLE_LC)
{
addr_out = addr_in & 0xffffff;
}
- else if (m68ki_cpu.hmmu_enabled == M68K_HMMU_ENABLE_II) // the original II does a more complex translation
+ else if (state->hmmu_enabled == M68K_HMMU_ENABLE_II) // the original II does a more complex translation
{
addr_out = addr_in & 0xffffff;
int m68851_buserror(u32& addr)
{
- if (!m68ki_cpu.pmmu_enabled)
+ if (!state->pmmu_enabled)
{
return false;
}
- if (m68ki_cpu.mmu_tablewalk)
+ if (state->mmu_tablewalk)
{
MMULOG(("buserror during table walk\n"));
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
+ state->mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
return true;
}
- addr = m68ki_cpu.mmu_last_logical_addr;
+ addr = state->mmu_last_logical_addr;
return false;
}
*/
projects / pistorm / commitdiff