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21 #ifndef AVCODEC_HEVC_H
22 #define AVCODEC_HEVC_H
25 * Table 7-1 – NAL unit type codes and NAL unit type classes in
28 enum HEVCNALUnitType {
39 HEVC_NAL_VCL_N10 = 10,
40 HEVC_NAL_VCL_R11 = 11,
41 HEVC_NAL_VCL_N12 = 12,
42 HEVC_NAL_VCL_R13 = 13,
43 HEVC_NAL_VCL_N14 = 14,
44 HEVC_NAL_VCL_R15 = 15,
45 HEVC_NAL_BLA_W_LP = 16,
46 HEVC_NAL_BLA_W_RADL = 17,
47 HEVC_NAL_BLA_N_LP = 18,
48 HEVC_NAL_IDR_W_RADL = 19,
49 HEVC_NAL_IDR_N_LP = 20,
50 HEVC_NAL_CRA_NUT = 21,
51 HEVC_NAL_RSV_IRAP_VCL22 = 22,
52 HEVC_NAL_RSV_IRAP_VCL23 = 23,
53 HEVC_NAL_RSV_VCL24 = 24,
54 HEVC_NAL_RSV_VCL25 = 25,
55 HEVC_NAL_RSV_VCL26 = 26,
56 HEVC_NAL_RSV_VCL27 = 27,
57 HEVC_NAL_RSV_VCL28 = 28,
58 HEVC_NAL_RSV_VCL29 = 29,
59 HEVC_NAL_RSV_VCL30 = 30,
60 HEVC_NAL_RSV_VCL31 = 31,
65 HEVC_NAL_EOS_NUT = 36,
66 HEVC_NAL_EOB_NUT = 37,
68 HEVC_NAL_SEI_PREFIX = 39,
69 HEVC_NAL_SEI_SUFFIX = 40,
70 HEVC_NAL_RSV_NVCL41 = 41,
71 HEVC_NAL_RSV_NVCL42 = 42,
72 HEVC_NAL_RSV_NVCL43 = 43,
73 HEVC_NAL_RSV_NVCL44 = 44,
74 HEVC_NAL_RSV_NVCL45 = 45,
75 HEVC_NAL_RSV_NVCL46 = 46,
76 HEVC_NAL_RSV_NVCL47 = 47,
77 HEVC_NAL_UNSPEC48 = 48,
78 HEVC_NAL_UNSPEC49 = 49,
79 HEVC_NAL_UNSPEC50 = 50,
80 HEVC_NAL_UNSPEC51 = 51,
81 HEVC_NAL_UNSPEC52 = 52,
82 HEVC_NAL_UNSPEC53 = 53,
83 HEVC_NAL_UNSPEC54 = 54,
84 HEVC_NAL_UNSPEC55 = 55,
85 HEVC_NAL_UNSPEC56 = 56,
86 HEVC_NAL_UNSPEC57 = 57,
87 HEVC_NAL_UNSPEC58 = 58,
88 HEVC_NAL_UNSPEC59 = 59,
89 HEVC_NAL_UNSPEC60 = 60,
90 HEVC_NAL_UNSPEC61 = 61,
91 HEVC_NAL_UNSPEC62 = 62,
92 HEVC_NAL_UNSPEC63 = 63,
102 // 7.4.3.1: vps_max_layers_minus1 is in [0, 62].
103 HEVC_MAX_LAYERS = 63,
104 // 7.4.3.1: vps_max_sub_layers_minus1 is in [0, 6].
105 HEVC_MAX_SUB_LAYERS = 7,
106 // 7.4.3.1: vps_num_layer_sets_minus1 is in [0, 1023].
107 HEVC_MAX_LAYER_SETS = 1024,
109 // 7.4.2.1: vps_video_parameter_set_id is u(4).
110 HEVC_MAX_VPS_COUNT = 16,
111 // 7.4.3.2.1: sps_seq_parameter_set_id is in [0, 15].
112 HEVC_MAX_SPS_COUNT = 16,
113 // 7.4.3.3.1: pps_pic_parameter_set_id is in [0, 63].
114 HEVC_MAX_PPS_COUNT = 64,
116 // A.4.2: MaxDpbSize is bounded above by 16.
117 HEVC_MAX_DPB_SIZE = 16,
118 // 7.4.3.1: vps_max_dec_pic_buffering_minus1[i] is in [0, MaxDpbSize - 1].
119 HEVC_MAX_REFS = HEVC_MAX_DPB_SIZE,
121 // 7.4.3.2.1: num_short_term_ref_pic_sets is in [0, 64].
122 HEVC_MAX_SHORT_TERM_REF_PIC_SETS = 64,
123 // 7.4.3.2.1: num_long_term_ref_pics_sps is in [0, 32].
124 HEVC_MAX_LONG_TERM_REF_PICS = 32,
126 // A.3: all profiles require that CtbLog2SizeY is in [4, 6].
127 HEVC_MIN_LOG2_CTB_SIZE = 4,
128 HEVC_MAX_LOG2_CTB_SIZE = 6,
130 // E.3.2: cpb_cnt_minus1[i] is in [0, 31].
131 HEVC_MAX_CPB_CNT = 32,
133 // A.4.1: in table A.6 the highest level allows a MaxLumaPs of 35 651 584.
134 HEVC_MAX_LUMA_PS = 35651584,
135 // A.4.1: pic_width_in_luma_samples and pic_height_in_luma_samples are
136 // constrained to be not greater than sqrt(MaxLumaPs * 8). Hence height/
137 // width are bounded above by sqrt(8 * 35651584) = 16888.2 samples.
138 HEVC_MAX_WIDTH = 16888,
139 HEVC_MAX_HEIGHT = 16888,
141 // A.4.1: table A.6 allows at most 22 tile rows for any level.
142 HEVC_MAX_TILE_ROWS = 22,
143 // A.4.1: table A.6 allows at most 20 tile columns for any level.
144 HEVC_MAX_TILE_COLUMNS = 20,
146 // A.4.2: table A.6 allows at most 600 slice segments for any level.
147 HEVC_MAX_SLICE_SEGMENTS = 600,
149 // 7.4.7.1: in the worst case (tiles_enabled_flag and
150 // entropy_coding_sync_enabled_flag are both set), entry points can be
151 // placed at the beginning of every Ctb row in every tile, giving an
152 // upper bound of (num_tile_columns_minus1 + 1) * PicHeightInCtbsY - 1.
153 // Only a stream with very high resolution and perverse parameters could
154 // get near that, though, so set a lower limit here with the maximum
155 // possible value for 4K video (at most 135 16x16 Ctb rows).
156 HEVC_MAX_ENTRY_POINT_OFFSETS = HEVC_MAX_TILE_COLUMNS * 135,
160 #endif /* AVCODEC_HEVC_H */