6 /* ======================================================================== */
7 /* ========================= LICENSING & COPYRIGHT ======================== */
8 /* ======================================================================== */
13 * A portable Motorola M680x0 processor emulation engine.
14 * Copyright Karl Stenerud. All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a copy
17 * of this software and associated documentation files (the "Software"), to deal
18 * in the Software without restriction, including without limitation the rights
19 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
20 * copies of the Software, and to permit persons to whom the Software is
21 * furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice shall be included in
24 * all copies or substantial portions of the Software.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
28 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
29 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
30 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
31 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 /* Special thanks to Bart Trzynadlowski for his insight into the
36 * undocumented features of this chip:
38 * http://dynarec.com/~bart/files/68knotes.txt
42 /* Input file for m68kmake
43 * -----------------------
45 * All sections begin with 80 X's in a row followed by an end-of-line
47 * After this, m68kmake will expect to find one of the following section
49 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
50 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
51 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
52 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
53 * M68KMAKE_TABLE_BODY - the table itself
54 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
55 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
56 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
58 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
59 * M68KMAKE_TABLE_BODY must be second last in the file.
61 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
62 * primitives themselves. Each opcode handler begins with:
63 * M68KMAKE_OP(A, B, C, D)
65 * where A is the opcode handler name, B is the size of the operation,
66 * C denotes any special processing mode, and D denotes a specific
68 * For C and D where nothing is specified, use "."
71 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
72 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
73 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
75 * All opcode handler primitives end with a closing curly brace "}" at column 1
77 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
78 * and do not put a closing curly brace at column 1 unless it is
79 * marking the end of the handler!
81 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
82 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
83 * opcode handlers to handle variations in the opcode handler.
84 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
85 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
86 * be interpreted on instructions where the corresponding table entry
87 * specifies multiple effective addressing modes.
89 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
91 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
92 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
93 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
96 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
97 M68KMAKE_PROTOTYPE_HEADER
99 #ifndef M68KOPS__HEADER
100 #define M68KOPS__HEADER
102 /* ======================================================================== */
103 /* ============================ OPCODE HANDLERS =========================== */
104 /* ======================================================================== */
108 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
109 M68KMAKE_PROTOTYPE_FOOTER
112 /* Build the opcode handler table */
113 void m68ki_build_opcode_table(void);
115 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
116 extern unsigned char m68ki_cycles[][0x10000];
119 /* ======================================================================== */
120 /* ============================== END OF FILE ============================= */
121 /* ======================================================================== */
123 #endif /* M68KOPS__HEADER */
127 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
128 M68KMAKE_TABLE_HEADER
130 /* ======================================================================== */
131 /* ========================= OPCODE TABLE BUILDER ========================= */
132 /* ======================================================================== */
137 #define NUM_CPU_TYPES 5
139 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
140 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
142 /* This is used to generate the opcode handler jump table */
145 void (*opcode_handler)(void); /* handler function */
146 unsigned int mask; /* mask on opcode */
147 unsigned int match; /* what to match after masking */
148 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
149 } opcode_handler_struct;
152 /* Opcode handler table */
153 static const opcode_handler_struct m68k_opcode_handler_table[] =
155 /* function mask match 000 010 020 040 */
159 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
160 M68KMAKE_TABLE_FOOTER
162 {0, 0, 0, {0, 0, 0, 0, 0}}
166 /* Build the opcode handler jump table */
167 void m68ki_build_opcode_table(void)
169 const opcode_handler_struct *ostruct;
176 for(i = 0; i < 0x10000; i++)
178 /* default to illegal */
179 m68ki_instruction_jump_table[i] = m68k_op_illegal;
180 for(k=0;k<NUM_CPU_TYPES;k++)
181 m68ki_cycles[k][i] = 0;
184 ostruct = m68k_opcode_handler_table;
185 while(ostruct->mask != 0xff00)
187 for(i = 0;i < 0x10000;i++)
189 if((i & ostruct->mask) == ostruct->match)
191 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
192 for(k=0;k<NUM_CPU_TYPES;k++)
193 m68ki_cycles[k][i] = ostruct->cycles[k];
198 while(ostruct->mask == 0xff00)
200 for(i = 0;i <= 0xff;i++)
202 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
203 for(k=0;k<NUM_CPU_TYPES;k++)
204 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
208 while(ostruct->mask == 0xf1f8)
214 instr = ostruct->match | (i << 9) | j;
215 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
216 for(k=0;k<NUM_CPU_TYPES;k++)
217 m68ki_cycles[k][instr] = ostruct->cycles[k];
218 // For all shift operations with known shift distance (encoded in instruction word)
219 if((instr & 0xf000) == 0xe000 && (!(instr & 0x20)))
221 // On the 68000 and 68010 shift distance affect execution time.
222 // Add the cycle cost of shifting; 2 times the shift distance
223 cycle_cost = ((((i-1)&7)+1)<<1);
224 m68ki_cycles[0][instr] += cycle_cost;
225 m68ki_cycles[1][instr] += cycle_cost;
226 // On the 68020 shift distance does not affect execution time
227 m68ki_cycles[2][instr] += 0;
233 while(ostruct->mask == 0xfff0)
235 for(i = 0;i <= 0x0f;i++)
237 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
238 for(k=0;k<NUM_CPU_TYPES;k++)
239 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
243 while(ostruct->mask == 0xf1ff)
245 for(i = 0;i <= 0x07;i++)
247 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
248 for(k=0;k<NUM_CPU_TYPES;k++)
249 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
253 while(ostruct->mask == 0xfff8)
255 for(i = 0;i <= 0x07;i++)
257 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
258 for(k=0;k<NUM_CPU_TYPES;k++)
259 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
263 while(ostruct->mask == 0xffff)
265 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
266 for(k=0;k<NUM_CPU_TYPES;k++)
267 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
273 /* ======================================================================== */
274 /* ============================== END OF FILE ============================= */
275 /* ======================================================================== */
279 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
280 M68KMAKE_OPCODE_HANDLER_HEADER
284 extern void m68040_fpu_op0(void);
285 extern void m68040_fpu_op1(void);
286 extern void m68851_mmu_ops();
287 extern void m68881_ftrap();
289 /* ======================================================================== */
290 /* ========================= INSTRUCTION HANDLERS ========================= */
291 /* ======================================================================== */
295 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
296 M68KMAKE_OPCODE_HANDLER_FOOTER
298 /* ======================================================================== */
299 /* ============================== END OF FILE ============================= */
300 /* ======================================================================== */
304 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
307 The following table is arranged as follows:
309 name: Opcode mnemonic
313 spec proc: Special processing mode:
317 rr: register to register
319 er: effective address to register
320 re: register to effective address
321 dd: data register to data register
322 da: data register to address register
323 aa: address register to address register
324 cr: control register to register
325 rc: register to control register
326 toc: to condition code register
327 tos: to status register
328 tou: to user stack pointer
329 frc: from condition code register
330 frs: from status register
331 fru: from user stack pointer
332 * for move.x, the special processing mode is a specific
333 destination effective addressing mode.
335 spec ea: Specific effective addressing mode:
340 ai: address register indirect
341 pi: address register indirect with postincrement
342 pd: address register indirect with predecrement
343 di: address register indirect with displacement
344 ix: address register indirect with index
345 aw: absolute word address
346 al: absolute long address
347 pcdi: program counter relative with displacement
348 pcix: program counter relative with index
349 a7: register specified in instruction is A7
350 ax7: register field X of instruction is A7
351 ay7: register field Y of instruction is A7
352 axy7: register fields X and Y of instruction are A7
354 bit pattern: Pattern to recognize this opcode. "." means don't care.
356 allowed ea: List of allowed addressing modes:
358 A: address register indirect
359 +: ARI (address register indirect) with postincrement
360 -: ARI with predecrement
361 D: ARI with displacement
363 W: absolute word address
364 L: absolute long address
365 d: program counter indirect with displacement
366 x: program counter indirect with index
368 mode: CPU operating mode for each cpu type. U = user or supervisor,
369 S = supervisor only, "." = opcode not present.
371 cpu cycles: Base number of cycles required to execute this opcode on the
373 Use "." if CPU does not have this opcode.
377 spec spec allowed ea mode cpu cycles
378 name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 000 010 020 030 040 comments
379 ====== ==== ==== ==== ================ ========== = = = = = === === === === === =============
381 1010 0 . . 1010............ .......... U U U U U 4 4 4 4 4
382 1111 0 . . 1111............ .......... U U U U U 4 4 4 4 4
383 040fpu0 32 . . 11110010........ .......... . . . . U . . . . 0
384 040fpu1 32 . . 11110011........ .......... . . . . U . . . . 0
385 abcd 8 rr . 1100...100000... .......... U U U U U 6 6 4 4 4
386 abcd 8 mm ax7 1100111100001... .......... U U U U U 18 18 16 16 16
387 abcd 8 mm ay7 1100...100001111 .......... U U U U U 18 18 16 16 16
388 abcd 8 mm axy7 1100111100001111 .......... U U U U U 18 18 16 16 16
389 abcd 8 mm . 1100...100001... .......... U U U U U 18 18 16 16 16
390 add 8 er d 1101...000000... .......... U U U U U 4 4 2 2 2
391 add 8 er . 1101...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
392 add 16 er d 1101...001000... .......... U U U U U 4 4 2 2 2
393 add 16 er a 1101...001001... .......... U U U U U 4 4 2 2 2
394 add 16 er . 1101...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
395 add 32 er d 1101...010000... .......... U U U U U 6 6 2 2 2
396 add 32 er a 1101...010001... .......... U U U U U 6 6 2 2 2
397 add 32 er . 1101...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
398 add 8 re . 1101...100...... A+-DXWL... U U U U U 8 8 4 4 4
399 add 16 re . 1101...101...... A+-DXWL... U U U U U 8 8 4 4 4
400 add 32 re . 1101...110...... A+-DXWL... U U U U U 12 12 4 4 4
401 adda 16 . d 1101...011000... .......... U U U U U 8 8 2 2 2
402 adda 16 . a 1101...011001... .......... U U U U U 8 8 2 2 2
403 adda 16 . . 1101...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
404 adda 32 . d 1101...111000... .......... U U U U U 6 6 2 2 2
405 adda 32 . a 1101...111001... .......... U U U U U 6 6 2 2 2
406 adda 32 . . 1101...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
407 addi 8 . d 0000011000000... .......... U U U U U 8 8 2 2 2
408 addi 8 . . 0000011000...... A+-DXWL... U U U U U 12 12 4 4 4
409 addi 16 . d 0000011001000... .......... U U U U U 8 8 2 2 2
410 addi 16 . . 0000011001...... A+-DXWL... U U U U U 12 12 4 4 4
411 addi 32 . d 0000011010000... .......... U U U U U 16 14 2 2 2
412 addi 32 . . 0000011010...... A+-DXWL... U U U U U 20 20 4 4 4
413 addq 8 . d 0101...000000... .......... U U U U U 4 4 2 2 2
414 addq 8 . . 0101...000...... A+-DXWL... U U U U U 8 8 4 4 4
415 addq 16 . d 0101...001000... .......... U U U U U 4 4 2 2 2
416 addq 16 . a 0101...001001... .......... U U U U U 4 4 2 2 2
417 addq 16 . . 0101...001...... A+-DXWL... U U U U U 8 8 4 4 4
418 addq 32 . d 0101...010000... .......... U U U U U 8 8 2 2 2
419 addq 32 . a 0101...010001... .......... U U U U U 8 8 2 2 2
420 addq 32 . . 0101...010...... A+-DXWL... U U U U U 12 12 4 4 4
421 addx 8 rr . 1101...100000... .......... U U U U U 4 4 2 2 2
422 addx 16 rr . 1101...101000... .......... U U U U U 4 4 2 2 2
423 addx 32 rr . 1101...110000... .......... U U U U U 8 6 2 2 2
424 addx 8 mm ax7 1101111100001... .......... U U U U U 18 18 12 12 12
425 addx 8 mm ay7 1101...100001111 .......... U U U U U 18 18 12 12 12
426 addx 8 mm axy7 1101111100001111 .......... U U U U U 18 18 12 12 12
427 addx 8 mm . 1101...100001... .......... U U U U U 18 18 12 12 12
428 addx 16 mm . 1101...101001... .......... U U U U U 18 18 12 12 12
429 addx 32 mm . 1101...110001... .......... U U U U U 30 30 12 12 12
430 and 8 er d 1100...000000... .......... U U U U U 4 4 2 2 2
431 and 8 er . 1100...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
432 and 16 er d 1100...001000... .......... U U U U U 4 4 2 2 2
433 and 16 er . 1100...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
434 and 32 er d 1100...010000... .......... U U U U U 6 6 2 2 2
435 and 32 er . 1100...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
436 and 8 re . 1100...100...... A+-DXWL... U U U U U 8 8 4 4 4
437 and 16 re . 1100...101...... A+-DXWL... U U U U U 8 8 4 4 4
438 and 32 re . 1100...110...... A+-DXWL... U U U U U 12 12 4 4 4
439 andi 16 toc . 0000001000111100 .......... U U U U U 20 16 12 12 12
440 andi 16 tos . 0000001001111100 .......... S S S S S 20 16 12 12 12
441 andi 8 . d 0000001000000... .......... U U U U U 8 8 2 2 2
442 andi 8 . . 0000001000...... A+-DXWL... U U U U U 12 12 4 4 4
443 andi 16 . d 0000001001000... .......... U U U U U 8 8 2 2 2
444 andi 16 . . 0000001001...... A+-DXWL... U U U U U 12 12 4 4 4
445 andi 32 . d 0000001010000... .......... U U U U U 14 14 2 2 2
446 andi 32 . . 0000001010...... A+-DXWL... U U U U U 20 20 4 4 4
447 asr 8 s . 1110...000000... .......... U U U U U 6 6 6 6 6
448 asr 16 s . 1110...001000... .......... U U U U U 6 6 6 6 6
449 asr 32 s . 1110...010000... .......... U U U U U 8 8 6 6 6
450 asr 8 r . 1110...000100... .......... U U U U U 6 6 6 6 6
451 asr 16 r . 1110...001100... .......... U U U U U 6 6 6 6 6
452 asr 32 r . 1110...010100... .......... U U U U U 8 8 6 6 6
453 asr 16 . . 1110000011...... A+-DXWL... U U U U U 8 8 5 5 5
454 asl 8 s . 1110...100000... .......... U U U U U 6 6 8 8 8
455 asl 16 s . 1110...101000... .......... U U U U U 6 6 8 8 8
456 asl 32 s . 1110...110000... .......... U U U U U 8 8 8 8 8
457 asl 8 r . 1110...100100... .......... U U U U U 6 6 8 8 8
458 asl 16 r . 1110...101100... .......... U U U U U 6 6 8 8 8
459 asl 32 r . 1110...110100... .......... U U U U U 8 8 8 8 8
460 asl 16 . . 1110000111...... A+-DXWL... U U U U U 8 8 6 6 6
461 bcc 8 . . 0110............ .......... U U U U U 10 10 6 6 6
462 bcc 16 . . 0110....00000000 .......... U U U U U 10 10 6 6 6
463 bcc 32 . . 0110....11111111 .......... U U U U U 10 10 6 6 6
464 bchg 8 r . 0000...101...... A+-DXWL... U U U U U 8 8 4 4 4
465 bchg 32 r d 0000...101000... .......... U U U U U 8 8 4 4 4
466 bchg 8 s . 0000100001...... A+-DXWL... U U U U U 12 12 4 4 4
467 bchg 32 s d 0000100001000... .......... U U U U U 12 12 4 4 4
468 bclr 8 r . 0000...110...... A+-DXWL... U U U U U 8 10 4 4 4
469 bclr 32 r d 0000...110000... .......... U U U U U 10 10 4 4 4
470 bclr 8 s . 0000100010...... A+-DXWL... U U U U U 12 12 4 4 4
471 bclr 32 s d 0000100010000... .......... U U U U U 14 14 4 4 4
472 bfchg 32 . d 1110101011000... .......... . . U U U . . 12 12 12 timing not quite correct
473 bfchg 32 . . 1110101011...... A..DXWL... . . U U U . . 20 20 20
474 bfclr 32 . d 1110110011000... .......... . . U U U . . 12 12 12
475 bfclr 32 . . 1110110011...... A..DXWL... . . U U U . . 20 20 20
476 bfexts 32 . d 1110101111000... .......... . . U U U . . 8 8 8
477 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U . . 15 15 15
478 bfextu 32 . d 1110100111000... .......... . . U U U . . 8 8 8
479 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U . . 15 15 15
480 bfffo 32 . d 1110110111000... .......... . . U U U . . 18 18 18
481 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U . . 28 28 28
482 bfins 32 . d 1110111111000... .......... . . U U U . . 10 10 10
483 bfins 32 . . 1110111111...... A..DXWL... . . U U U . . 17 17 17
484 bfset 32 . d 1110111011000... .......... . . U U U . . 12 12 12
485 bfset 32 . . 1110111011...... A..DXWL... . . U U U . . 20 20 20
486 bftst 32 . d 1110100011000... .......... . . U U U . . 6 6 6
487 bftst 32 . . 1110100011...... A..DXWLdx. . . U U U . . 13 13 13
488 bkpt 0 . . 0100100001001... .......... . U U U U . 10 10 10 10
489 bra 8 . . 01100000........ .......... U U U U U 10 10 10 10 10
490 bra 16 . . 0110000000000000 .......... U U U U U 10 10 10 10 10
491 bra 32 . . 0110000011111111 .......... U U U U U 10 10 10 10 10
492 bset 32 r d 0000...111000... .......... U U U U U 8 8 4 4 4
493 bset 8 r . 0000...111...... A+-DXWL... U U U U U 8 8 4 4 4
494 bset 8 s . 0000100011...... A+-DXWL... U U U U U 12 12 4 4 4
495 bset 32 s d 0000100011000... .......... U U U U U 12 12 4 4 4
496 bsr 8 . . 01100001........ .......... U U U U U 18 18 7 7 7
497 bsr 16 . . 0110000100000000 .......... U U U U U 18 18 7 7 7
498 bsr 32 . . 0110000111111111 .......... U U U U U 18 18 7 7 7
499 btst 8 r . 0000...100...... A+-DXWLdxI U U U U U 4 4 4 4 4
500 btst 32 r d 0000...100000... .......... U U U U U 6 6 4 4 4
501 btst 8 s . 0000100000...... A+-DXWLdx. U U U U U 8 8 4 4 4
502 btst 32 s d 0000100000000... .......... U U U U U 10 10 4 4 4
503 callm 32 . . 0000011011...... A..DXWLdx. . . U U U . . 60 60 60 not properly emulated
504 cas 8 . . 0000101011...... A+-DXWL... . . U U U . . 12 12 12
505 cas 16 . . 0000110011...... A+-DXWL... . . U U U . . 12 12 12
506 cas 32 . . 0000111011...... A+-DXWL... . . U U U . . 12 12 12
507 cas2 16 . . 0000110011111100 .......... . . U U U . . 12 12 12
508 cas2 32 . . 0000111011111100 .......... . . U U U . . 12 12 12
509 chk 16 . d 0100...110000... .......... U U U U U 10 8 8 8 8
510 chk 16 . . 0100...110...... A+-DXWLdxI U U U U U 10 8 8 8 8
511 chk 32 . d 0100...100000... .......... . . U U U . . 8 8 8
512 chk 32 . . 0100...100...... A+-DXWLdxI . . U U U . . 8 8 8
513 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U . . 23 23 23
514 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U . . 23 23 23
515 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U . . 18 18 18
516 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U . . 23 23 23
517 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U . . 23 23 23
518 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U . . 18 18 18
519 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U . . 23 23 23
520 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U . . 23 23 23
521 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U . . 18 18 18
522 clr 8 . d 0100001000000... .......... U U U U U 4 4 2 2 2
523 clr 8 . . 0100001000...... A+-DXWL... U U U U U 8 4 4 4 4
524 clr 16 . d 0100001001000... .......... U U U U U 4 4 2 2 2
525 clr 16 . . 0100001001...... A+-DXWL... U U U U U 8 4 4 4 4
526 clr 32 . d 0100001010000... .......... U U U U U 6 6 2 2 2
527 clr 32 . . 0100001010...... A+-DXWL... U U U U U 12 6 4 4 4
528 cmp 8 . d 1011...000000... .......... U U U U U 4 4 2 2 2
529 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
530 cmp 16 . d 1011...001000... .......... U U U U U 4 4 2 2 2
531 cmp 16 . a 1011...001001... .......... U U U U U 4 4 2 2 2
532 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
533 cmp 32 . d 1011...010000... .......... U U U U U 6 6 2 2 2
534 cmp 32 . a 1011...010001... .......... U U U U U 6 6 2 2 2
535 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
536 cmpa 16 . d 1011...011000... .......... U U U U U 6 6 4 4 4
537 cmpa 16 . a 1011...011001... .......... U U U U U 6 6 4 4 4
538 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U 6 6 4 4 4
539 cmpa 32 . d 1011...111000... .......... U U U U U 6 6 4 4 4
540 cmpa 32 . a 1011...111001... .......... U U U U U 6 6 4 4 4
541 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U 6 6 4 4 4
542 cmpi 8 . d 0000110000000... .......... U U U U U 8 8 2 2 2
543 cmpi 8 . . 0000110000...... A+-DXWL... U U U U U 8 8 2 2 2
544 cmpi 8 . pcdi 0000110000111010 .......... . . U U U . . 7 7 7
545 cmpi 8 . pcix 0000110000111011 .......... . . U U U . . 9 9 9
546 cmpi 16 . d 0000110001000... .......... U U U U U 8 8 2 2 2
547 cmpi 16 . . 0000110001...... A+-DXWL... U U U U U 8 8 2 2 2
548 cmpi 16 . pcdi 0000110001111010 .......... . . U U U . . 7 7 7
549 cmpi 16 . pcix 0000110001111011 .......... . . U U U . . 9 9 9
550 cmpi 32 . d 0000110010000... .......... U U U U U 14 12 2 2 2
551 cmpi 32 . . 0000110010...... A+-DXWL... U U U U U 12 12 2 2 2
552 cmpi 32 . pcdi 0000110010111010 .......... . . U U U . . 7 7 7
553 cmpi 32 . pcix 0000110010111011 .......... . . U U U . . 9 9 9
554 cmpm 8 . ax7 1011111100001... .......... U U U U U 12 12 9 9 9
555 cmpm 8 . ay7 1011...100001111 .......... U U U U U 12 12 9 9 9
556 cmpm 8 . axy7 1011111100001111 .......... U U U U U 12 12 9 9 9
557 cmpm 8 . . 1011...100001... .......... U U U U U 12 12 9 9 9
558 cmpm 16 . . 1011...101001... .......... U U U U U 12 12 9 9 9
559 cmpm 32 . . 1011...110001... .......... U U U U U 20 20 9 9 9
560 cpbcc 32 . . 1111...01....... .......... . . U U . . . 4 4 . unemulated
561 cpdbcc 32 . . 1111...001001... .......... . . U U . . . 4 4 . unemulated
562 cpgen 32 . . 1111...000...... .......... . . U U . . . 4 4 . unemulated
563 cpscc 32 . . 1111...001...... .......... . . U U . . . 4 4 . unemulated
564 cptrapcc 32 . . 1111...001111... .......... . . U U . . . 4 4 . unemulated
565 ftrapcc 32 . . 1111001001111... .......... . . U U . . . 4 4 .
566 dbt 16 . . 0101000011001... .......... U U U U U 12 12 6 6 6
567 dbf 16 . . 0101000111001... .......... U U U U U 12 12 6 6 6
568 dbcc 16 . . 0101....11001... .......... U U U U U 12 12 6 6 6
569 divs 16 . d 1000...111000... .......... U U U U U 158 122 56 56 56
570 divs 16 . . 1000...111...... A+-DXWLdxI U U U U U 158 122 56 56 56
571 divu 16 . d 1000...011000... .......... U U U U U 140 108 44 44 44
572 divu 16 . . 1000...011...... A+-DXWLdxI U U U U U 140 108 44 44 44
573 divl 32 . d 0100110001000... .......... . . U U U . . 84 84 84
574 divl 32 . . 0100110001...... A+-DXWLdxI . . U U U . . 84 84 84
575 eor 8 . d 1011...100000... .......... U U U U U 4 4 2 2 2
576 eor 8 . . 1011...100...... A+-DXWL... U U U U U 8 8 4 4 4
577 eor 16 . d 1011...101000... .......... U U U U U 4 4 2 2 2
578 eor 16 . . 1011...101...... A+-DXWL... U U U U U 8 8 4 4 4
579 eor 32 . d 1011...110000... .......... U U U U U 8 6 2 2 2
580 eor 32 . . 1011...110...... A+-DXWL... U U U U U 12 12 4 4 4
581 eori 16 toc . 0000101000111100 .......... U U U U U 20 16 12 12 12
582 eori 16 tos . 0000101001111100 .......... S S S S S 20 16 12 12 12
583 eori 8 . d 0000101000000... .......... U U U U U 8 8 2 2 2
584 eori 8 . . 0000101000...... A+-DXWL... U U U U U 12 12 4 4 4
585 eori 16 . d 0000101001000... .......... U U U U U 8 8 2 2 2
586 eori 16 . . 0000101001...... A+-DXWL... U U U U U 12 12 4 4 4
587 eori 32 . d 0000101010000... .......... U U U U U 16 14 2 2 2
588 eori 32 . . 0000101010...... A+-DXWL... U U U U U 20 20 4 4 4
589 exg 32 dd . 1100...101000... .......... U U U U U 6 6 2 2 2
590 exg 32 aa . 1100...101001... .......... U U U U U 6 6 2 2 2
591 exg 32 da . 1100...110001... .......... U U U U U 6 6 2 2 2
592 ext 16 . . 0100100010000... .......... U U U U U 4 4 4 4 4
593 ext 32 . . 0100100011000... .......... U U U U U 4 4 4 4 4
594 extb 32 . . 0100100111000... .......... . . U U U . . 4 4 4
595 illegal 0 . . 0100101011111100 .......... U U U U U 4 4 4 4 4
596 jmp 32 . . 0100111011...... A..DXWLdx. U U U U U 4 4 0 0 0
597 jsr 32 . . 0100111010...... A..DXWLdx. U U U U U 12 12 0 0 0
598 lea 32 . . 0100...111...... A..DXWLdx. U U U U U 0 0 2 2 2
599 link 16 . a7 0100111001010111 .......... U U U U U 16 16 5 5 5
600 link 16 . . 0100111001010... .......... U U U U U 16 16 5 5 5
601 link 32 . a7 0100100000001111 .......... . . U U U . . 6 6 6
602 link 32 . . 0100100000001... .......... . . U U U . . 6 6 6
603 lsr 8 s . 1110...000001... .......... U U U U U 6 6 4 4 4
604 lsr 16 s . 1110...001001... .......... U U U U U 6 6 4 4 4
605 lsr 32 s . 1110...010001... .......... U U U U U 8 8 4 4 4
606 lsr 8 r . 1110...000101... .......... U U U U U 6 6 6 6 6
607 lsr 16 r . 1110...001101... .......... U U U U U 6 6 6 6 6
608 lsr 32 r . 1110...010101... .......... U U U U U 8 8 6 6 6
609 lsr 16 . . 1110001011...... A+-DXWL... U U U U U 8 8 5 5 5
610 lsl 8 s . 1110...100001... .......... U U U U U 6 6 4 4 4
611 lsl 16 s . 1110...101001... .......... U U U U U 6 6 4 4 4
612 lsl 32 s . 1110...110001... .......... U U U U U 8 8 4 4 4
613 lsl 8 r . 1110...100101... .......... U U U U U 6 6 6 6 6
614 lsl 16 r . 1110...101101... .......... U U U U U 6 6 6 6 6
615 lsl 32 r . 1110...110101... .......... U U U U U 8 8 6 6 6
616 lsl 16 . . 1110001111...... A+-DXWL... U U U U U 8 8 5 5 5
617 move 8 d d 0001...000000... .......... U U U U U 4 4 2 2 2
618 move 8 d . 0001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
619 move 8 ai d 0001...010000... .......... U U U U U 8 8 4 4 4
620 move 8 ai . 0001...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
621 move 8 pi d 0001...011000... .......... U U U U U 8 8 4 4 4
622 move 8 pi . 0001...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
623 move 8 pi7 d 0001111011000... .......... U U U U U 8 8 4 4 4
624 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U 8 8 4 4 4
625 move 8 pd d 0001...100000... .......... U U U U U 8 8 5 5 5
626 move 8 pd . 0001...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
627 move 8 pd7 d 0001111100000... .......... U U U U U 8 8 5 5 5
628 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U 8 8 5 5 5
629 move 8 di d 0001...101000... .......... U U U U U 12 12 5 5 5
630 move 8 di . 0001...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
631 move 8 ix d 0001...110000... .......... U U U U U 14 14 7 7 7
632 move 8 ix . 0001...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
633 move 8 aw d 0001000111000... .......... U U U U U 12 12 4 4 4
634 move 8 aw . 0001000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
635 move 8 al d 0001001111000... .......... U U U U U 16 16 6 6 6
636 move 8 al . 0001001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
637 move 16 d d 0011...000000... .......... U U U U U 4 4 2 2 2
638 move 16 d a 0011...000001... .......... U U U U U 4 4 2 2 2
639 move 16 d . 0011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
640 move 16 ai d 0011...010000... .......... U U U U U 8 8 4 4 4
641 move 16 ai a 0011...010001... .......... U U U U U 8 8 4 4 4
642 move 16 ai . 0011...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
643 move 16 pi d 0011...011000... .......... U U U U U 8 8 4 4 4
644 move 16 pi a 0011...011001... .......... U U U U U 8 8 4 4 4
645 move 16 pi . 0011...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
646 move 16 pd d 0011...100000... .......... U U U U U 8 8 5 5 5
647 move 16 pd a 0011...100001... .......... U U U U U 8 8 5 5 5
648 move 16 pd . 0011...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
649 move 16 di d 0011...101000... .......... U U U U U 12 12 5 5 5
650 move 16 di a 0011...101001... .......... U U U U U 12 12 5 5 5
651 move 16 di . 0011...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
652 move 16 ix d 0011...110000... .......... U U U U U 14 14 7 7 7
653 move 16 ix a 0011...110001... .......... U U U U U 14 14 7 7 7
654 move 16 ix . 0011...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
655 move 16 aw d 0011000111000... .......... U U U U U 12 12 4 4 4
656 move 16 aw a 0011000111001... .......... U U U U U 12 12 4 4 4
657 move 16 aw . 0011000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
658 move 16 al d 0011001111000... .......... U U U U U 16 16 6 6 6
659 move 16 al a 0011001111001... .......... U U U U U 16 16 6 6 6
660 move 16 al . 0011001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
661 move 32 d d 0010...000000... .......... U U U U U 4 4 2 2 2
662 move 32 d a 0010...000001... .......... U U U U U 4 4 2 2 2
663 move 32 d . 0010...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
664 move 32 ai d 0010...010000... .......... U U U U U 12 12 4 4 4
665 move 32 ai a 0010...010001... .......... U U U U U 12 12 4 4 4
666 move 32 ai . 0010...010...... A+-DXWLdxI U U U U U 12 12 4 4 4
667 move 32 pi d 0010...011000... .......... U U U U U 12 12 4 4 4
668 move 32 pi a 0010...011001... .......... U U U U U 12 12 4 4 4
669 move 32 pi . 0010...011...... A+-DXWLdxI U U U U U 12 12 4 4 4
670 move 32 pd d 0010...100000... .......... U U U U U 12 14 5 5 5
671 move 32 pd a 0010...100001... .......... U U U U U 12 14 5 5 5
672 move 32 pd . 0010...100...... A+-DXWLdxI U U U U U 12 14 5 5 5
673 move 32 di d 0010...101000... .......... U U U U U 16 16 5 5 5
674 move 32 di a 0010...101001... .......... U U U U U 16 16 5 5 5
675 move 32 di . 0010...101...... A+-DXWLdxI U U U U U 16 16 5 5 5
676 move 32 ix d 0010...110000... .......... U U U U U 18 18 7 7 7
677 move 32 ix a 0010...110001... .......... U U U U U 18 18 7 7 7
678 move 32 ix . 0010...110...... A+-DXWLdxI U U U U U 18 18 7 7 7
679 move 32 aw d 0010000111000... .......... U U U U U 16 16 4 4 4
680 move 32 aw a 0010000111001... .......... U U U U U 16 16 4 4 4
681 move 32 aw . 0010000111...... A+-DXWLdxI U U U U U 16 16 4 4 4
682 move 32 al d 0010001111000... .......... U U U U U 20 20 6 6 6
683 move 32 al a 0010001111001... .......... U U U U U 20 20 6 6 6
684 move 32 al . 0010001111...... A+-DXWLdxI U U U U U 20 20 6 6 6
685 movea 16 . d 0011...001000... .......... U U U U U 4 4 2 2 2
686 movea 16 . a 0011...001001... .......... U U U U U 4 4 2 2 2
687 movea 16 . . 0011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
688 movea 32 . d 0010...001000... .......... U U U U U 4 4 2 2 2
689 movea 32 . a 0010...001001... .......... U U U U U 4 4 2 2 2
690 movea 32 . . 0010...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
691 move 16 frc d 0100001011000... .......... . U U U U . 4 4 4 4
692 move 16 frc . 0100001011...... A+-DXWL... . U U U U . 8 4 4 4
693 move 16 toc d 0100010011000... .......... U U U U U 12 12 4 4 4
694 move 16 toc . 0100010011...... A+-DXWLdxI U U U U U 12 12 4 4 4
695 move 16 frs d 0100000011000... .......... U S S S S 6 4 8 8 8 U only for 000
696 move 16 frs . 0100000011...... A+-DXWL... U S S S S 8 8 8 8 8 U only for 000
697 move 16 tos d 0100011011000... .......... S S S S S 12 12 8 8 8
698 move 16 tos . 0100011011...... A+-DXWLdxI S S S S S 12 12 8 8 8
699 move 32 fru . 0100111001101... .......... S S S S S 4 6 2 2 2
700 move 32 tou . 0100111001100... .......... S S S S S 4 6 2 2 2
701 movec 32 cr . 0100111001111010 .......... . S S S S . 12 6 6 6
702 movec 32 rc . 0100111001111011 .......... . S S S S . 10 12 12 12
703 movem 16 re pd 0100100010100... .......... U U U U U 8 8 4 4 4
704 movem 16 re . 0100100010...... A..DXWL... U U U U U 8 8 4 4 4
705 movem 32 re pd 0100100011100... .......... U U U U U 8 8 4 4 4
706 movem 32 re . 0100100011...... A..DXWL... U U U U U 8 8 4 4 4
707 movem 16 er pi 0100110010011... .......... U U U U U 12 12 8 8 8
708 movem 16 er pcdi 0100110010111010 .......... U U U U U 16 16 9 9 9
709 movem 16 er pcix 0100110010111011 .......... U U U U U 18 18 11 11 11
710 movem 16 er . 0100110010...... A..DXWL... U U U U U 12 12 8 8 8
711 movem 32 er pi 0100110011011... .......... U U U U U 12 12 8 8 8
712 movem 32 er pcdi 0100110011111010 .......... U U U U U 16 16 9 9 9
713 movem 32 er pcix 0100110011111011 .......... U U U U U 18 18 11 11 11
714 movem 32 er . 0100110011...... A..DXWL... U U U U U 12 12 8 8 8
715 movep 16 er . 0000...100001... .......... U U U U U 16 16 12 12 12
716 movep 32 er . 0000...101001... .......... U U U U U 24 24 18 18 18
717 movep 16 re . 0000...110001... .......... U U U U U 16 16 11 11 11
718 movep 32 re . 0000...111001... .......... U U U U U 24 24 17 17 17
719 moveq 32 . . 0111...0........ .......... U U U U U 4 4 2 2 2
720 moves 8 . . 0000111000...... A+-DXWL... . S S S S . 14 5 5 5
721 moves 16 . . 0000111001...... A+-DXWL... . S S S S . 14 5 5 5
722 moves 32 . . 0000111010...... A+-DXWL... . S S S S . 16 5 5 5
723 move16 32 . . 1111011000100... .......... . . . . U . . . . 4 TODO: correct timing
724 muls 16 . d 1100...111000... .......... U U U U U 54 32 27 27 27
725 muls 16 . . 1100...111...... A+-DXWLdxI U U U U U 54 32 27 27 27
726 mulu 16 . d 1100...011000... .......... U U U U U 54 30 27 27 27
727 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U 54 30 27 27 27
728 mull 32 . d 0100110000000... .......... . . U U U . . 43 43 43
729 mull 32 . . 0100110000...... A+-DXWLdxI . . U U U . . 43 43 43
730 nbcd 8 . d 0100100000000... .......... U U U U U 6 6 6 6 6
731 nbcd 8 . . 0100100000...... A+-DXWL... U U U U U 8 8 6 6 6
732 neg 8 . d 0100010000000... .......... U U U U U 4 4 2 2 2
733 neg 8 . . 0100010000...... A+-DXWL... U U U U U 8 8 4 4 4
734 neg 16 . d 0100010001000... .......... U U U U U 4 4 2 2 2
735 neg 16 . . 0100010001...... A+-DXWL... U U U U U 8 8 4 4 4
736 neg 32 . d 0100010010000... .......... U U U U U 6 6 2 2 2
737 neg 32 . . 0100010010...... A+-DXWL... U U U U U 12 12 4 4 4
738 negx 8 . d 0100000000000... .......... U U U U U 4 4 2 2 2
739 negx 8 . . 0100000000...... A+-DXWL... U U U U U 8 8 4 4 4
740 negx 16 . d 0100000001000... .......... U U U U U 4 4 2 2 2
741 negx 16 . . 0100000001...... A+-DXWL... U U U U U 8 8 4 4 4
742 negx 32 . d 0100000010000... .......... U U U U U 6 6 2 2 2
743 negx 32 . . 0100000010...... A+-DXWL... U U U U U 12 12 4 4 4
744 nop 0 . . 0100111001110001 .......... U U U U U 4 4 2 2 2
745 not 8 . d 0100011000000... .......... U U U U U 4 4 2 2 2
746 not 8 . . 0100011000...... A+-DXWL... U U U U U 8 8 4 4 4
747 not 16 . d 0100011001000... .......... U U U U U 4 4 2 2 2
748 not 16 . . 0100011001...... A+-DXWL... U U U U U 8 8 4 4 4
749 not 32 . d 0100011010000... .......... U U U U U 6 6 2 2 2
750 not 32 . . 0100011010...... A+-DXWL... U U U U U 12 12 4 4 4
751 or 8 er d 1000...000000... .......... U U U U U 4 4 2 2 2
752 or 8 er . 1000...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
753 or 16 er d 1000...001000... .......... U U U U U 4 4 2 2 2
754 or 16 er . 1000...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
755 or 32 er d 1000...010000... .......... U U U U U 6 6 2 2 2
756 or 32 er . 1000...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
757 or 8 re . 1000...100...... A+-DXWL... U U U U U 8 8 4 4 4
758 or 16 re . 1000...101...... A+-DXWL... U U U U U 8 8 4 4 4
759 or 32 re . 1000...110...... A+-DXWL... U U U U U 12 12 4 4 4
760 ori 16 toc . 0000000000111100 .......... U U U U U 20 16 12 12 12
761 ori 16 tos . 0000000001111100 .......... S S S S S 20 16 12 12 12
762 ori 8 . d 0000000000000... .......... U U U U U 8 8 2 2 2
763 ori 8 . . 0000000000...... A+-DXWL... U U U U U 12 12 4 4 4
764 ori 16 . d 0000000001000... .......... U U U U U 8 8 2 2 2
765 ori 16 . . 0000000001...... A+-DXWL... U U U U U 12 12 4 4 4
766 ori 32 . d 0000000010000... .......... U U U U U 16 14 2 2 2
767 ori 32 . . 0000000010...... A+-DXWL... U U U U U 20 20 4 4 4
768 pack 16 rr . 1000...101000... .......... . . U U U . . 6 6 6
769 pack 16 mm ax7 1000111101001... .......... . . U U U . . 13 13 13
770 pack 16 mm ay7 1000...101001111 .......... . . U U U . . 13 13 13
771 pack 16 mm axy7 1000111101001111 .......... . . U U U . . 13 13 13
772 pack 16 mm . 1000...101001... .......... . . U U U . . 13 13 13
773 pea 32 . . 0100100001...... A..DXWLdx. U U U U U 6 6 5 5 5
774 pflusha 32 . . 1111010100011... .......... . . . . S . . . . 4 TODO: correct timing
775 pflushan 32 . . 1111010100010... .......... . . . . S . . . . 4 TODO: correct timing
776 pmmu 32 . . 1111000......... .......... . . S S S . . 8 8 8
777 reset 0 . . 0100111001110000 .......... S S S S S 0 0 0 0 0
778 ror 8 s . 1110...000011... .......... U U U U U 6 6 8 8 8
779 ror 16 s . 1110...001011... .......... U U U U U 6 6 8 8 8
780 ror 32 s . 1110...010011... .......... U U U U U 8 8 8 8 8
781 ror 8 r . 1110...000111... .......... U U U U U 6 6 8 8 8
782 ror 16 r . 1110...001111... .......... U U U U U 6 6 8 8 8
783 ror 32 r . 1110...010111... .......... U U U U U 8 8 8 8 8
784 ror 16 . . 1110011011...... A+-DXWL... U U U U U 8 8 7 7 7
785 rol 8 s . 1110...100011... .......... U U U U U 6 6 8 8 8
786 rol 16 s . 1110...101011... .......... U U U U U 6 6 8 8 8
787 rol 32 s . 1110...110011... .......... U U U U U 8 8 8 8 8
788 rol 8 r . 1110...100111... .......... U U U U U 6 6 8 8 8
789 rol 16 r . 1110...101111... .......... U U U U U 6 6 8 8 8
790 rol 32 r . 1110...110111... .......... U U U U U 8 8 8 8 8
791 rol 16 . . 1110011111...... A+-DXWL... U U U U U 8 8 7 7 7
792 roxr 8 s . 1110...000010... .......... U U U U U 6 6 12 12 12
793 roxr 16 s . 1110...001010... .......... U U U U U 6 6 12 12 12
794 roxr 32 s . 1110...010010... .......... U U U U U 8 8 12 12 12
795 roxr 8 r . 1110...000110... .......... U U U U U 6 6 12 12 12
796 roxr 16 r . 1110...001110... .......... U U U U U 6 6 12 12 12
797 roxr 32 r . 1110...010110... .......... U U U U U 8 8 12 12 12
798 roxr 16 . . 1110010011...... A+-DXWL... U U U U U 8 8 5 5 5
799 roxl 8 s . 1110...100010... .......... U U U U U 6 6 12 12 12
800 roxl 16 s . 1110...101010... .......... U U U U U 6 6 12 12 12
801 roxl 32 s . 1110...110010... .......... U U U U U 8 8 12 12 12
802 roxl 8 r . 1110...100110... .......... U U U U U 6 6 12 12 12
803 roxl 16 r . 1110...101110... .......... U U U U U 6 6 12 12 12
804 roxl 32 r . 1110...110110... .......... U U U U U 8 8 12 12 12
805 roxl 16 . . 1110010111...... A+-DXWL... U U U U U 8 8 5 5 5
806 rtd 32 . . 0100111001110100 .......... . U U U U . 16 10 10 10
807 rte 32 . . 0100111001110011 .......... S S S S S 20 24 20 20 20 bus fault not emulated
808 rtm 32 . . 000001101100.... .......... . . U U U . . 19 19 19 not properly emulated
809 rtr 32 . . 0100111001110111 .......... U U U U U 20 20 14 14 14
810 rts 32 . . 0100111001110101 .......... U U U U U 16 16 10 10 10
811 sbcd 8 rr . 1000...100000... .......... U U U U U 6 6 4 4 4
812 sbcd 8 mm ax7 1000111100001... .......... U U U U U 18 18 16 16 16
813 sbcd 8 mm ay7 1000...100001111 .......... U U U U U 18 18 16 16 16
814 sbcd 8 mm axy7 1000111100001111 .......... U U U U U 18 18 16 16 16
815 sbcd 8 mm . 1000...100001... .......... U U U U U 18 18 16 16 16
816 st 8 . d 0101000011000... .......... U U U U U 6 4 4 4 4
817 st 8 . . 0101000011...... A+-DXWL... U U U U U 8 8 6 6 6
818 sf 8 . d 0101000111000... .......... U U U U U 4 4 4 4 4
819 sf 8 . . 0101000111...... A+-DXWL... U U U U U 8 8 6 6 6
820 scc 8 . d 0101....11000... .......... U U U U U 4 4 4 4 4
821 scc 8 . . 0101....11...... A+-DXWL... U U U U U 8 8 6 6 6
822 stop 0 . . 0100111001110010 .......... S S S S S 4 4 8 8 8
823 sub 8 er d 1001...000000... .......... U U U U U 4 4 2 2 2
824 sub 8 er . 1001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
825 sub 16 er d 1001...001000... .......... U U U U U 4 4 2 2 2
826 sub 16 er a 1001...001001... .......... U U U U U 4 4 2 2 2
827 sub 16 er . 1001...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
828 sub 32 er d 1001...010000... .......... U U U U U 6 6 2 2 2
829 sub 32 er a 1001...010001... .......... U U U U U 6 6 2 2 2
830 sub 32 er . 1001...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
831 sub 8 re . 1001...100...... A+-DXWL... U U U U U 8 8 4 4 4
832 sub 16 re . 1001...101...... A+-DXWL... U U U U U 8 8 4 4 4
833 sub 32 re . 1001...110...... A+-DXWL... U U U U U 12 12 4 4 4
834 suba 16 . d 1001...011000... .......... U U U U U 8 8 2 2 2
835 suba 16 . a 1001...011001... .......... U U U U U 8 8 2 2 2
836 suba 16 . . 1001...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
837 suba 32 . d 1001...111000... .......... U U U U U 6 6 2 2 2
838 suba 32 . a 1001...111001... .......... U U U U U 6 6 2 2 2
839 suba 32 . . 1001...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
840 subi 8 . d 0000010000000... .......... U U U U U 8 8 2 2 2
841 subi 8 . . 0000010000...... A+-DXWL... U U U U U 12 12 4 4 4
842 subi 16 . d 0000010001000... .......... U U U U U 8 8 2 2 2
843 subi 16 . . 0000010001...... A+-DXWL... U U U U U 12 12 4 4 4
844 subi 32 . d 0000010010000... .......... U U U U U 16 14 2 2 2
845 subi 32 . . 0000010010...... A+-DXWL... U U U U U 20 20 4 4 4
846 subq 8 . d 0101...100000... .......... U U U U U 4 4 2 2 2
847 subq 8 . . 0101...100...... A+-DXWL... U U U U U 8 8 4 4 4
848 subq 16 . d 0101...101000... .......... U U U U U 4 4 2 2 2
849 subq 16 . a 0101...101001... .......... U U U U U 8 4 2 2 2
850 subq 16 . . 0101...101...... A+-DXWL... U U U U U 8 8 4 4 4
851 subq 32 . d 0101...110000... .......... U U U U U 8 8 2 2 2
852 subq 32 . a 0101...110001... .......... U U U U U 8 8 2 2 2
853 subq 32 . . 0101...110...... A+-DXWL... U U U U U 12 12 4 4 4
854 subx 8 rr . 1001...100000... .......... U U U U U 4 4 2 2 2
855 subx 16 rr . 1001...101000... .......... U U U U U 4 4 2 2 2
856 subx 32 rr . 1001...110000... .......... U U U U U 8 6 2 2 2
857 subx 8 mm ax7 1001111100001... .......... U U U U U 18 18 12 12 12
858 subx 8 mm ay7 1001...100001111 .......... U U U U U 18 18 12 12 12
859 subx 8 mm axy7 1001111100001111 .......... U U U U U 18 18 12 12 12
860 subx 8 mm . 1001...100001... .......... U U U U U 18 18 12 12 12
861 subx 16 mm . 1001...101001... .......... U U U U U 18 18 12 12 12
862 subx 32 mm . 1001...110001... .......... U U U U U 30 30 12 12 12
863 swap 32 . . 0100100001000... .......... U U U U U 4 4 4 4 4
864 tas 8 . d 0100101011000... .......... U U U U U 4 4 4 4 4
865 tas 8 . . 0100101011...... A+-DXWL... U U U U U 14 14 12 12 12
866 trap 0 . . 010011100100.... .......... U U U U U 4 4 4 4 4
867 trapt 0 . . 0101000011111100 .......... . . U U U . . 4 4 4
868 trapt 16 . . 0101000011111010 .......... . . U U U . . 6 6 6
869 trapt 32 . . 0101000011111011 .......... . . U U U . . 8 8 8
870 trapf 0 . . 0101000111111100 .......... . . U U U . . 4 4 4
871 trapf 16 . . 0101000111111010 .......... . . U U U . . 6 6 6
872 trapf 32 . . 0101000111111011 .......... . . U U U . . 8 8 8
873 trapcc 0 . . 0101....11111100 .......... . . U U U . . 4 4 4
874 trapcc 16 . . 0101....11111010 .......... . . U U U . . 6 6 6
875 trapcc 32 . . 0101....11111011 .......... . . U U U . . 8 8 8
876 trapv 0 . . 0100111001110110 .......... U U U U U 4 4 4 4 4
877 tst 8 . d 0100101000000... .......... U U U U U 4 4 2 2 2
878 tst 8 . . 0100101000...... A+-DXWL... U U U U U 4 4 2 2 2
879 tst 8 . pcdi 0100101000111010 .......... . . U U U . . 7 7 7
880 tst 8 . pcix 0100101000111011 .......... . . U U U . . 9 9 9
881 tst 8 . i 0100101000111100 .......... . . U U U . . 6 6 6
882 tst 16 . d 0100101001000... .......... U U U U U 4 4 2 2 2
883 tst 16 . a 0100101001001... .......... . . U U U . . 2 2 2
884 tst 16 . . 0100101001...... A+-DXWL... U U U U U 4 4 2 2 2
885 tst 16 . pcdi 0100101001111010 .......... . . U U U . . 7 7 7
886 tst 16 . pcix 0100101001111011 .......... . . U U U . . 9 9 9
887 tst 16 . i 0100101001111100 .......... . . U U U . . 6 6 6
888 tst 32 . d 0100101010000... .......... U U U U U 4 4 2 2 2
889 tst 32 . a 0100101010001... .......... . . U U U . . 2 2 2
890 tst 32 . . 0100101010...... A+-DXWL... U U U U U 4 4 2 2 2
891 tst 32 . pcdi 0100101010111010 .......... . . U U U . . 7 7 7
892 tst 32 . pcix 0100101010111011 .......... . . U U U . . 9 9 9
893 tst 32 . i 0100101010111100 .......... . . U U U . . 6 6 6
894 unlk 32 . a7 0100111001011111 .......... U U U U U 12 12 6 6 6
895 unlk 32 . . 0100111001011... .......... U U U U U 12 12 6 6 6
896 unpk 16 rr . 1000...110000... .......... . . U U U . . 8 8 8
897 unpk 16 mm ax7 1000111110001... .......... . . U U U . . 13 13 13
898 unpk 16 mm ay7 1000...110001111 .......... . . U U U . . 13 13 13
899 unpk 16 mm axy7 1000111110001111 .......... . . U U U . . 13 13 13
900 unpk 16 mm . 1000...110001... .......... . . U U U . . 13 13 13
904 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
905 M68KMAKE_OPCODE_HANDLER_BODY
907 M68KMAKE_OP(1010, 0, ., .)
909 m68ki_exception_1010();
913 M68KMAKE_OP(1111, 0, ., .)
915 m68ki_exception_1111();
919 M68KMAKE_OP(040fpu0, 32, ., .)
921 // printf("FPU 040fpu0 HAS_FPU=%d\n",!!HAS_FPU);
927 m68ki_exception_1111();
931 M68KMAKE_OP(040fpu1, 32, ., .)
933 // printf("FPU 040fpu1 HAS_FPU=%d\n",!!HAS_FPU);
939 m68ki_exception_1111();
944 M68KMAKE_OP(abcd, 8, rr, .)
949 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
954 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
955 FLAG_V = ~res; /* Undefined V behavior */
957 FLAG_X = FLAG_C = (res > 0x9f) << 8;
961 FLAG_V &= res; /* Undefined V behavior part II */
962 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
964 res = MASK_OUT_ABOVE_8(res);
967 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
971 M68KMAKE_OP(abcd, 8, mm, ax7)
973 uint src = OPER_AY_PD_8();
974 uint ea = EA_A7_PD_8();
975 uint dst = m68ki_read_8(ea);
976 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
981 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
982 FLAG_V = ~res; /* Undefined V behavior */
984 FLAG_X = FLAG_C = (res > 0x9f) << 8;
988 FLAG_V &= res; /* Undefined V behavior part II */
989 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
991 res = MASK_OUT_ABOVE_8(res);
994 m68ki_write_8(ea, res);
998 M68KMAKE_OP(abcd, 8, mm, ay7)
1000 uint src = OPER_A7_PD_8();
1001 uint ea = EA_AX_PD_8();
1002 uint dst = m68ki_read_8(ea);
1003 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1008 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1009 FLAG_V = ~res; /* Undefined V behavior */
1011 FLAG_X = FLAG_C = (res > 0x9f) << 8;
1015 FLAG_V &= res; /* Undefined V behavior part II */
1016 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1018 res = MASK_OUT_ABOVE_8(res);
1021 m68ki_write_8(ea, res);
1025 M68KMAKE_OP(abcd, 8, mm, axy7)
1027 uint src = OPER_A7_PD_8();
1028 uint ea = EA_A7_PD_8();
1029 uint dst = m68ki_read_8(ea);
1030 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1035 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1036 FLAG_V = ~res; /* Undefined V behavior */
1038 FLAG_X = FLAG_C = (res > 0x9f) << 8;
1042 FLAG_V &= res; /* Undefined V behavior part II */
1043 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1045 res = MASK_OUT_ABOVE_8(res);
1048 m68ki_write_8(ea, res);
1052 M68KMAKE_OP(abcd, 8, mm, .)
1054 uint src = OPER_AY_PD_8();
1055 uint ea = EA_AX_PD_8();
1056 uint dst = m68ki_read_8(ea);
1057 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1062 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1063 FLAG_V = ~res; /* Undefined V behavior */
1065 FLAG_X = FLAG_C = (res > 0x9f) << 8;
1069 FLAG_V &= res; /* Undefined V behavior part II */
1070 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1072 res = MASK_OUT_ABOVE_8(res);
1075 m68ki_write_8(ea, res);
1079 M68KMAKE_OP(add, 8, er, d)
1082 uint src = MASK_OUT_ABOVE_8(DY);
1083 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1084 uint res = src + dst;
1086 FLAG_N = NFLAG_8(res);
1087 FLAG_V = VFLAG_ADD_8(src, dst, res);
1088 FLAG_X = FLAG_C = CFLAG_8(res);
1089 FLAG_Z = MASK_OUT_ABOVE_8(res);
1091 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1095 M68KMAKE_OP(add, 8, er, .)
1098 uint src = M68KMAKE_GET_OPER_AY_8;
1099 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1100 uint res = src + dst;
1102 FLAG_N = NFLAG_8(res);
1103 FLAG_V = VFLAG_ADD_8(src, dst, res);
1104 FLAG_X = FLAG_C = CFLAG_8(res);
1105 FLAG_Z = MASK_OUT_ABOVE_8(res);
1107 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1111 M68KMAKE_OP(add, 16, er, d)
1114 uint src = MASK_OUT_ABOVE_16(DY);
1115 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1116 uint res = src + dst;
1118 FLAG_N = NFLAG_16(res);
1119 FLAG_V = VFLAG_ADD_16(src, dst, res);
1120 FLAG_X = FLAG_C = CFLAG_16(res);
1121 FLAG_Z = MASK_OUT_ABOVE_16(res);
1123 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1127 M68KMAKE_OP(add, 16, er, a)
1130 uint src = MASK_OUT_ABOVE_16(AY);
1131 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1132 uint res = src + dst;
1134 FLAG_N = NFLAG_16(res);
1135 FLAG_V = VFLAG_ADD_16(src, dst, res);
1136 FLAG_X = FLAG_C = CFLAG_16(res);
1137 FLAG_Z = MASK_OUT_ABOVE_16(res);
1139 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1143 M68KMAKE_OP(add, 16, er, .)
1146 uint src = M68KMAKE_GET_OPER_AY_16;
1147 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1148 uint res = src + dst;
1150 FLAG_N = NFLAG_16(res);
1151 FLAG_V = VFLAG_ADD_16(src, dst, res);
1152 FLAG_X = FLAG_C = CFLAG_16(res);
1153 FLAG_Z = MASK_OUT_ABOVE_16(res);
1155 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1159 M68KMAKE_OP(add, 32, er, d)
1164 uint res = src + dst;
1166 FLAG_N = NFLAG_32(res);
1167 FLAG_V = VFLAG_ADD_32(src, dst, res);
1168 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1169 FLAG_Z = MASK_OUT_ABOVE_32(res);
1175 M68KMAKE_OP(add, 32, er, a)
1180 uint res = src + dst;
1182 FLAG_N = NFLAG_32(res);
1183 FLAG_V = VFLAG_ADD_32(src, dst, res);
1184 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1185 FLAG_Z = MASK_OUT_ABOVE_32(res);
1191 M68KMAKE_OP(add, 32, er, .)
1194 uint src = M68KMAKE_GET_OPER_AY_32;
1196 uint res = src + dst;
1198 FLAG_N = NFLAG_32(res);
1199 FLAG_V = VFLAG_ADD_32(src, dst, res);
1200 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1201 FLAG_Z = MASK_OUT_ABOVE_32(res);
1207 M68KMAKE_OP(add, 8, re, .)
1209 uint ea = M68KMAKE_GET_EA_AY_8;
1210 uint src = MASK_OUT_ABOVE_8(DX);
1211 uint dst = m68ki_read_8(ea);
1212 uint res = src + dst;
1214 FLAG_N = NFLAG_8(res);
1215 FLAG_V = VFLAG_ADD_8(src, dst, res);
1216 FLAG_X = FLAG_C = CFLAG_8(res);
1217 FLAG_Z = MASK_OUT_ABOVE_8(res);
1219 m68ki_write_8(ea, FLAG_Z);
1223 M68KMAKE_OP(add, 16, re, .)
1225 uint ea = M68KMAKE_GET_EA_AY_16;
1226 uint src = MASK_OUT_ABOVE_16(DX);
1227 uint dst = m68ki_read_16(ea);
1228 uint res = src + dst;
1230 FLAG_N = NFLAG_16(res);
1231 FLAG_V = VFLAG_ADD_16(src, dst, res);
1232 FLAG_X = FLAG_C = CFLAG_16(res);
1233 FLAG_Z = MASK_OUT_ABOVE_16(res);
1235 m68ki_write_16(ea, FLAG_Z);
1239 M68KMAKE_OP(add, 32, re, .)
1241 uint ea = M68KMAKE_GET_EA_AY_32;
1243 uint dst = m68ki_read_32(ea);
1244 uint res = src + dst;
1246 FLAG_N = NFLAG_32(res);
1247 FLAG_V = VFLAG_ADD_32(src, dst, res);
1248 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1249 FLAG_Z = MASK_OUT_ABOVE_32(res);
1251 m68ki_write_32(ea, FLAG_Z);
1255 M68KMAKE_OP(adda, 16, ., d)
1259 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
1263 M68KMAKE_OP(adda, 16, ., a)
1267 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
1271 M68KMAKE_OP(adda, 16, ., .)
1274 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
1276 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1280 M68KMAKE_OP(adda, 32, ., d)
1284 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
1288 M68KMAKE_OP(adda, 32, ., a)
1292 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
1296 M68KMAKE_OP(adda, 32, ., .)
1298 uint src = M68KMAKE_GET_OPER_AY_32;
1301 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1305 M68KMAKE_OP(addi, 8, ., d)
1308 uint src = OPER_I_8();
1309 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1310 uint res = src + dst;
1312 FLAG_N = NFLAG_8(res);
1313 FLAG_V = VFLAG_ADD_8(src, dst, res);
1314 FLAG_X = FLAG_C = CFLAG_8(res);
1315 FLAG_Z = MASK_OUT_ABOVE_8(res);
1317 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1321 M68KMAKE_OP(addi, 8, ., .)
1323 uint src = OPER_I_8();
1324 uint ea = M68KMAKE_GET_EA_AY_8;
1325 uint dst = m68ki_read_8(ea);
1326 uint res = src + dst;
1328 FLAG_N = NFLAG_8(res);
1329 FLAG_V = VFLAG_ADD_8(src, dst, res);
1330 FLAG_X = FLAG_C = CFLAG_8(res);
1331 FLAG_Z = MASK_OUT_ABOVE_8(res);
1333 m68ki_write_8(ea, FLAG_Z);
1337 M68KMAKE_OP(addi, 16, ., d)
1340 uint src = OPER_I_16();
1341 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1342 uint res = src + dst;
1344 FLAG_N = NFLAG_16(res);
1345 FLAG_V = VFLAG_ADD_16(src, dst, res);
1346 FLAG_X = FLAG_C = CFLAG_16(res);
1347 FLAG_Z = MASK_OUT_ABOVE_16(res);
1349 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1353 M68KMAKE_OP(addi, 16, ., .)
1355 uint src = OPER_I_16();
1356 uint ea = M68KMAKE_GET_EA_AY_16;
1357 uint dst = m68ki_read_16(ea);
1358 uint res = src + dst;
1360 FLAG_N = NFLAG_16(res);
1361 FLAG_V = VFLAG_ADD_16(src, dst, res);
1362 FLAG_X = FLAG_C = CFLAG_16(res);
1363 FLAG_Z = MASK_OUT_ABOVE_16(res);
1365 m68ki_write_16(ea, FLAG_Z);
1369 M68KMAKE_OP(addi, 32, ., d)
1372 uint src = OPER_I_32();
1374 uint res = src + dst;
1376 FLAG_N = NFLAG_32(res);
1377 FLAG_V = VFLAG_ADD_32(src, dst, res);
1378 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1379 FLAG_Z = MASK_OUT_ABOVE_32(res);
1385 M68KMAKE_OP(addi, 32, ., .)
1387 uint src = OPER_I_32();
1388 uint ea = M68KMAKE_GET_EA_AY_32;
1389 uint dst = m68ki_read_32(ea);
1390 uint res = src + dst;
1392 FLAG_N = NFLAG_32(res);
1393 FLAG_V = VFLAG_ADD_32(src, dst, res);
1394 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1395 FLAG_Z = MASK_OUT_ABOVE_32(res);
1397 m68ki_write_32(ea, FLAG_Z);
1401 M68KMAKE_OP(addq, 8, ., d)
1404 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1405 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1406 uint res = src + dst;
1408 FLAG_N = NFLAG_8(res);
1409 FLAG_V = VFLAG_ADD_8(src, dst, res);
1410 FLAG_X = FLAG_C = CFLAG_8(res);
1411 FLAG_Z = MASK_OUT_ABOVE_8(res);
1413 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1417 M68KMAKE_OP(addq, 8, ., .)
1419 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1420 uint ea = M68KMAKE_GET_EA_AY_8;
1421 uint dst = m68ki_read_8(ea);
1422 uint res = src + dst;
1424 FLAG_N = NFLAG_8(res);
1425 FLAG_V = VFLAG_ADD_8(src, dst, res);
1426 FLAG_X = FLAG_C = CFLAG_8(res);
1427 FLAG_Z = MASK_OUT_ABOVE_8(res);
1429 m68ki_write_8(ea, FLAG_Z);
1433 M68KMAKE_OP(addq, 16, ., d)
1436 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1437 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1438 uint res = src + dst;
1440 FLAG_N = NFLAG_16(res);
1441 FLAG_V = VFLAG_ADD_16(src, dst, res);
1442 FLAG_X = FLAG_C = CFLAG_16(res);
1443 FLAG_Z = MASK_OUT_ABOVE_16(res);
1445 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1449 M68KMAKE_OP(addq, 16, ., a)
1453 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1457 M68KMAKE_OP(addq, 16, ., .)
1459 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1460 uint ea = M68KMAKE_GET_EA_AY_16;
1461 uint dst = m68ki_read_16(ea);
1462 uint res = src + dst;
1464 FLAG_N = NFLAG_16(res);
1465 FLAG_V = VFLAG_ADD_16(src, dst, res);
1466 FLAG_X = FLAG_C = CFLAG_16(res);
1467 FLAG_Z = MASK_OUT_ABOVE_16(res);
1469 m68ki_write_16(ea, FLAG_Z);
1473 M68KMAKE_OP(addq, 32, ., d)
1476 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1478 uint res = src + dst;
1480 FLAG_N = NFLAG_32(res);
1481 FLAG_V = VFLAG_ADD_32(src, dst, res);
1482 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1483 FLAG_Z = MASK_OUT_ABOVE_32(res);
1489 M68KMAKE_OP(addq, 32, ., a)
1493 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1497 M68KMAKE_OP(addq, 32, ., .)
1499 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1500 uint ea = M68KMAKE_GET_EA_AY_32;
1501 uint dst = m68ki_read_32(ea);
1502 uint res = src + dst;
1505 FLAG_N = NFLAG_32(res);
1506 FLAG_V = VFLAG_ADD_32(src, dst, res);
1507 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1508 FLAG_Z = MASK_OUT_ABOVE_32(res);
1510 m68ki_write_32(ea, FLAG_Z);
1514 M68KMAKE_OP(addx, 8, rr, .)
1517 uint src = MASK_OUT_ABOVE_8(DY);
1518 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1519 uint res = src + dst + XFLAG_AS_1();
1521 FLAG_N = NFLAG_8(res);
1522 FLAG_V = VFLAG_ADD_8(src, dst, res);
1523 FLAG_X = FLAG_C = CFLAG_8(res);
1525 res = MASK_OUT_ABOVE_8(res);
1528 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1532 M68KMAKE_OP(addx, 16, rr, .)
1535 uint src = MASK_OUT_ABOVE_16(DY);
1536 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1537 uint res = src + dst + XFLAG_AS_1();
1539 FLAG_N = NFLAG_16(res);
1540 FLAG_V = VFLAG_ADD_16(src, dst, res);
1541 FLAG_X = FLAG_C = CFLAG_16(res);
1543 res = MASK_OUT_ABOVE_16(res);
1546 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1550 M68KMAKE_OP(addx, 32, rr, .)
1555 uint res = src + dst + XFLAG_AS_1();
1557 FLAG_N = NFLAG_32(res);
1558 FLAG_V = VFLAG_ADD_32(src, dst, res);
1559 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1561 res = MASK_OUT_ABOVE_32(res);
1568 M68KMAKE_OP(addx, 8, mm, ax7)
1570 uint src = OPER_AY_PD_8();
1571 uint ea = EA_A7_PD_8();
1572 uint dst = m68ki_read_8(ea);
1573 uint res = src + dst + XFLAG_AS_1();
1575 FLAG_N = NFLAG_8(res);
1576 FLAG_V = VFLAG_ADD_8(src, dst, res);
1577 FLAG_X = FLAG_C = CFLAG_8(res);
1579 res = MASK_OUT_ABOVE_8(res);
1582 m68ki_write_8(ea, res);
1586 M68KMAKE_OP(addx, 8, mm, ay7)
1588 uint src = OPER_A7_PD_8();
1589 uint ea = EA_AX_PD_8();
1590 uint dst = m68ki_read_8(ea);
1591 uint res = src + dst + XFLAG_AS_1();
1593 FLAG_N = NFLAG_8(res);
1594 FLAG_V = VFLAG_ADD_8(src, dst, res);
1595 FLAG_X = FLAG_C = CFLAG_8(res);
1597 res = MASK_OUT_ABOVE_8(res);
1600 m68ki_write_8(ea, res);
1604 M68KMAKE_OP(addx, 8, mm, axy7)
1606 uint src = OPER_A7_PD_8();
1607 uint ea = EA_A7_PD_8();
1608 uint dst = m68ki_read_8(ea);
1609 uint res = src + dst + XFLAG_AS_1();
1611 FLAG_N = NFLAG_8(res);
1612 FLAG_V = VFLAG_ADD_8(src, dst, res);
1613 FLAG_X = FLAG_C = CFLAG_8(res);
1615 res = MASK_OUT_ABOVE_8(res);
1618 m68ki_write_8(ea, res);
1622 M68KMAKE_OP(addx, 8, mm, .)
1624 uint src = OPER_AY_PD_8();
1625 uint ea = EA_AX_PD_8();
1626 uint dst = m68ki_read_8(ea);
1627 uint res = src + dst + XFLAG_AS_1();
1629 FLAG_N = NFLAG_8(res);
1630 FLAG_V = VFLAG_ADD_8(src, dst, res);
1631 FLAG_X = FLAG_C = CFLAG_8(res);
1633 res = MASK_OUT_ABOVE_8(res);
1636 m68ki_write_8(ea, res);
1640 M68KMAKE_OP(addx, 16, mm, .)
1642 uint src = OPER_AY_PD_16();
1643 uint ea = EA_AX_PD_16();
1644 uint dst = m68ki_read_16(ea);
1645 uint res = src + dst + XFLAG_AS_1();
1647 FLAG_N = NFLAG_16(res);
1648 FLAG_V = VFLAG_ADD_16(src, dst, res);
1649 FLAG_X = FLAG_C = CFLAG_16(res);
1651 res = MASK_OUT_ABOVE_16(res);
1654 m68ki_write_16(ea, res);
1658 M68KMAKE_OP(addx, 32, mm, .)
1660 uint src = OPER_AY_PD_32();
1661 uint ea = EA_AX_PD_32();
1662 uint dst = m68ki_read_32(ea);
1663 uint res = src + dst + XFLAG_AS_1();
1665 FLAG_N = NFLAG_32(res);
1666 FLAG_V = VFLAG_ADD_32(src, dst, res);
1667 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1669 res = MASK_OUT_ABOVE_32(res);
1672 m68ki_write_32(ea, res);
1676 M68KMAKE_OP(and, 8, er, d)
1678 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
1680 FLAG_N = NFLAG_8(FLAG_Z);
1681 FLAG_C = CFLAG_CLEAR;
1682 FLAG_V = VFLAG_CLEAR;
1686 M68KMAKE_OP(and, 8, er, .)
1688 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
1690 FLAG_N = NFLAG_8(FLAG_Z);
1691 FLAG_C = CFLAG_CLEAR;
1692 FLAG_V = VFLAG_CLEAR;
1696 M68KMAKE_OP(and, 16, er, d)
1698 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
1700 FLAG_N = NFLAG_16(FLAG_Z);
1701 FLAG_C = CFLAG_CLEAR;
1702 FLAG_V = VFLAG_CLEAR;
1706 M68KMAKE_OP(and, 16, er, .)
1708 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
1710 FLAG_N = NFLAG_16(FLAG_Z);
1711 FLAG_C = CFLAG_CLEAR;
1712 FLAG_V = VFLAG_CLEAR;
1716 M68KMAKE_OP(and, 32, er, d)
1720 FLAG_N = NFLAG_32(FLAG_Z);
1721 FLAG_C = CFLAG_CLEAR;
1722 FLAG_V = VFLAG_CLEAR;
1726 M68KMAKE_OP(and, 32, er, .)
1728 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
1730 FLAG_N = NFLAG_32(FLAG_Z);
1731 FLAG_C = CFLAG_CLEAR;
1732 FLAG_V = VFLAG_CLEAR;
1736 M68KMAKE_OP(and, 8, re, .)
1738 uint ea = M68KMAKE_GET_EA_AY_8;
1739 uint res = DX & m68ki_read_8(ea);
1741 FLAG_N = NFLAG_8(res);
1742 FLAG_C = CFLAG_CLEAR;
1743 FLAG_V = VFLAG_CLEAR;
1744 FLAG_Z = MASK_OUT_ABOVE_8(res);
1746 m68ki_write_8(ea, FLAG_Z);
1750 M68KMAKE_OP(and, 16, re, .)
1752 uint ea = M68KMAKE_GET_EA_AY_16;
1753 uint res = DX & m68ki_read_16(ea);
1755 FLAG_N = NFLAG_16(res);
1756 FLAG_C = CFLAG_CLEAR;
1757 FLAG_V = VFLAG_CLEAR;
1758 FLAG_Z = MASK_OUT_ABOVE_16(res);
1760 m68ki_write_16(ea, FLAG_Z);
1764 M68KMAKE_OP(and, 32, re, .)
1766 uint ea = M68KMAKE_GET_EA_AY_32;
1767 uint res = DX & m68ki_read_32(ea);
1769 FLAG_N = NFLAG_32(res);
1771 FLAG_C = CFLAG_CLEAR;
1772 FLAG_V = VFLAG_CLEAR;
1774 m68ki_write_32(ea, res);
1778 M68KMAKE_OP(andi, 8, ., d)
1780 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
1782 FLAG_N = NFLAG_8(FLAG_Z);
1783 FLAG_C = CFLAG_CLEAR;
1784 FLAG_V = VFLAG_CLEAR;
1788 M68KMAKE_OP(andi, 8, ., .)
1790 uint src = OPER_I_8();
1791 uint ea = M68KMAKE_GET_EA_AY_8;
1792 uint res = src & m68ki_read_8(ea);
1794 FLAG_N = NFLAG_8(res);
1796 FLAG_C = CFLAG_CLEAR;
1797 FLAG_V = VFLAG_CLEAR;
1799 m68ki_write_8(ea, res);
1803 M68KMAKE_OP(andi, 16, ., d)
1805 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
1807 FLAG_N = NFLAG_16(FLAG_Z);
1808 FLAG_C = CFLAG_CLEAR;
1809 FLAG_V = VFLAG_CLEAR;
1813 M68KMAKE_OP(andi, 16, ., .)
1815 uint src = OPER_I_16();
1816 uint ea = M68KMAKE_GET_EA_AY_16;
1817 uint res = src & m68ki_read_16(ea);
1819 FLAG_N = NFLAG_16(res);
1821 FLAG_C = CFLAG_CLEAR;
1822 FLAG_V = VFLAG_CLEAR;
1824 m68ki_write_16(ea, res);
1828 M68KMAKE_OP(andi, 32, ., d)
1830 FLAG_Z = DY &= (OPER_I_32());
1832 FLAG_N = NFLAG_32(FLAG_Z);
1833 FLAG_C = CFLAG_CLEAR;
1834 FLAG_V = VFLAG_CLEAR;
1838 M68KMAKE_OP(andi, 32, ., .)
1840 uint src = OPER_I_32();
1841 uint ea = M68KMAKE_GET_EA_AY_32;
1842 uint res = src & m68ki_read_32(ea);
1844 FLAG_N = NFLAG_32(res);
1846 FLAG_C = CFLAG_CLEAR;
1847 FLAG_V = VFLAG_CLEAR;
1849 m68ki_write_32(ea, res);
1853 M68KMAKE_OP(andi, 16, toc, .)
1855 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8());
1859 M68KMAKE_OP(andi, 16, tos, .)
1863 uint src = OPER_I_16();
1864 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
1865 m68ki_set_sr(m68ki_get_sr() & src);
1868 m68ki_exception_privilege_violation();
1872 M68KMAKE_OP(asr, 8, s, .)
1875 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1876 uint src = MASK_OUT_ABOVE_8(*r_dst);
1877 uint res = src >> shift;
1880 USE_CYCLES(shift<<CYC_SHIFT);
1883 res |= m68ki_shift_8_table[shift];
1885 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1887 FLAG_N = NFLAG_8(res);
1889 FLAG_V = VFLAG_CLEAR;
1890 FLAG_X = FLAG_C = src << (9-shift);
1894 M68KMAKE_OP(asr, 16, s, .)
1897 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1898 uint src = MASK_OUT_ABOVE_16(*r_dst);
1899 uint res = src >> shift;
1902 USE_CYCLES(shift<<CYC_SHIFT);
1905 res |= m68ki_shift_16_table[shift];
1907 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1909 FLAG_N = NFLAG_16(res);
1911 FLAG_V = VFLAG_CLEAR;
1912 FLAG_X = FLAG_C = src << (9-shift);
1916 M68KMAKE_OP(asr, 32, s, .)
1919 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1921 uint res = src >> shift;
1924 USE_CYCLES(shift<<CYC_SHIFT);
1927 res |= m68ki_shift_32_table[shift];
1931 FLAG_N = NFLAG_32(res);
1933 FLAG_V = VFLAG_CLEAR;
1934 FLAG_X = FLAG_C = src << (9-shift);
1938 M68KMAKE_OP(asr, 8, r, .)
1941 uint shift = DX & 0x3f;
1942 uint src = MASK_OUT_ABOVE_8(*r_dst);
1943 uint res = src >> shift;
1947 USE_CYCLES(shift<<CYC_SHIFT);
1952 res |= m68ki_shift_8_table[shift];
1954 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1956 FLAG_X = FLAG_C = src << (9-shift);
1957 FLAG_N = NFLAG_8(res);
1959 FLAG_V = VFLAG_CLEAR;
1969 FLAG_Z = ZFLAG_CLEAR;
1970 FLAG_V = VFLAG_CLEAR;
1974 *r_dst &= 0xffffff00;
1975 FLAG_C = CFLAG_CLEAR;
1976 FLAG_X = XFLAG_CLEAR;
1977 FLAG_N = NFLAG_CLEAR;
1979 FLAG_V = VFLAG_CLEAR;
1983 FLAG_C = CFLAG_CLEAR;
1984 FLAG_N = NFLAG_8(src);
1986 FLAG_V = VFLAG_CLEAR;
1990 M68KMAKE_OP(asr, 16, r, .)
1993 uint shift = DX & 0x3f;
1994 uint src = MASK_OUT_ABOVE_16(*r_dst);
1995 uint res = src >> shift;
1999 USE_CYCLES(shift<<CYC_SHIFT);
2004 res |= m68ki_shift_16_table[shift];
2006 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2008 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2009 FLAG_N = NFLAG_16(res);
2011 FLAG_V = VFLAG_CLEAR;
2021 FLAG_Z = ZFLAG_CLEAR;
2022 FLAG_V = VFLAG_CLEAR;
2026 *r_dst &= 0xffff0000;
2027 FLAG_C = CFLAG_CLEAR;
2028 FLAG_X = XFLAG_CLEAR;
2029 FLAG_N = NFLAG_CLEAR;
2031 FLAG_V = VFLAG_CLEAR;
2035 FLAG_C = CFLAG_CLEAR;
2036 FLAG_N = NFLAG_16(src);
2038 FLAG_V = VFLAG_CLEAR;
2042 M68KMAKE_OP(asr, 32, r, .)
2045 uint shift = DX & 0x3f;
2047 uint res = src >> shift;
2051 USE_CYCLES(shift<<CYC_SHIFT);
2056 res |= m68ki_shift_32_table[shift];
2060 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2061 FLAG_N = NFLAG_32(res);
2063 FLAG_V = VFLAG_CLEAR;
2069 *r_dst = 0xffffffff;
2073 FLAG_Z = ZFLAG_CLEAR;
2074 FLAG_V = VFLAG_CLEAR;
2079 FLAG_C = CFLAG_CLEAR;
2080 FLAG_X = XFLAG_CLEAR;
2081 FLAG_N = NFLAG_CLEAR;
2083 FLAG_V = VFLAG_CLEAR;
2087 FLAG_C = CFLAG_CLEAR;
2088 FLAG_N = NFLAG_32(src);
2090 FLAG_V = VFLAG_CLEAR;
2094 M68KMAKE_OP(asr, 16, ., .)
2096 uint ea = M68KMAKE_GET_EA_AY_16;
2097 uint src = m68ki_read_16(ea);
2098 uint res = src >> 1;
2103 m68ki_write_16(ea, res);
2105 FLAG_N = NFLAG_16(res);
2107 FLAG_V = VFLAG_CLEAR;
2108 FLAG_C = FLAG_X = src << 8;
2112 M68KMAKE_OP(asl, 8, s, .)
2115 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2116 uint src = MASK_OUT_ABOVE_8(*r_dst);
2117 uint res = MASK_OUT_ABOVE_8(src << shift);
2120 USE_CYCLES(shift<<CYC_SHIFT);
2122 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2124 FLAG_X = FLAG_C = src << shift;
2125 FLAG_N = NFLAG_8(res);
2127 src &= m68ki_shift_8_table[shift + 1];
2128 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
2132 M68KMAKE_OP(asl, 16, s, .)
2135 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2136 uint src = MASK_OUT_ABOVE_16(*r_dst);
2137 uint res = MASK_OUT_ABOVE_16(src << shift);
2140 USE_CYCLES(shift<<CYC_SHIFT);
2142 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2144 FLAG_N = NFLAG_16(res);
2146 FLAG_X = FLAG_C = src >> (8-shift);
2147 src &= m68ki_shift_16_table[shift + 1];
2148 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2152 M68KMAKE_OP(asl, 32, s, .)
2155 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2157 uint res = MASK_OUT_ABOVE_32(src << shift);
2160 USE_CYCLES(shift<<CYC_SHIFT);
2164 FLAG_N = NFLAG_32(res);
2166 FLAG_X = FLAG_C = src >> (24-shift);
2167 src &= m68ki_shift_32_table[shift + 1];
2168 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2172 M68KMAKE_OP(asl, 8, r, .)
2175 uint shift = DX & 0x3f;
2176 uint src = MASK_OUT_ABOVE_8(*r_dst);
2177 uint res = MASK_OUT_ABOVE_8(src << shift);
2181 USE_CYCLES(shift<<CYC_SHIFT);
2185 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2186 FLAG_X = FLAG_C = src << shift;
2187 FLAG_N = NFLAG_8(res);
2189 src &= m68ki_shift_8_table[shift + 1];
2190 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
2194 *r_dst &= 0xffffff00;
2195 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
2196 FLAG_N = NFLAG_CLEAR;
2198 FLAG_V = (!(src == 0))<<7;
2202 FLAG_C = CFLAG_CLEAR;
2203 FLAG_N = NFLAG_8(src);
2205 FLAG_V = VFLAG_CLEAR;
2209 M68KMAKE_OP(asl, 16, r, .)
2212 uint shift = DX & 0x3f;
2213 uint src = MASK_OUT_ABOVE_16(*r_dst);
2214 uint res = MASK_OUT_ABOVE_16(src << shift);
2218 USE_CYCLES(shift<<CYC_SHIFT);
2222 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2223 FLAG_X = FLAG_C = (src << shift) >> 8;
2224 FLAG_N = NFLAG_16(res);
2226 src &= m68ki_shift_16_table[shift + 1];
2227 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2231 *r_dst &= 0xffff0000;
2232 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
2233 FLAG_N = NFLAG_CLEAR;
2235 FLAG_V = (!(src == 0))<<7;
2239 FLAG_C = CFLAG_CLEAR;
2240 FLAG_N = NFLAG_16(src);
2242 FLAG_V = VFLAG_CLEAR;
2246 M68KMAKE_OP(asl, 32, r, .)
2249 uint shift = DX & 0x3f;
2251 uint res = MASK_OUT_ABOVE_32(src << shift);
2255 USE_CYCLES(shift<<CYC_SHIFT);
2260 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
2261 FLAG_N = NFLAG_32(res);
2263 src &= m68ki_shift_32_table[shift + 1];
2264 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2269 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
2270 FLAG_N = NFLAG_CLEAR;
2272 FLAG_V = (!(src == 0))<<7;
2276 FLAG_C = CFLAG_CLEAR;
2277 FLAG_N = NFLAG_32(src);
2279 FLAG_V = VFLAG_CLEAR;
2283 M68KMAKE_OP(asl, 16, ., .)
2285 uint ea = M68KMAKE_GET_EA_AY_16;
2286 uint src = m68ki_read_16(ea);
2287 uint res = MASK_OUT_ABOVE_16(src << 1);
2289 m68ki_write_16(ea, res);
2291 FLAG_N = NFLAG_16(res);
2293 FLAG_X = FLAG_C = src >> 7;
2295 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
2299 M68KMAKE_OP(bcc, 8, ., .)
2303 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2304 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2307 USE_CYCLES(CYC_BCC_NOTAKE_B);
2311 M68KMAKE_OP(bcc, 16, ., .)
2315 uint offset = OPER_I_16();
2317 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2318 m68ki_branch_16(offset);
2322 USE_CYCLES(CYC_BCC_NOTAKE_W);
2326 M68KMAKE_OP(bcc, 32, ., .)
2328 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2332 uint offset = OPER_I_32();
2334 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2335 m68ki_branch_32(offset);
2345 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2346 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2349 USE_CYCLES(CYC_BCC_NOTAKE_B);
2354 M68KMAKE_OP(bchg, 32, r, d)
2357 uint mask = 1 << (DX & 0x1f);
2359 FLAG_Z = *r_dst & mask;
2364 M68KMAKE_OP(bchg, 8, r, .)
2366 uint ea = M68KMAKE_GET_EA_AY_8;
2367 uint src = m68ki_read_8(ea);
2368 uint mask = 1 << (DX & 7);
2370 FLAG_Z = src & mask;
2371 m68ki_write_8(ea, src ^ mask);
2375 M68KMAKE_OP(bchg, 32, s, d)
2378 uint mask = 1 << (OPER_I_8() & 0x1f);
2380 FLAG_Z = *r_dst & mask;
2385 M68KMAKE_OP(bchg, 8, s, .)
2387 uint mask = 1 << (OPER_I_8() & 7);
2388 uint ea = M68KMAKE_GET_EA_AY_8;
2389 uint src = m68ki_read_8(ea);
2391 FLAG_Z = src & mask;
2392 m68ki_write_8(ea, src ^ mask);
2396 M68KMAKE_OP(bclr, 32, r, d)
2399 uint mask = 1 << (DX & 0x1f);
2401 FLAG_Z = *r_dst & mask;
2406 M68KMAKE_OP(bclr, 8, r, .)
2408 uint ea = M68KMAKE_GET_EA_AY_8;
2409 uint src = m68ki_read_8(ea);
2410 uint mask = 1 << (DX & 7);
2412 FLAG_Z = src & mask;
2413 m68ki_write_8(ea, src & ~mask);
2417 M68KMAKE_OP(bclr, 32, s, d)
2420 uint mask = 1 << (OPER_I_8() & 0x1f);
2422 FLAG_Z = *r_dst & mask;
2427 M68KMAKE_OP(bclr, 8, s, .)
2429 uint mask = 1 << (OPER_I_8() & 7);
2430 uint ea = M68KMAKE_GET_EA_AY_8;
2431 uint src = m68ki_read_8(ea);
2433 FLAG_Z = src & mask;
2434 m68ki_write_8(ea, src & ~mask);
2438 M68KMAKE_OP(bfchg, 32, ., d)
2440 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2442 uint word2 = OPER_I_16();
2443 uint offset = (word2>>6)&31;
2450 offset = REG_D[offset&7];
2452 width = REG_D[width&7];
2455 width = ((width-1) & 31) + 1;
2457 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2458 mask = ROR_32(mask, offset);
2460 FLAG_N = NFLAG_32(*data<<offset);
2461 FLAG_Z = *data & mask;
2462 FLAG_V = VFLAG_CLEAR;
2463 FLAG_C = CFLAG_CLEAR;
2469 m68ki_exception_illegal();
2473 M68KMAKE_OP(bfchg, 32, ., .)
2475 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2477 uint word2 = OPER_I_16();
2478 sint offset = (word2>>6)&31;
2485 uint ea = M68KMAKE_GET_EA_AY_8;
2489 offset = MAKE_INT_32(REG_D[offset&7]);
2491 width = REG_D[width&7];
2493 /* Offset is signed so we have to use ugly math =( */
2501 width = ((width-1) & 31) + 1;
2503 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2504 mask_long = mask_base >> offset;
2506 data_long = m68ki_read_32(ea);
2507 FLAG_N = NFLAG_32(data_long << offset);
2508 FLAG_Z = data_long & mask_long;
2509 FLAG_V = VFLAG_CLEAR;
2510 FLAG_C = CFLAG_CLEAR;
2512 m68ki_write_32(ea, data_long ^ mask_long);
2514 if((width + offset) > 32)
2516 mask_byte = MASK_OUT_ABOVE_8(mask_base) << (8-offset);
2517 data_byte = m68ki_read_8(ea+4);
2518 FLAG_Z |= (data_byte & mask_byte);
2519 m68ki_write_8(ea+4, data_byte ^ mask_byte);
2523 m68ki_exception_illegal();
2527 M68KMAKE_OP(bfclr, 32, ., d)
2529 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2531 uint word2 = OPER_I_16();
2532 uint offset = (word2>>6)&31;
2539 offset = REG_D[offset&7];
2541 width = REG_D[width&7];
2545 width = ((width-1) & 31) + 1;
2548 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2549 mask = ROR_32(mask, offset);
2551 FLAG_N = NFLAG_32(*data<<offset);
2552 FLAG_Z = *data & mask;
2553 FLAG_V = VFLAG_CLEAR;
2554 FLAG_C = CFLAG_CLEAR;
2560 m68ki_exception_illegal();
2564 M68KMAKE_OP(bfclr, 32, ., .)
2566 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2568 uint word2 = OPER_I_16();
2569 sint offset = (word2>>6)&31;
2576 uint ea = M68KMAKE_GET_EA_AY_8;
2580 offset = MAKE_INT_32(REG_D[offset&7]);
2582 width = REG_D[width&7];
2584 /* Offset is signed so we have to use ugly math =( */
2592 width = ((width-1) & 31) + 1;
2594 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2595 mask_long = mask_base >> offset;
2597 data_long = m68ki_read_32(ea);
2598 FLAG_N = NFLAG_32(data_long << offset);
2599 FLAG_Z = data_long & mask_long;
2600 FLAG_V = VFLAG_CLEAR;
2601 FLAG_C = CFLAG_CLEAR;
2603 m68ki_write_32(ea, data_long & ~mask_long);
2605 if((width + offset) > 32)
2607 mask_byte = MASK_OUT_ABOVE_8(mask_base) << (8-offset);
2608 data_byte = m68ki_read_8(ea+4);
2609 FLAG_Z |= (data_byte & mask_byte);
2610 m68ki_write_8(ea+4, data_byte & ~mask_byte);
2614 m68ki_exception_illegal();
2618 M68KMAKE_OP(bfexts, 32, ., d)
2620 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2622 uint word2 = OPER_I_16();
2623 uint offset = (word2>>6)&31;
2629 offset = REG_D[offset&7];
2631 width = REG_D[width&7];
2634 width = ((width-1) & 31) + 1;
2636 data = ROL_32(data, offset);
2637 FLAG_N = NFLAG_32(data);
2638 data = MAKE_INT_32(data) >> (32 - width);
2641 FLAG_V = VFLAG_CLEAR;
2642 FLAG_C = CFLAG_CLEAR;
2644 REG_D[(word2>>12)&7] = data;
2648 m68ki_exception_illegal();
2652 M68KMAKE_OP(bfexts, 32, ., .)
2654 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2656 uint word2 = OPER_I_16();
2657 sint offset = (word2>>6)&31;
2660 uint ea = M68KMAKE_GET_EA_AY_8;
2664 offset = MAKE_INT_32(REG_D[offset&7]);
2666 width = REG_D[width&7];
2669 /* Offset is signed so we have to use ugly math =( */
2678 width = ((width-1) & 31) + 1;
2680 data = (offset+width) < 8 ? (m68ki_read_8(ea) << 24) :
2681 (offset+width) < 16 ? (m68ki_read_16(ea) << 16) : m68ki_read_32(ea);
2683 data = MASK_OUT_ABOVE_32(data<<offset);
2685 if((offset+width) > 32)
2686 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2688 FLAG_N = NFLAG_32(data);
2689 data = MAKE_INT_32(data) >> (32 - width);
2692 FLAG_V = VFLAG_CLEAR;
2693 FLAG_C = CFLAG_CLEAR;
2695 REG_D[(word2 >> 12) & 7] = data;
2699 m68ki_exception_illegal();
2703 M68KMAKE_OP(bfextu, 32, ., d)
2705 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2707 uint word2 = OPER_I_16();
2708 uint offset = (word2>>6)&31;
2714 offset = REG_D[offset&7];
2716 width = REG_D[width&7];
2719 width = ((width-1) & 31) + 1;
2721 data = ROL_32(data, offset);
2722 FLAG_N = NFLAG_32(data);
2723 data >>= 32 - width;
2726 FLAG_V = VFLAG_CLEAR;
2727 FLAG_C = CFLAG_CLEAR;
2729 REG_D[(word2>>12)&7] = data;
2733 m68ki_exception_illegal();
2737 M68KMAKE_OP(bfextu, 32, ., .)
2739 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2741 uint word2 = OPER_I_16();
2742 sint offset = (word2>>6)&31;
2745 uint ea = M68KMAKE_GET_EA_AY_8;
2749 offset = MAKE_INT_32(REG_D[offset&7]);
2751 width = REG_D[width&7];
2754 /* Offset is signed so we have to use ugly math =( */
2763 width = ((width-1) & 31) + 1;
2765 data = (offset+width) < 8 ? (m68ki_read_8(ea) << 24) :
2766 (offset+width) < 16 ? (m68ki_read_16(ea) << 16) : m68ki_read_32(ea);
2767 data = MASK_OUT_ABOVE_32(data<<offset);
2769 if((offset+width) > 32)
2770 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2772 FLAG_N = NFLAG_32(data);
2773 data >>= (32 - width);
2776 FLAG_V = VFLAG_CLEAR;
2777 FLAG_C = CFLAG_CLEAR;
2779 REG_D[(word2 >> 12) & 7] = data;
2783 m68ki_exception_illegal();
2787 M68KMAKE_OP(bfffo, 32, ., d)
2789 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2791 uint word2 = OPER_I_16();
2792 uint offset = (word2>>6)&31;
2799 offset = REG_D[offset&7];
2801 width = REG_D[width&7];
2804 width = ((width-1) & 31) + 1;
2806 data = ROL_32(data, offset);
2807 FLAG_N = NFLAG_32(data);
2808 data >>= 32 - width;
2811 FLAG_V = VFLAG_CLEAR;
2812 FLAG_C = CFLAG_CLEAR;
2814 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2817 REG_D[(word2>>12)&7] = offset;
2821 m68ki_exception_illegal();
2825 M68KMAKE_OP(bfffo, 32, ., .)
2827 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2829 uint word2 = OPER_I_16();
2830 sint offset = (word2>>6)&31;
2835 uint ea = M68KMAKE_GET_EA_AY_8;
2839 offset = MAKE_INT_32(REG_D[offset&7]);
2841 width = REG_D[width&7];
2843 /* Offset is signed so we have to use ugly math =( */
2845 local_offset = offset % 8;
2846 if(local_offset < 0)
2851 width = ((width-1) & 31) + 1;
2853 data = (offset+width) < 16 ? (m68ki_read_16(ea) << 16) : m68ki_read_32(ea);
2854 data = MASK_OUT_ABOVE_32(data<<local_offset);
2856 if((local_offset+width) > 32)
2857 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
2859 FLAG_N = NFLAG_32(data);
2860 data >>= (32 - width);
2863 FLAG_V = VFLAG_CLEAR;
2864 FLAG_C = CFLAG_CLEAR;
2866 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2869 REG_D[(word2>>12)&7] = offset;
2873 m68ki_exception_illegal();
2877 M68KMAKE_OP(bfins, 32, ., d)
2879 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2881 uint word2 = OPER_I_16();
2882 uint offset = (word2>>6)&31;
2886 uint64 insert = REG_D[(word2>>12)&7];
2890 offset = REG_D[offset&7];
2892 width = REG_D[width&7];
2896 width = ((width-1) & 31) + 1;
2899 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2900 mask = ROR_32(mask, offset);
2902 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
2903 FLAG_N = NFLAG_32(insert);
2905 insert = ROR_32(insert, offset);
2907 FLAG_V = VFLAG_CLEAR;
2908 FLAG_C = CFLAG_CLEAR;
2915 m68ki_exception_illegal();
2919 M68KMAKE_OP(bfins, 32, ., .)
2921 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2923 uint word2 = OPER_I_16();
2924 sint offset = (word2>>6)&31;
2926 uint insert_base = REG_D[(word2>>12)&7];
2934 uint ea = M68KMAKE_GET_EA_AY_8;
2938 offset = MAKE_INT_32(REG_D[offset&7]);
2940 width = REG_D[width&7];
2943 /* Offset is signed so we have to use ugly math =( */
2952 width = ((width-1) & 31) + 1;
2954 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2955 mask_long = mask_base >> offset;
2957 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
2958 FLAG_N = NFLAG_32(insert_base);
2959 FLAG_Z = insert_base;
2960 insert_long = insert_base >> offset;
2962 data_long = (offset+width) < 8 ? (m68ki_read_8(ea) << 24) :
2963 (offset+width) < 16 ? (m68ki_read_16(ea) << 16) : m68ki_read_32(ea);
2964 FLAG_V = VFLAG_CLEAR;
2965 FLAG_C = CFLAG_CLEAR;
2967 if((width + offset) < 8) {
2968 m68ki_write_8(ea, ((data_long & ~mask_long) | insert_long) >> 24);
2969 } else if((width + offset) < 16) {
2970 m68ki_write_16(ea, ((data_long & ~mask_long) | insert_long) >> 16);
2972 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
2975 if((width + offset) > 32)
2977 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2978 insert_byte = MASK_OUT_ABOVE_8(insert_base);
2979 data_byte = m68ki_read_8(ea+4);
2980 FLAG_Z |= (data_byte & mask_byte);
2981 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
2985 m68ki_exception_illegal();
2989 M68KMAKE_OP(bfset, 32, ., d)
2991 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2993 uint word2 = OPER_I_16();
2994 uint offset = (word2>>6)&31;
3001 offset = REG_D[offset&7];
3003 width = REG_D[width&7];
3007 width = ((width-1) & 31) + 1;
3010 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3011 mask = ROR_32(mask, offset);
3013 FLAG_N = NFLAG_32(*data<<offset);
3014 FLAG_Z = *data & mask;
3015 FLAG_V = VFLAG_CLEAR;
3016 FLAG_C = CFLAG_CLEAR;
3022 m68ki_exception_illegal();
3026 M68KMAKE_OP(bfset, 32, ., .)
3028 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3030 uint word2 = OPER_I_16();
3031 sint offset = (word2>>6)&31;
3038 uint ea = M68KMAKE_GET_EA_AY_8;
3042 offset = MAKE_INT_32(REG_D[offset&7]);
3044 width = REG_D[width&7];
3046 /* Offset is signed so we have to use ugly math =( */
3054 width = ((width-1) & 31) + 1;
3057 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3058 mask_long = mask_base >> offset;
3060 data_long = m68ki_read_32(ea);
3061 FLAG_N = NFLAG_32(data_long << offset);
3062 FLAG_Z = data_long & mask_long;
3063 FLAG_V = VFLAG_CLEAR;
3064 FLAG_C = CFLAG_CLEAR;
3066 m68ki_write_32(ea, data_long | mask_long);
3068 if((width + offset) > 32)
3070 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3071 data_byte = m68ki_read_8(ea+4);
3072 FLAG_Z |= (data_byte & mask_byte);
3073 m68ki_write_8(ea+4, data_byte | mask_byte);
3077 m68ki_exception_illegal();
3081 M68KMAKE_OP(bftst, 32, ., d)
3083 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3085 uint word2 = OPER_I_16();
3086 uint offset = (word2>>6)&31;
3093 offset = REG_D[offset&7];
3095 width = REG_D[width&7];
3099 width = ((width-1) & 31) + 1;
3102 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3103 mask = ROR_32(mask, offset);
3105 FLAG_N = NFLAG_32(*data<<offset);
3106 FLAG_Z = *data & mask;
3107 FLAG_V = VFLAG_CLEAR;
3108 FLAG_C = CFLAG_CLEAR;
3112 m68ki_exception_illegal();
3116 M68KMAKE_OP(bftst, 32, ., .)
3118 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3120 uint word2 = OPER_I_16();
3121 sint offset = (word2>>6)&31;
3128 uint ea = M68KMAKE_GET_EA_AY_8;
3131 offset = MAKE_INT_32(REG_D[offset&7]);
3133 width = REG_D[width&7];
3135 /* Offset is signed so we have to use ugly math =( */
3143 width = ((width-1) & 31) + 1;
3146 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3147 mask_long = mask_base >> offset;
3149 data_long = m68ki_read_32(ea);
3150 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
3151 FLAG_Z = data_long & mask_long;
3152 FLAG_V = VFLAG_CLEAR;
3153 FLAG_C = CFLAG_CLEAR;
3155 if((width + offset) > 32)
3157 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3158 data_byte = m68ki_read_8(ea+4);
3159 FLAG_Z |= (data_byte & mask_byte);
3163 m68ki_exception_illegal();
3167 M68KMAKE_OP(bkpt, 0, ., .)
3169 // TODO: review this...
3170 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
3172 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
3174 m68ki_exception_illegal();
3178 M68KMAKE_OP(bra, 8, ., .)
3180 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3181 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3182 // TODO: review this...
3183 // if(REG_PC == REG_PPC)
3184 // USE_ALL_CYCLES();
3188 M68KMAKE_OP(bra, 16, ., .)
3190 uint offset = OPER_I_16();
3192 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3193 m68ki_branch_16(offset);
3194 // TODO: review this...
3195 // if(REG_PC == REG_PPC)
3196 // USE_ALL_CYCLES();
3200 M68KMAKE_OP(bra, 32, ., .)
3202 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3204 uint offset = OPER_I_32();
3206 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3207 m68ki_branch_32(offset);
3208 // TODO: review this...
3209 // if(REG_PC == REG_PPC)
3210 // USE_ALL_CYCLES();
3215 // TODO: review this...
3216 m68ki_exception_illegal();
3217 // m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3218 // m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3219 // if(REG_PC == REG_PPC)
3220 // USE_ALL_CYCLES();
3225 M68KMAKE_OP(bset, 32, r, d)
3228 uint mask = 1 << (DX & 0x1f);
3230 FLAG_Z = *r_dst & mask;
3235 M68KMAKE_OP(bset, 8, r, .)
3237 uint ea = M68KMAKE_GET_EA_AY_8;
3238 uint src = m68ki_read_8(ea);
3239 uint mask = 1 << (DX & 7);
3241 FLAG_Z = src & mask;
3242 m68ki_write_8(ea, src | mask);
3246 M68KMAKE_OP(bset, 32, s, d)
3249 uint mask = 1 << (OPER_I_8() & 0x1f);
3251 FLAG_Z = *r_dst & mask;
3256 M68KMAKE_OP(bset, 8, s, .)
3258 uint mask = 1 << (OPER_I_8() & 7);
3259 uint ea = M68KMAKE_GET_EA_AY_8;
3260 uint src = m68ki_read_8(ea);
3262 FLAG_Z = src & mask;
3263 m68ki_write_8(ea, src | mask);
3267 M68KMAKE_OP(bsr, 8, ., .)
3269 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3270 m68ki_push_32(REG_PC);
3271 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3275 M68KMAKE_OP(bsr, 16, ., .)
3277 uint offset = OPER_I_16();
3278 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3279 m68ki_push_32(REG_PC);
3281 m68ki_branch_16(offset);
3285 M68KMAKE_OP(bsr, 32, ., .)
3287 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3289 uint offset = OPER_I_32();
3290 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3291 m68ki_push_32(REG_PC);
3293 m68ki_branch_32(offset);
3298 // TODO: review this...
3299 m68ki_exception_illegal();
3300 // m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3301 // m68ki_push_32(REG_PC);
3302 // m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3307 M68KMAKE_OP(btst, 32, r, d)
3309 FLAG_Z = DY & (1 << (DX & 0x1f));
3313 M68KMAKE_OP(btst, 8, r, .)
3315 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
3319 M68KMAKE_OP(btst, 32, s, d)
3321 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
3325 M68KMAKE_OP(btst, 8, s, .)
3327 uint bit = OPER_I_8() & 7;
3329 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
3333 M68KMAKE_OP(callm, 32, ., .)
3335 /* note: watch out for pcrelative modes */
3336 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
3338 uint ea = M68KMAKE_GET_EA_AY_32;
3340 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3342 (void)ea; /* just to avoid an 'unused variable' warning */
3343 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
3344 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
3345 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
3348 m68ki_exception_illegal();
3352 M68KMAKE_OP(cas, 8, ., .)
3354 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3356 uint word2 = OPER_I_16();
3357 uint ea = M68KMAKE_GET_EA_AY_8;
3358 uint dest = m68ki_read_8(ea);
3359 uint* compare = ®_D[word2 & 7];
3360 uint res = dest - MASK_OUT_ABOVE_8(*compare);
3362 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3363 FLAG_N = NFLAG_8(res);
3364 FLAG_Z = MASK_OUT_ABOVE_8(res);
3365 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
3366 FLAG_C = CFLAG_8(res);
3369 *compare = MASK_OUT_BELOW_8(*compare) | dest;
3373 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
3377 m68ki_exception_illegal();
3381 M68KMAKE_OP(cas, 16, ., .)
3383 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3385 uint word2 = OPER_I_16();
3386 uint ea = M68KMAKE_GET_EA_AY_16;
3387 uint dest = m68ki_read_16(ea);
3388 uint* compare = ®_D[word2 & 7];
3389 uint res = dest - MASK_OUT_ABOVE_16(*compare);
3391 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3392 FLAG_N = NFLAG_16(res);
3393 FLAG_Z = MASK_OUT_ABOVE_16(res);
3394 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
3395 FLAG_C = CFLAG_16(res);
3398 *compare = MASK_OUT_BELOW_16(*compare) | dest;
3402 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
3406 m68ki_exception_illegal();
3410 M68KMAKE_OP(cas, 32, ., .)
3412 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3414 uint word2 = OPER_I_16();
3415 uint ea = M68KMAKE_GET_EA_AY_32;
3416 uint dest = m68ki_read_32(ea);
3417 uint* compare = ®_D[word2 & 7];
3418 uint res = dest - *compare;
3420 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3421 FLAG_N = NFLAG_32(res);
3422 FLAG_Z = MASK_OUT_ABOVE_32(res);
3423 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
3424 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
3431 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
3435 m68ki_exception_illegal();
3439 M68KMAKE_OP(cas2, 16, ., .)
3441 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3443 uint word2 = OPER_I_32();
3444 uint* compare1 = ®_D[(word2 >> 16) & 7];
3445 uint ea1 = REG_DA[(word2 >> 28) & 15];
3446 uint dest1 = m68ki_read_16(ea1);
3447 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
3448 uint* compare2 = ®_D[word2 & 7];
3449 uint ea2 = REG_DA[(word2 >> 12) & 15];
3450 uint dest2 = m68ki_read_16(ea2);
3453 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3454 FLAG_N = NFLAG_16(res1);
3455 FLAG_Z = MASK_OUT_ABOVE_16(res1);
3456 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
3457 FLAG_C = CFLAG_16(res1);
3461 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
3463 FLAG_N = NFLAG_16(res2);
3464 FLAG_Z = MASK_OUT_ABOVE_16(res2);
3465 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
3466 FLAG_C = CFLAG_16(res2);
3471 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
3472 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
3476 *compare1 = BIT_1F(word2) ? (uint)MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
3477 *compare2 = BIT_F(word2) ? (uint)MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
3480 m68ki_exception_illegal();
3484 M68KMAKE_OP(cas2, 32, ., .)
3486 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3488 uint word2 = OPER_I_32();
3489 uint* compare1 = ®_D[(word2 >> 16) & 7];
3490 uint ea1 = REG_DA[(word2 >> 28) & 15];
3491 uint dest1 = m68ki_read_32(ea1);
3492 uint res1 = dest1 - *compare1;
3493 uint* compare2 = ®_D[word2 & 7];
3494 uint ea2 = REG_DA[(word2 >> 12) & 15];
3495 uint dest2 = m68ki_read_32(ea2);
3498 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3499 FLAG_N = NFLAG_32(res1);
3500 FLAG_Z = MASK_OUT_ABOVE_32(res1);
3501 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
3502 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
3506 res2 = dest2 - *compare2;
3508 FLAG_N = NFLAG_32(res2);
3509 FLAG_Z = MASK_OUT_ABOVE_32(res2);
3510 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
3511 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
3516 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
3517 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
3525 m68ki_exception_illegal();
3529 M68KMAKE_OP(chk, 16, ., d)
3531 sint src = MAKE_INT_16(DX);
3532 sint bound = MAKE_INT_16(DY);
3534 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3535 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3536 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3538 if(src >= 0 && src <= bound)
3542 FLAG_N = (src < 0)<<7;
3543 m68ki_exception_trap(EXCEPTION_CHK);
3547 M68KMAKE_OP(chk, 16, ., .)
3549 sint src = MAKE_INT_16(DX);
3550 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3552 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3553 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3554 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3556 if(src >= 0 && src <= bound)
3560 FLAG_N = (src < 0)<<7;
3561 m68ki_exception_trap(EXCEPTION_CHK);
3565 M68KMAKE_OP(chk, 32, ., d)
3567 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3569 sint src = MAKE_INT_32(DX);
3570 sint bound = MAKE_INT_32(DY);
3572 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3573 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3574 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3576 if(src >= 0 && src <= bound)
3580 FLAG_N = (src < 0)<<7;
3581 m68ki_exception_trap(EXCEPTION_CHK);
3584 m68ki_exception_illegal();
3588 M68KMAKE_OP(chk, 32, ., .)
3590 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3592 sint src = MAKE_INT_32(DX);
3593 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
3595 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3596 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3597 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3599 if(src >= 0 && src <= bound)
3603 FLAG_N = (src < 0)<<7;
3604 m68ki_exception_trap(EXCEPTION_CHK);
3607 m68ki_exception_illegal();
3611 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
3613 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3615 uint word2 = OPER_I_16();
3616 sint compare = REG_DA[(word2 >> 12) & 15];
3620 uint ea = EA_PCDI_8();
3621 sint lower_bound = m68ki_read_pcrel_8(ea);
3622 sint upper_bound = m68ki_read_pcrel_8(ea + 1);
3624 // for signed compare, the arithmetically smaller value is the lower bound
3625 if (lower_bound & 0x80) {
3626 lower_bound = (int32)(int8)lower_bound;
3627 upper_bound = (int32)(int8)upper_bound;
3630 compare = (int32)(int8)compare;
3633 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3634 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3636 if(COND_CS() && BIT_B(word2))
3637 m68ki_exception_trap(EXCEPTION_CHK);
3642 m68ki_exception_illegal();
3646 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
3648 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3650 uint word2 = OPER_I_16();
3651 sint compare = REG_DA[(word2 >> 12) & 15];
3655 uint ea = EA_PCIX_8();
3656 sint lower_bound = m68ki_read_pcrel_8(ea);
3657 sint upper_bound = m68ki_read_pcrel_8(ea + 1);
3659 if (lower_bound & 0x80) {
3660 lower_bound = (int32)(int8)lower_bound;
3661 upper_bound = (int32)(int8)upper_bound;
3664 compare = (int32)(int8)compare;
3667 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3668 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3670 if(COND_CS() && BIT_B(word2))
3671 m68ki_exception_trap(EXCEPTION_CHK);
3675 m68ki_exception_illegal();
3679 M68KMAKE_OP(chk2cmp2, 8, ., .)
3681 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3683 uint word2 = OPER_I_16();
3684 sint compare = REG_DA[(word2 >> 12) & 15];
3688 uint ea = M68KMAKE_GET_EA_AY_8;
3689 sint lower_bound = (int8)m68ki_read_8(ea);
3690 sint upper_bound = (int8)m68ki_read_8(ea + 1);
3692 // for signed compare, the arithmetically smaller value is the lower bound
3693 if (lower_bound & 0x80) {
3694 lower_bound = (int32)(int8)lower_bound;
3695 upper_bound = (int32)(int8)upper_bound;
3698 compare = (int32)(int8)compare;
3701 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3702 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3704 if(COND_CS() && BIT_B(word2))
3705 m68ki_exception_trap(EXCEPTION_CHK);
3708 m68ki_exception_illegal();
3712 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
3714 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3716 uint word2 = OPER_I_16();
3717 sint compare = REG_DA[(word2 >> 12) & 15];
3721 uint ea = EA_PCDI_16();
3722 sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
3723 sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
3725 // for signed compare, the arithmetically smaller value is the lower bound
3726 if (lower_bound & 0x8000) {
3727 lower_bound = (int32)(int16)lower_bound;
3728 upper_bound = (int32)(int16)upper_bound;
3731 compare = (int32)(int16)compare;
3734 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3735 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3737 if(COND_CS() && BIT_B(word2))
3738 m68ki_exception_trap(EXCEPTION_CHK);
3741 m68ki_exception_illegal();
3745 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
3747 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3749 uint word2 = OPER_I_16();
3750 sint compare = REG_DA[(word2 >> 12) & 15];
3754 uint ea = EA_PCIX_16();
3755 sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
3756 sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
3758 // for signed compare, the arithmetically smaller value is the lower bound
3759 if (lower_bound & 0x8000) {
3760 lower_bound = (int32)(int16)lower_bound;
3761 upper_bound = (int32)(int16)upper_bound;
3764 compare = (int32)(int16)compare;
3767 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3768 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3770 if(COND_CS() && BIT_B(word2))
3771 m68ki_exception_trap(EXCEPTION_CHK);
3774 m68ki_exception_illegal();
3778 M68KMAKE_OP(chk2cmp2, 16, ., .)
3780 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3782 uint word2 = OPER_I_16();
3783 sint compare = REG_DA[(word2 >> 12) & 15];
3787 uint ea = M68KMAKE_GET_EA_AY_16;
3788 sint lower_bound = (int16)m68ki_read_16(ea);
3789 sint upper_bound = (int16)m68ki_read_16(ea + 2);
3791 // for signed compare, the arithmetically smaller value is the lower bound
3792 if (lower_bound & 0x8000) {
3793 lower_bound = (int32)(int16)lower_bound;
3794 upper_bound = (int32)(int16)upper_bound;
3797 compare = (int32)(int16)compare;
3800 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3801 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3803 if(COND_CS() && BIT_B(word2))
3804 m68ki_exception_trap(EXCEPTION_CHK);
3807 m68ki_exception_illegal();
3811 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
3813 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3815 uint32 word2 = OPER_I_16();
3816 sint64 compare = REG_DA[(word2 >> 12) & 15];
3817 uint32 ea = EA_PCDI_32();
3818 sint64 lower_bound = m68ki_read_pcrel_32(ea);
3819 sint64 upper_bound = m68ki_read_pcrel_32(ea + 4);
3821 // for signed compare, the arithmetically smaller value is the lower bound
3822 if (lower_bound & 0x80000000) {
3823 lower_bound = (int64)(int32)lower_bound;
3824 upper_bound = (int64)(int32)upper_bound;
3825 compare = (int64)(int32)compare;
3828 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3829 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3831 if(COND_CS() && BIT_B(word2))
3832 m68ki_exception_trap(EXCEPTION_CHK);
3835 m68ki_exception_illegal();
3839 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
3841 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3843 uint32 word2 = OPER_I_16();
3844 sint64 compare = REG_DA[(word2 >> 12) & 15];
3845 uint32 ea = EA_PCIX_32();
3846 sint64 lower_bound = m68ki_read_32(ea);
3847 sint64 upper_bound = m68ki_read_32(ea + 4);
3849 // for signed compare, the arithmetically smaller value is the lower bound
3850 if (lower_bound & 0x80000000) {
3851 lower_bound = (int64)(int32)lower_bound;
3852 upper_bound = (int64)(int32)upper_bound;
3853 compare = (int64)(int32)compare;
3856 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3857 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3859 if(COND_CS() && BIT_B(word2))
3860 m68ki_exception_trap(EXCEPTION_CHK);
3863 m68ki_exception_illegal();
3867 M68KMAKE_OP(chk2cmp2, 32, ., .)
3869 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3871 uint32 word2 = OPER_I_16();
3872 sint64 compare = REG_DA[(word2 >> 12) & 15];
3873 uint32 ea = M68KMAKE_GET_EA_AY_32;
3874 sint64 lower_bound = m68ki_read_32(ea);
3875 sint64 upper_bound = m68ki_read_32(ea + 4);
3877 // for signed compare, the arithmetically smaller value is the lower bound
3878 if (lower_bound & 0x80000000) {
3879 lower_bound = (int64)(int32)lower_bound;
3880 upper_bound = (int64)(int32)upper_bound;
3881 compare = (int64)(int32)compare;
3884 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3885 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3887 if(COND_CS() && BIT_B(word2))
3888 m68ki_exception_trap(EXCEPTION_CHK);
3891 m68ki_exception_illegal();
3895 M68KMAKE_OP(clr, 8, ., d)
3899 FLAG_N = NFLAG_CLEAR;
3900 FLAG_V = VFLAG_CLEAR;
3901 FLAG_C = CFLAG_CLEAR;
3906 M68KMAKE_OP(clr, 8, ., .)
3908 uint32 ea = M68KMAKE_GET_EA_AY_8;
3910 if(CPU_TYPE_IS_000(CPU_TYPE))
3911 m68ki_read_8(ea); /* the 68000 does a dummy read, the value is discarded */
3912 m68ki_write_8(ea, 0);
3914 FLAG_N = NFLAG_CLEAR;
3915 FLAG_V = VFLAG_CLEAR;
3916 FLAG_C = CFLAG_CLEAR;
3921 M68KMAKE_OP(clr, 16, ., d)
3925 FLAG_N = NFLAG_CLEAR;
3926 FLAG_V = VFLAG_CLEAR;
3927 FLAG_C = CFLAG_CLEAR;
3932 M68KMAKE_OP(clr, 16, ., .)
3934 uint32 ea = M68KMAKE_GET_EA_AY_16;
3936 if(CPU_TYPE_IS_000(CPU_TYPE))
3937 m68ki_read_16(ea); /* the 68000 does a dummy read, the value is discarded */
3938 m68ki_write_16(ea, 0);
3940 FLAG_N = NFLAG_CLEAR;
3941 FLAG_V = VFLAG_CLEAR;
3942 FLAG_C = CFLAG_CLEAR;
3947 M68KMAKE_OP(clr, 32, ., d)
3951 FLAG_N = NFLAG_CLEAR;
3952 FLAG_V = VFLAG_CLEAR;
3953 FLAG_C = CFLAG_CLEAR;
3958 M68KMAKE_OP(clr, 32, ., .)
3960 uint32 ea = M68KMAKE_GET_EA_AY_32;
3962 if(CPU_TYPE_IS_000(CPU_TYPE))
3963 m68ki_read_32(ea); /* the 68000 does a dummy read, the value is discarded */
3964 m68ki_write_32(ea, 0);
3966 FLAG_N = NFLAG_CLEAR;
3967 FLAG_V = VFLAG_CLEAR;
3968 FLAG_C = CFLAG_CLEAR;
3973 M68KMAKE_OP(cmp, 8, ., d)
3975 uint src = MASK_OUT_ABOVE_8(DY);
3976 uint dst = MASK_OUT_ABOVE_8(DX);
3977 uint res = dst - src;
3979 FLAG_N = NFLAG_8(res);
3980 FLAG_Z = MASK_OUT_ABOVE_8(res);
3981 FLAG_V = VFLAG_SUB_8(src, dst, res);
3982 FLAG_C = CFLAG_8(res);
3986 M68KMAKE_OP(cmp, 8, ., .)
3988 uint src = M68KMAKE_GET_OPER_AY_8;
3989 uint dst = MASK_OUT_ABOVE_8(DX);
3990 uint res = dst - src;
3992 FLAG_N = NFLAG_8(res);
3993 FLAG_Z = MASK_OUT_ABOVE_8(res);
3994 FLAG_V = VFLAG_SUB_8(src, dst, res);
3995 FLAG_C = CFLAG_8(res);
3999 M68KMAKE_OP(cmp, 16, ., d)
4001 uint src = MASK_OUT_ABOVE_16(DY);
4002 uint dst = MASK_OUT_ABOVE_16(DX);
4003 uint res = dst - src;
4005 FLAG_N = NFLAG_16(res);
4006 FLAG_Z = MASK_OUT_ABOVE_16(res);
4007 FLAG_V = VFLAG_SUB_16(src, dst, res);
4008 FLAG_C = CFLAG_16(res);
4012 M68KMAKE_OP(cmp, 16, ., a)
4014 uint src = MASK_OUT_ABOVE_16(AY);
4015 uint dst = MASK_OUT_ABOVE_16(DX);
4016 uint res = dst - src;
4018 FLAG_N = NFLAG_16(res);
4019 FLAG_Z = MASK_OUT_ABOVE_16(res);
4020 FLAG_V = VFLAG_SUB_16(src, dst, res);
4021 FLAG_C = CFLAG_16(res);
4025 M68KMAKE_OP(cmp, 16, ., .)
4027 uint src = M68KMAKE_GET_OPER_AY_16;
4028 uint dst = MASK_OUT_ABOVE_16(DX);
4029 uint res = dst - src;
4031 FLAG_N = NFLAG_16(res);
4032 FLAG_Z = MASK_OUT_ABOVE_16(res);
4033 FLAG_V = VFLAG_SUB_16(src, dst, res);
4034 FLAG_C = CFLAG_16(res);
4038 M68KMAKE_OP(cmp, 32, ., d)
4042 uint res = dst - src;
4044 FLAG_N = NFLAG_32(res);
4045 FLAG_Z = MASK_OUT_ABOVE_32(res);
4046 FLAG_V = VFLAG_SUB_32(src, dst, res);
4047 FLAG_C = CFLAG_SUB_32(src, dst, res);
4051 M68KMAKE_OP(cmp, 32, ., a)
4055 uint res = dst - src;
4057 FLAG_N = NFLAG_32(res);
4058 FLAG_Z = MASK_OUT_ABOVE_32(res);
4059 FLAG_V = VFLAG_SUB_32(src, dst, res);
4060 FLAG_C = CFLAG_SUB_32(src, dst, res);
4064 M68KMAKE_OP(cmp, 32, ., .)
4066 uint src = M68KMAKE_GET_OPER_AY_32;
4068 uint res = dst - src;
4070 FLAG_N = NFLAG_32(res);
4071 FLAG_Z = MASK_OUT_ABOVE_32(res);
4072 FLAG_V = VFLAG_SUB_32(src, dst, res);
4073 FLAG_C = CFLAG_SUB_32(src, dst, res);
4077 M68KMAKE_OP(cmpa, 16, ., d)
4079 uint src = MAKE_INT_16(DY);
4081 uint res = dst - src;
4083 FLAG_N = NFLAG_32(res);
4084 FLAG_Z = MASK_OUT_ABOVE_32(res);
4085 FLAG_V = VFLAG_SUB_32(src, dst, res);
4086 FLAG_C = CFLAG_SUB_32(src, dst, res);
4090 M68KMAKE_OP(cmpa, 16, ., a)
4092 uint src = MAKE_INT_16(AY);
4094 uint res = dst - src;
4096 FLAG_N = NFLAG_32(res);
4097 FLAG_Z = MASK_OUT_ABOVE_32(res);
4098 FLAG_V = VFLAG_SUB_32(src, dst, res);
4099 FLAG_C = CFLAG_SUB_32(src, dst, res);
4103 M68KMAKE_OP(cmpa, 16, ., .)
4105 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4107 uint res = dst - src;
4109 FLAG_N = NFLAG_32(res);
4110 FLAG_Z = MASK_OUT_ABOVE_32(res);
4111 FLAG_V = VFLAG_SUB_32(src, dst, res);
4112 FLAG_C = CFLAG_SUB_32(src, dst, res);
4116 M68KMAKE_OP(cmpa, 32, ., d)
4120 uint res = dst - src;
4122 FLAG_N = NFLAG_32(res);
4123 FLAG_Z = MASK_OUT_ABOVE_32(res);
4124 FLAG_V = VFLAG_SUB_32(src, dst, res);
4125 FLAG_C = CFLAG_SUB_32(src, dst, res);
4129 M68KMAKE_OP(cmpa, 32, ., a)
4133 uint res = dst - src;
4135 FLAG_N = NFLAG_32(res);
4136 FLAG_Z = MASK_OUT_ABOVE_32(res);
4137 FLAG_V = VFLAG_SUB_32(src, dst, res);
4138 FLAG_C = CFLAG_SUB_32(src, dst, res);
4142 M68KMAKE_OP(cmpa, 32, ., .)
4144 uint src = M68KMAKE_GET_OPER_AY_32;
4146 uint res = dst - src;
4148 FLAG_N = NFLAG_32(res);
4149 FLAG_Z = MASK_OUT_ABOVE_32(res);
4150 FLAG_V = VFLAG_SUB_32(src, dst, res);
4151 FLAG_C = CFLAG_SUB_32(src, dst, res);
4155 M68KMAKE_OP(cmpi, 8, ., d)
4157 uint src = OPER_I_8();
4158 uint dst = MASK_OUT_ABOVE_8(DY);
4159 uint res = dst - src;
4161 FLAG_N = NFLAG_8(res);
4162 FLAG_Z = MASK_OUT_ABOVE_8(res);
4163 FLAG_V = VFLAG_SUB_8(src, dst, res);
4164 FLAG_C = CFLAG_8(res);
4168 M68KMAKE_OP(cmpi, 8, ., .)
4170 uint src = OPER_I_8();
4171 uint dst = M68KMAKE_GET_OPER_AY_8;
4172 uint res = dst - src;
4174 FLAG_N = NFLAG_8(res);
4175 FLAG_Z = MASK_OUT_ABOVE_8(res);
4176 FLAG_V = VFLAG_SUB_8(src, dst, res);
4177 FLAG_C = CFLAG_8(res);
4181 M68KMAKE_OP(cmpi, 8, ., pcdi)
4183 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4185 uint src = OPER_I_8();
4186 uint dst = OPER_PCDI_8();
4187 uint res = dst - src;
4189 FLAG_N = NFLAG_8(res);
4190 FLAG_Z = MASK_OUT_ABOVE_8(res);
4191 FLAG_V = VFLAG_SUB_8(src, dst, res);
4192 FLAG_C = CFLAG_8(res);
4195 m68ki_exception_illegal();
4199 M68KMAKE_OP(cmpi, 8, ., pcix)
4201 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4203 uint src = OPER_I_8();
4204 uint dst = OPER_PCIX_8();
4205 uint res = dst - src;
4207 FLAG_N = NFLAG_8(res);
4208 FLAG_Z = MASK_OUT_ABOVE_8(res);
4209 FLAG_V = VFLAG_SUB_8(src, dst, res);
4210 FLAG_C = CFLAG_8(res);
4213 m68ki_exception_illegal();
4217 M68KMAKE_OP(cmpi, 16, ., d)
4219 uint src = OPER_I_16();
4220 uint dst = MASK_OUT_ABOVE_16(DY);
4221 uint res = dst - src;
4223 FLAG_N = NFLAG_16(res);
4224 FLAG_Z = MASK_OUT_ABOVE_16(res);
4225 FLAG_V = VFLAG_SUB_16(src, dst, res);
4226 FLAG_C = CFLAG_16(res);
4230 M68KMAKE_OP(cmpi, 16, ., .)
4232 uint src = OPER_I_16();
4233 uint dst = M68KMAKE_GET_OPER_AY_16;
4234 uint res = dst - src;
4236 FLAG_N = NFLAG_16(res);
4237 FLAG_Z = MASK_OUT_ABOVE_16(res);
4238 FLAG_V = VFLAG_SUB_16(src, dst, res);
4239 FLAG_C = CFLAG_16(res);
4243 M68KMAKE_OP(cmpi, 16, ., pcdi)
4245 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4247 uint src = OPER_I_16();
4248 uint dst = OPER_PCDI_16();
4249 uint res = dst - src;
4251 FLAG_N = NFLAG_16(res);
4252 FLAG_Z = MASK_OUT_ABOVE_16(res);
4253 FLAG_V = VFLAG_SUB_16(src, dst, res);
4254 FLAG_C = CFLAG_16(res);
4257 m68ki_exception_illegal();
4261 M68KMAKE_OP(cmpi, 16, ., pcix)
4263 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4265 uint src = OPER_I_16();
4266 uint dst = OPER_PCIX_16();
4267 uint res = dst - src;
4269 FLAG_N = NFLAG_16(res);
4270 FLAG_Z = MASK_OUT_ABOVE_16(res);
4271 FLAG_V = VFLAG_SUB_16(src, dst, res);
4272 FLAG_C = CFLAG_16(res);
4275 m68ki_exception_illegal();
4279 M68KMAKE_OP(cmpi, 32, ., d)
4281 uint src = OPER_I_32();
4283 uint res = dst - src;
4285 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
4286 FLAG_N = NFLAG_32(res);
4287 FLAG_Z = MASK_OUT_ABOVE_32(res);
4288 FLAG_V = VFLAG_SUB_32(src, dst, res);
4289 FLAG_C = CFLAG_SUB_32(src, dst, res);
4293 M68KMAKE_OP(cmpi, 32, ., .)
4295 uint src = OPER_I_32();
4296 uint dst = M68KMAKE_GET_OPER_AY_32;
4297 uint res = dst - src;
4299 FLAG_N = NFLAG_32(res);
4300 FLAG_Z = MASK_OUT_ABOVE_32(res);
4301 FLAG_V = VFLAG_SUB_32(src, dst, res);
4302 FLAG_C = CFLAG_SUB_32(src, dst, res);
4306 M68KMAKE_OP(cmpi, 32, ., pcdi)
4308 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4310 uint src = OPER_I_32();
4311 uint dst = OPER_PCDI_32();
4312 uint res = dst - src;
4314 FLAG_N = NFLAG_32(res);
4315 FLAG_Z = MASK_OUT_ABOVE_32(res);
4316 FLAG_V = VFLAG_SUB_32(src, dst, res);
4317 FLAG_C = CFLAG_SUB_32(src, dst, res);
4320 m68ki_exception_illegal();
4324 M68KMAKE_OP(cmpi, 32, ., pcix)
4326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4328 uint src = OPER_I_32();
4329 uint dst = OPER_PCIX_32();
4330 uint res = dst - src;
4332 FLAG_N = NFLAG_32(res);
4333 FLAG_Z = MASK_OUT_ABOVE_32(res);
4334 FLAG_V = VFLAG_SUB_32(src, dst, res);
4335 FLAG_C = CFLAG_SUB_32(src, dst, res);
4338 m68ki_exception_illegal();
4342 M68KMAKE_OP(cmpm, 8, ., ax7)
4344 uint src = OPER_AY_PI_8();
4345 uint dst = OPER_A7_PI_8();
4346 uint res = dst - src;
4348 FLAG_N = NFLAG_8(res);
4349 FLAG_Z = MASK_OUT_ABOVE_8(res);
4350 FLAG_V = VFLAG_SUB_8(src, dst, res);
4351 FLAG_C = CFLAG_8(res);
4355 M68KMAKE_OP(cmpm, 8, ., ay7)
4357 uint src = OPER_A7_PI_8();
4358 uint dst = OPER_AX_PI_8();
4359 uint res = dst - src;
4361 FLAG_N = NFLAG_8(res);
4362 FLAG_Z = MASK_OUT_ABOVE_8(res);
4363 FLAG_V = VFLAG_SUB_8(src, dst, res);
4364 FLAG_C = CFLAG_8(res);
4368 M68KMAKE_OP(cmpm, 8, ., axy7)
4370 uint src = OPER_A7_PI_8();
4371 uint dst = OPER_A7_PI_8();
4372 uint res = dst - src;
4374 FLAG_N = NFLAG_8(res);
4375 FLAG_Z = MASK_OUT_ABOVE_8(res);
4376 FLAG_V = VFLAG_SUB_8(src, dst, res);
4377 FLAG_C = CFLAG_8(res);
4381 M68KMAKE_OP(cmpm, 8, ., .)
4383 uint src = OPER_AY_PI_8();
4384 uint dst = OPER_AX_PI_8();
4385 uint res = dst - src;
4387 FLAG_N = NFLAG_8(res);
4388 FLAG_Z = MASK_OUT_ABOVE_8(res);
4389 FLAG_V = VFLAG_SUB_8(src, dst, res);
4390 FLAG_C = CFLAG_8(res);
4394 M68KMAKE_OP(cmpm, 16, ., .)
4396 uint src = OPER_AY_PI_16();
4397 uint dst = OPER_AX_PI_16();
4398 uint res = dst - src;
4400 FLAG_N = NFLAG_16(res);
4401 FLAG_Z = MASK_OUT_ABOVE_16(res);
4402 FLAG_V = VFLAG_SUB_16(src, dst, res);
4403 FLAG_C = CFLAG_16(res);
4407 M68KMAKE_OP(cmpm, 32, ., .)
4409 uint src = OPER_AY_PI_32();
4410 uint dst = OPER_AX_PI_32();
4411 uint res = dst - src;
4413 FLAG_N = NFLAG_32(res);
4414 FLAG_Z = MASK_OUT_ABOVE_32(res);
4415 FLAG_V = VFLAG_SUB_32(src, dst, res);
4416 FLAG_C = CFLAG_SUB_32(src, dst, res);
4420 M68KMAKE_OP(cpbcc, 32, ., .)
4422 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4424 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4425 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4426 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4429 m68ki_exception_1111();
4433 M68KMAKE_OP(cpdbcc, 32, ., .)
4435 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4437 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4438 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4439 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4442 m68ki_exception_1111();
4446 M68KMAKE_OP(cpgen, 32, ., .)
4448 // TODO: what's the condition?
4449 // if(HAS_FPU || HAS_PMMU)
4450 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4452 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4453 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4454 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4457 m68ki_exception_1111();
4461 M68KMAKE_OP(cpscc, 32, ., .)
4463 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4465 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4466 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4467 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4470 m68ki_exception_1111();
4474 M68KMAKE_OP(cptrapcc, 32, ., .)
4476 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4478 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4479 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4480 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4481 // JFF: unsupported, but at least if the trap doesn't occur, app should still work, so at least PC increase is correct
4485 m68ki_exception_1111();
4488 M68KMAKE_OP(ftrapcc,32, ., .)
4494 m68ki_exception_1111();
4498 M68KMAKE_OP(dbt, 16, ., .)
4504 M68KMAKE_OP(dbf, 16, ., .)
4507 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4509 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4512 uint offset = OPER_I_16();
4514 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4515 m68ki_branch_16(offset);
4516 USE_CYCLES(CYC_DBCC_F_NOEXP);
4520 USE_CYCLES(CYC_DBCC_F_EXP);
4524 M68KMAKE_OP(dbcc, 16, ., .)
4529 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4531 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4534 uint offset = OPER_I_16();
4536 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4537 m68ki_branch_16(offset);
4538 USE_CYCLES(CYC_DBCC_F_NOEXP);
4542 USE_CYCLES(CYC_DBCC_F_EXP);
4549 M68KMAKE_OP(divs, 16, ., d)
4552 sint src = MAKE_INT_16(DY);
4558 FLAG_C = CFLAG_CLEAR;
4559 if((uint32)*r_dst == 0x80000000 && src == -1)
4562 FLAG_N = NFLAG_CLEAR;
4563 FLAG_V = VFLAG_CLEAR;
4568 quotient = MAKE_INT_32(*r_dst) / src;
4569 remainder = MAKE_INT_32(*r_dst) % src;
4571 if(quotient == MAKE_INT_16(quotient))
4574 FLAG_N = NFLAG_16(quotient);
4575 FLAG_V = VFLAG_CLEAR;
4576 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4582 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4586 M68KMAKE_OP(divs, 16, ., .)
4589 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4595 FLAG_C = CFLAG_CLEAR;
4596 if((uint32)*r_dst == 0x80000000 && src == -1)
4599 FLAG_N = NFLAG_CLEAR;
4600 FLAG_V = VFLAG_CLEAR;
4605 quotient = MAKE_INT_32(*r_dst) / src;
4606 remainder = MAKE_INT_32(*r_dst) % src;
4608 if(quotient == MAKE_INT_16(quotient))
4611 FLAG_N = NFLAG_16(quotient);
4612 FLAG_V = VFLAG_CLEAR;
4613 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4619 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4623 M68KMAKE_OP(divu, 16, ., d)
4626 uint src = MASK_OUT_ABOVE_16(DY);
4630 FLAG_C = CFLAG_CLEAR;
4631 uint quotient = *r_dst / src;
4632 uint remainder = *r_dst % src;
4634 if(quotient < 0x10000)
4637 FLAG_N = NFLAG_16(quotient);
4638 FLAG_V = VFLAG_CLEAR;
4639 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4645 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4649 M68KMAKE_OP(divu, 16, ., .)
4652 uint src = M68KMAKE_GET_OPER_AY_16;
4656 FLAG_C = CFLAG_CLEAR;
4657 uint quotient = *r_dst / src;
4658 uint remainder = *r_dst % src;
4660 if(quotient < 0x10000)
4663 FLAG_N = NFLAG_16(quotient);
4664 FLAG_V = VFLAG_CLEAR;
4665 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4671 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4675 M68KMAKE_OP(divl, 32, ., d)
4679 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4681 uint word2 = OPER_I_16();
4682 uint64 divisor = DY;
4683 uint64 dividend = 0;
4684 uint64 quotient = 0;
4685 uint64 remainder = 0;
4689 if(BIT_A(word2)) /* 64 bit */
4691 dividend = REG_D[word2 & 7];
4693 dividend |= REG_D[(word2 >> 12) & 7];
4695 if(BIT_B(word2)) /* signed */
4697 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4698 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4699 if((sint64)quotient != (sint64)((sint32)quotient))
4707 quotient = dividend / divisor;
4708 if(quotient > 0xffffffff)
4713 remainder = dividend % divisor;
4718 dividend = REG_D[(word2 >> 12) & 7];
4719 if(BIT_B(word2)) /* signed */
4721 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4722 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4726 quotient = dividend / divisor;
4727 remainder = dividend % divisor;
4731 REG_D[word2 & 7] = remainder;
4732 REG_D[(word2 >> 12) & 7] = quotient;
4734 FLAG_N = NFLAG_32(quotient);
4736 FLAG_V = VFLAG_CLEAR;
4737 FLAG_C = CFLAG_CLEAR;
4740 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4743 m68ki_exception_illegal();
4747 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4749 uint word2 = OPER_I_16();
4751 uint dividend_hi = REG_D[word2 & 7];
4752 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4755 uint dividend_neg = 0;
4756 uint divisor_neg = 0;
4762 /* quad / long : long quotient, long remainder */
4765 if(BIT_B(word2)) /* signed */
4767 /* special case in signed divide */
4768 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4770 REG_D[word2 & 7] = 0;
4771 REG_D[(word2 >> 12) & 7] = 0x80000000;
4774 FLAG_Z = ZFLAG_CLEAR;
4775 FLAG_V = VFLAG_CLEAR;
4776 FLAG_C = CFLAG_CLEAR;
4779 if(GET_MSB_32(dividend_hi))
4782 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4783 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4785 if(GET_MSB_32(divisor))
4788 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4793 /* if the upper long is greater than the divisor, we're overflowing. */
4794 if(dividend_hi >= divisor)
4800 for(i = 31; i >= 0; i--)
4803 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4804 if(remainder >= divisor)
4806 remainder -= divisor;
4810 for(i = 31; i >= 0; i--)
4813 overflow = GET_MSB_32(remainder);
4814 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4815 if(remainder >= divisor || overflow)
4817 remainder -= divisor;
4822 if(BIT_B(word2)) /* signed */
4824 if(quotient > 0x7fffffff)
4831 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4832 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4835 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4838 REG_D[word2 & 7] = remainder;
4839 REG_D[(word2 >> 12) & 7] = quotient;
4841 FLAG_N = NFLAG_32(quotient);
4843 FLAG_V = VFLAG_CLEAR;
4844 FLAG_C = CFLAG_CLEAR;
4848 /* long / long: long quotient, maybe long remainder */
4849 if(BIT_B(word2)) /* signed */
4851 /* Special case in divide */
4852 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4855 FLAG_Z = ZFLAG_CLEAR;
4856 FLAG_V = VFLAG_CLEAR;
4857 FLAG_C = CFLAG_CLEAR;
4858 REG_D[(word2 >> 12) & 7] = 0x80000000;
4859 REG_D[word2 & 7] = 0;
4862 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4863 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4867 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4868 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4871 FLAG_N = NFLAG_32(quotient);
4873 FLAG_V = VFLAG_CLEAR;
4874 FLAG_C = CFLAG_CLEAR;
4877 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4880 m68ki_exception_illegal();
4886 M68KMAKE_OP(divl, 32, ., .)
4890 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4892 uint word2 = OPER_I_16();
4893 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
4894 uint64 dividend = 0;
4895 uint64 quotient = 0;
4896 uint64 remainder = 0;
4900 if(BIT_A(word2)) /* 64 bit */
4902 dividend = REG_D[word2 & 7];
4904 dividend |= REG_D[(word2 >> 12) & 7];
4906 if(BIT_B(word2)) /* signed */
4908 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4909 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4910 if((sint64)quotient != (sint64)((sint32)quotient))
4918 quotient = dividend / divisor;
4919 if(quotient > 0xffffffff)
4924 remainder = dividend % divisor;
4929 dividend = REG_D[(word2 >> 12) & 7];
4930 if(BIT_B(word2)) /* signed */
4932 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4933 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4937 quotient = dividend / divisor;
4938 remainder = dividend % divisor;
4942 REG_D[word2 & 7] = remainder;
4943 REG_D[(word2 >> 12) & 7] = quotient;
4945 FLAG_N = NFLAG_32(quotient);
4947 FLAG_V = VFLAG_CLEAR;
4948 FLAG_C = CFLAG_CLEAR;
4951 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4954 m68ki_exception_illegal();
4958 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4960 uint word2 = OPER_I_16();
4961 uint divisor = M68KMAKE_GET_OPER_AY_32;
4962 uint dividend_hi = REG_D[word2 & 7];
4963 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4966 uint dividend_neg = 0;
4967 uint divisor_neg = 0;
4973 /* quad / long : long quotient, long remainder */
4976 if(BIT_B(word2)) /* signed */
4978 /* special case in signed divide */
4979 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4981 REG_D[word2 & 7] = 0;
4982 REG_D[(word2 >> 12) & 7] = 0x80000000;
4985 FLAG_Z = ZFLAG_CLEAR;
4986 FLAG_V = VFLAG_CLEAR;
4987 FLAG_C = CFLAG_CLEAR;
4990 if(GET_MSB_32(dividend_hi))
4993 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4994 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4996 if(GET_MSB_32(divisor))
4999 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
5004 /* if the upper long is greater than the divisor, we're overflowing. */
5005 if(dividend_hi >= divisor)
5011 for(i = 31; i >= 0; i--)
5014 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
5015 if(remainder >= divisor)
5017 remainder -= divisor;
5021 for(i = 31; i >= 0; i--)
5024 overflow = GET_MSB_32(remainder);
5025 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
5026 if(remainder >= divisor || overflow)
5028 remainder -= divisor;
5033 if(BIT_B(word2)) /* signed */
5035 if(quotient > 0x7fffffff)
5042 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
5043 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
5046 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
5049 REG_D[word2 & 7] = remainder;
5050 REG_D[(word2 >> 12) & 7] = quotient;
5052 FLAG_N = NFLAG_32(quotient);
5054 FLAG_V = VFLAG_CLEAR;
5055 FLAG_C = CFLAG_CLEAR;
5059 /* long / long: long quotient, maybe long remainder */
5060 if(BIT_B(word2)) /* signed */
5062 /* Special case in divide */
5063 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
5066 FLAG_Z = ZFLAG_CLEAR;
5067 FLAG_V = VFLAG_CLEAR;
5068 FLAG_C = CFLAG_CLEAR;
5069 REG_D[(word2 >> 12) & 7] = 0x80000000;
5070 REG_D[word2 & 7] = 0;
5073 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
5074 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
5078 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
5079 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
5082 FLAG_N = NFLAG_32(quotient);
5084 FLAG_V = VFLAG_CLEAR;
5085 FLAG_C = CFLAG_CLEAR;
5088 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
5091 m68ki_exception_illegal();
5097 M68KMAKE_OP(eor, 8, ., d)
5099 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
5101 FLAG_N = NFLAG_8(res);
5103 FLAG_C = CFLAG_CLEAR;
5104 FLAG_V = VFLAG_CLEAR;
5108 M68KMAKE_OP(eor, 8, ., .)
5110 uint ea = M68KMAKE_GET_EA_AY_8;
5111 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
5113 m68ki_write_8(ea, res);
5115 FLAG_N = NFLAG_8(res);
5117 FLAG_C = CFLAG_CLEAR;
5118 FLAG_V = VFLAG_CLEAR;
5122 M68KMAKE_OP(eor, 16, ., d)
5124 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
5126 FLAG_N = NFLAG_16(res);
5128 FLAG_C = CFLAG_CLEAR;
5129 FLAG_V = VFLAG_CLEAR;
5133 M68KMAKE_OP(eor, 16, ., .)
5135 uint ea = M68KMAKE_GET_EA_AY_16;
5136 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
5138 m68ki_write_16(ea, res);
5140 FLAG_N = NFLAG_16(res);
5142 FLAG_C = CFLAG_CLEAR;
5143 FLAG_V = VFLAG_CLEAR;
5147 M68KMAKE_OP(eor, 32, ., d)
5149 uint res = DY ^= DX;
5151 FLAG_N = NFLAG_32(res);
5153 FLAG_C = CFLAG_CLEAR;
5154 FLAG_V = VFLAG_CLEAR;
5158 M68KMAKE_OP(eor, 32, ., .)
5160 uint ea = M68KMAKE_GET_EA_AY_32;
5161 uint res = DX ^ m68ki_read_32(ea);
5163 m68ki_write_32(ea, res);
5165 FLAG_N = NFLAG_32(res);
5167 FLAG_C = CFLAG_CLEAR;
5168 FLAG_V = VFLAG_CLEAR;
5172 M68KMAKE_OP(eori, 8, ., d)
5174 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
5176 FLAG_N = NFLAG_8(res);
5178 FLAG_C = CFLAG_CLEAR;
5179 FLAG_V = VFLAG_CLEAR;
5183 M68KMAKE_OP(eori, 8, ., .)
5185 uint src = OPER_I_8();
5186 uint ea = M68KMAKE_GET_EA_AY_8;
5187 uint res = src ^ m68ki_read_8(ea);
5189 m68ki_write_8(ea, res);
5191 FLAG_N = NFLAG_8(res);
5193 FLAG_C = CFLAG_CLEAR;
5194 FLAG_V = VFLAG_CLEAR;
5198 M68KMAKE_OP(eori, 16, ., d)
5200 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
5202 FLAG_N = NFLAG_16(res);
5204 FLAG_C = CFLAG_CLEAR;
5205 FLAG_V = VFLAG_CLEAR;
5209 M68KMAKE_OP(eori, 16, ., .)
5211 uint src = OPER_I_16();
5212 uint ea = M68KMAKE_GET_EA_AY_16;
5213 uint res = src ^ m68ki_read_16(ea);
5215 m68ki_write_16(ea, res);
5217 FLAG_N = NFLAG_16(res);
5219 FLAG_C = CFLAG_CLEAR;
5220 FLAG_V = VFLAG_CLEAR;
5224 M68KMAKE_OP(eori, 32, ., d)
5226 uint res = DY ^= OPER_I_32();
5228 FLAG_N = NFLAG_32(res);
5230 FLAG_C = CFLAG_CLEAR;
5231 FLAG_V = VFLAG_CLEAR;
5235 M68KMAKE_OP(eori, 32, ., .)
5237 uint src = OPER_I_32();
5238 uint ea = M68KMAKE_GET_EA_AY_32;
5239 uint res = src ^ m68ki_read_32(ea);
5241 m68ki_write_32(ea, res);
5243 FLAG_N = NFLAG_32(res);
5245 FLAG_C = CFLAG_CLEAR;
5246 FLAG_V = VFLAG_CLEAR;
5250 M68KMAKE_OP(eori, 16, toc, .)
5252 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8());
5256 M68KMAKE_OP(eori, 16, tos, .)
5260 uint src = OPER_I_16();
5261 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5262 m68ki_set_sr(m68ki_get_sr() ^ src);
5265 m68ki_exception_privilege_violation();
5269 M68KMAKE_OP(exg, 32, dd, .)
5279 M68KMAKE_OP(exg, 32, aa, .)
5289 M68KMAKE_OP(exg, 32, da, .)
5299 M68KMAKE_OP(ext, 16, ., .)
5303 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
5305 FLAG_N = NFLAG_16(*r_dst);
5306 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
5307 FLAG_V = VFLAG_CLEAR;
5308 FLAG_C = CFLAG_CLEAR;
5312 M68KMAKE_OP(ext, 32, ., .)
5316 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
5318 FLAG_N = NFLAG_32(*r_dst);
5320 FLAG_V = VFLAG_CLEAR;
5321 FLAG_C = CFLAG_CLEAR;
5325 M68KMAKE_OP(extb, 32, ., .)
5327 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5331 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
5333 FLAG_N = NFLAG_32(*r_dst);
5335 FLAG_V = VFLAG_CLEAR;
5336 FLAG_C = CFLAG_CLEAR;
5339 m68ki_exception_illegal();
5343 M68KMAKE_OP(illegal, 0, ., .)
5345 m68ki_exception_illegal();
5348 M68KMAKE_OP(jmp, 32, ., .)
5350 m68ki_jump(M68KMAKE_GET_EA_AY_32);
5351 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5355 M68KMAKE_OP(jsr, 32, ., .)
5357 uint ea = M68KMAKE_GET_EA_AY_32;
5358 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5359 m68ki_push_32(REG_PC);
5364 M68KMAKE_OP(lea, 32, ., .)
5366 AX = M68KMAKE_GET_EA_AY_32;
5370 M68KMAKE_OP(link, 16, ., a7)
5373 m68ki_write_32(REG_A[7], REG_A[7]);
5374 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5378 M68KMAKE_OP(link, 16, ., .)
5382 m68ki_push_32(*r_dst);
5384 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5388 M68KMAKE_OP(link, 32, ., a7)
5390 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5393 m68ki_write_32(REG_A[7], REG_A[7]);
5394 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5397 m68ki_exception_illegal();
5401 M68KMAKE_OP(link, 32, ., .)
5403 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5407 m68ki_push_32(*r_dst);
5409 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5412 m68ki_exception_illegal();
5416 M68KMAKE_OP(lsr, 8, s, .)
5419 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5420 uint src = MASK_OUT_ABOVE_8(*r_dst);
5421 uint res = src >> shift;
5424 USE_CYCLES(shift<<CYC_SHIFT);
5426 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5428 FLAG_N = NFLAG_CLEAR;
5430 FLAG_X = FLAG_C = src << (9-shift);
5431 FLAG_V = VFLAG_CLEAR;
5435 M68KMAKE_OP(lsr, 16, s, .)
5438 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5439 uint src = MASK_OUT_ABOVE_16(*r_dst);
5440 uint res = src >> shift;
5443 USE_CYCLES(shift<<CYC_SHIFT);
5445 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5447 FLAG_N = NFLAG_CLEAR;
5449 FLAG_X = FLAG_C = src << (9-shift);
5450 FLAG_V = VFLAG_CLEAR;
5454 M68KMAKE_OP(lsr, 32, s, .)
5457 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5459 uint res = src >> shift;
5462 USE_CYCLES(shift<<CYC_SHIFT);
5466 FLAG_N = NFLAG_CLEAR;
5468 FLAG_X = FLAG_C = src << (9-shift);
5469 FLAG_V = VFLAG_CLEAR;
5473 M68KMAKE_OP(lsr, 8, r, .)
5476 uint shift = DX & 0x3f;
5477 uint src = MASK_OUT_ABOVE_8(*r_dst);
5478 uint res = src >> shift;
5482 USE_CYCLES(shift<<CYC_SHIFT);
5486 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5487 FLAG_X = FLAG_C = src << (9-shift);
5488 FLAG_N = NFLAG_CLEAR;
5490 FLAG_V = VFLAG_CLEAR;
5494 *r_dst &= 0xffffff00;
5495 FLAG_X = XFLAG_CLEAR;
5496 FLAG_C = CFLAG_CLEAR;
5497 FLAG_N = NFLAG_CLEAR;
5499 FLAG_V = VFLAG_CLEAR;
5503 FLAG_C = CFLAG_CLEAR;
5504 FLAG_N = NFLAG_8(src);
5506 FLAG_V = VFLAG_CLEAR;
5510 M68KMAKE_OP(lsr, 16, r, .)
5513 uint shift = DX & 0x3f;
5514 uint src = MASK_OUT_ABOVE_16(*r_dst);
5515 uint res = src >> shift;
5519 USE_CYCLES(shift<<CYC_SHIFT);
5523 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5524 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5525 FLAG_N = NFLAG_CLEAR;
5527 FLAG_V = VFLAG_CLEAR;
5531 *r_dst &= 0xffff0000;
5532 FLAG_X = XFLAG_CLEAR;
5533 FLAG_C = CFLAG_CLEAR;
5534 FLAG_N = NFLAG_CLEAR;
5536 FLAG_V = VFLAG_CLEAR;
5540 FLAG_C = CFLAG_CLEAR;
5541 FLAG_N = NFLAG_16(src);
5543 FLAG_V = VFLAG_CLEAR;
5547 M68KMAKE_OP(lsr, 32, r, .)
5550 uint shift = DX & 0x3f;
5552 uint res = src >> shift;
5556 USE_CYCLES(shift<<CYC_SHIFT);
5561 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5562 FLAG_N = NFLAG_CLEAR;
5564 FLAG_V = VFLAG_CLEAR;
5569 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
5570 FLAG_N = NFLAG_CLEAR;
5572 FLAG_V = VFLAG_CLEAR;
5576 FLAG_C = CFLAG_CLEAR;
5577 FLAG_N = NFLAG_32(src);
5579 FLAG_V = VFLAG_CLEAR;
5583 M68KMAKE_OP(lsr, 16, ., .)
5585 uint ea = M68KMAKE_GET_EA_AY_16;
5586 uint src = m68ki_read_16(ea);
5587 uint res = src >> 1;
5589 m68ki_write_16(ea, res);
5591 FLAG_N = NFLAG_CLEAR;
5593 FLAG_C = FLAG_X = src << 8;
5594 FLAG_V = VFLAG_CLEAR;
5598 M68KMAKE_OP(lsl, 8, s, .)
5601 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5602 uint src = MASK_OUT_ABOVE_8(*r_dst);
5603 uint res = MASK_OUT_ABOVE_8(src << shift);
5606 USE_CYCLES(shift<<CYC_SHIFT);
5608 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5610 FLAG_N = NFLAG_8(res);
5612 FLAG_X = FLAG_C = src << shift;
5613 FLAG_V = VFLAG_CLEAR;
5617 M68KMAKE_OP(lsl, 16, s, .)
5620 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5621 uint src = MASK_OUT_ABOVE_16(*r_dst);
5622 uint res = MASK_OUT_ABOVE_16(src << shift);
5625 USE_CYCLES(shift<<CYC_SHIFT);
5627 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5629 FLAG_N = NFLAG_16(res);
5631 FLAG_X = FLAG_C = src >> (8-shift);
5632 FLAG_V = VFLAG_CLEAR;
5636 M68KMAKE_OP(lsl, 32, s, .)
5639 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5641 uint res = MASK_OUT_ABOVE_32(src << shift);
5644 USE_CYCLES(shift<<CYC_SHIFT);
5648 FLAG_N = NFLAG_32(res);
5650 FLAG_X = FLAG_C = src >> (24-shift);
5651 FLAG_V = VFLAG_CLEAR;
5655 M68KMAKE_OP(lsl, 8, r, .)
5658 uint shift = DX & 0x3f;
5659 uint src = MASK_OUT_ABOVE_8(*r_dst);
5660 uint res = MASK_OUT_ABOVE_8(src << shift);
5664 USE_CYCLES(shift<<CYC_SHIFT);
5668 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5669 FLAG_X = FLAG_C = src << shift;
5670 FLAG_N = NFLAG_8(res);
5672 FLAG_V = VFLAG_CLEAR;
5676 *r_dst &= 0xffffff00;
5677 FLAG_X = XFLAG_CLEAR;
5678 FLAG_C = CFLAG_CLEAR;
5679 FLAG_N = NFLAG_CLEAR;
5681 FLAG_V = VFLAG_CLEAR;
5685 FLAG_C = CFLAG_CLEAR;
5686 FLAG_N = NFLAG_8(src);
5688 FLAG_V = VFLAG_CLEAR;
5692 M68KMAKE_OP(lsl, 16, r, .)
5695 uint shift = DX & 0x3f;
5696 uint src = MASK_OUT_ABOVE_16(*r_dst);
5697 uint res = MASK_OUT_ABOVE_16(src << shift);
5701 USE_CYCLES(shift<<CYC_SHIFT);
5705 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5706 FLAG_X = FLAG_C = (src << shift) >> 8;
5707 FLAG_N = NFLAG_16(res);
5709 FLAG_V = VFLAG_CLEAR;
5713 *r_dst &= 0xffff0000;
5714 FLAG_X = XFLAG_CLEAR;
5715 FLAG_C = CFLAG_CLEAR;
5716 FLAG_N = NFLAG_CLEAR;
5718 FLAG_V = VFLAG_CLEAR;
5722 FLAG_C = CFLAG_CLEAR;
5723 FLAG_N = NFLAG_16(src);
5725 FLAG_V = VFLAG_CLEAR;
5729 M68KMAKE_OP(lsl, 32, r, .)
5732 uint shift = DX & 0x3f;
5734 uint res = MASK_OUT_ABOVE_32(src << shift);
5738 USE_CYCLES(shift<<CYC_SHIFT);
5743 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
5744 FLAG_N = NFLAG_32(res);
5746 FLAG_V = VFLAG_CLEAR;
5751 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
5752 FLAG_N = NFLAG_CLEAR;
5754 FLAG_V = VFLAG_CLEAR;
5758 FLAG_C = CFLAG_CLEAR;
5759 FLAG_N = NFLAG_32(src);
5761 FLAG_V = VFLAG_CLEAR;
5765 M68KMAKE_OP(lsl, 16, ., .)
5767 uint ea = M68KMAKE_GET_EA_AY_16;
5768 uint src = m68ki_read_16(ea);
5769 uint res = MASK_OUT_ABOVE_16(src << 1);
5771 m68ki_write_16(ea, res);
5773 FLAG_N = NFLAG_16(res);
5775 FLAG_X = FLAG_C = src >> 7;
5776 FLAG_V = VFLAG_CLEAR;
5780 M68KMAKE_OP(move, 8, d, d)
5782 uint res = MASK_OUT_ABOVE_8(DY);
5785 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5787 FLAG_N = NFLAG_8(res);
5789 FLAG_V = VFLAG_CLEAR;
5790 FLAG_C = CFLAG_CLEAR;
5794 M68KMAKE_OP(move, 8, d, .)
5796 uint res = M68KMAKE_GET_OPER_AY_8;
5799 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5801 FLAG_N = NFLAG_8(res);
5803 FLAG_V = VFLAG_CLEAR;
5804 FLAG_C = CFLAG_CLEAR;
5808 M68KMAKE_OP(move, 8, ai, d)
5810 uint res = MASK_OUT_ABOVE_8(DY);
5811 uint ea = EA_AX_AI_8();
5813 m68ki_write_8(ea, res);
5815 FLAG_N = NFLAG_8(res);
5817 FLAG_V = VFLAG_CLEAR;
5818 FLAG_C = CFLAG_CLEAR;
5822 M68KMAKE_OP(move, 8, ai, .)
5824 uint res = M68KMAKE_GET_OPER_AY_8;
5825 uint ea = EA_AX_AI_8();
5827 m68ki_write_8(ea, res);
5829 FLAG_N = NFLAG_8(res);
5831 FLAG_V = VFLAG_CLEAR;
5832 FLAG_C = CFLAG_CLEAR;
5836 M68KMAKE_OP(move, 8, pi7, d)
5838 uint res = MASK_OUT_ABOVE_8(DY);
5839 uint ea = EA_A7_PI_8();
5841 m68ki_write_8(ea, res);
5843 FLAG_N = NFLAG_8(res);
5845 FLAG_V = VFLAG_CLEAR;
5846 FLAG_C = CFLAG_CLEAR;
5850 M68KMAKE_OP(move, 8, pi, d)
5852 uint res = MASK_OUT_ABOVE_8(DY);
5853 uint ea = EA_AX_PI_8();
5855 m68ki_write_8(ea, res);
5857 FLAG_N = NFLAG_8(res);
5859 FLAG_V = VFLAG_CLEAR;
5860 FLAG_C = CFLAG_CLEAR;
5864 M68KMAKE_OP(move, 8, pi7, .)
5866 uint res = M68KMAKE_GET_OPER_AY_8;
5867 uint ea = EA_A7_PI_8();
5869 m68ki_write_8(ea, res);
5871 FLAG_N = NFLAG_8(res);
5873 FLAG_V = VFLAG_CLEAR;
5874 FLAG_C = CFLAG_CLEAR;
5878 M68KMAKE_OP(move, 8, pi, .)
5880 uint res = M68KMAKE_GET_OPER_AY_8;
5881 uint ea = EA_AX_PI_8();
5883 m68ki_write_8(ea, res);
5885 FLAG_N = NFLAG_8(res);
5887 FLAG_V = VFLAG_CLEAR;
5888 FLAG_C = CFLAG_CLEAR;
5892 M68KMAKE_OP(move, 8, pd7, d)
5894 uint res = MASK_OUT_ABOVE_8(DY);
5895 uint ea = EA_A7_PD_8();
5897 m68ki_write_8(ea, res);
5899 FLAG_N = NFLAG_8(res);
5901 FLAG_V = VFLAG_CLEAR;
5902 FLAG_C = CFLAG_CLEAR;
5906 M68KMAKE_OP(move, 8, pd, d)
5908 uint res = MASK_OUT_ABOVE_8(DY);
5909 uint ea = EA_AX_PD_8();
5911 m68ki_write_8(ea, res);
5913 FLAG_N = NFLAG_8(res);
5915 FLAG_V = VFLAG_CLEAR;
5916 FLAG_C = CFLAG_CLEAR;
5920 M68KMAKE_OP(move, 8, pd7, .)
5922 uint res = M68KMAKE_GET_OPER_AY_8;
5923 uint ea = EA_A7_PD_8();
5925 m68ki_write_8(ea, res);
5927 FLAG_N = NFLAG_8(res);
5929 FLAG_V = VFLAG_CLEAR;
5930 FLAG_C = CFLAG_CLEAR;
5934 M68KMAKE_OP(move, 8, pd, .)
5936 uint res = M68KMAKE_GET_OPER_AY_8;
5937 uint ea = EA_AX_PD_8();
5939 m68ki_write_8(ea, res);
5941 FLAG_N = NFLAG_8(res);
5943 FLAG_V = VFLAG_CLEAR;
5944 FLAG_C = CFLAG_CLEAR;
5948 M68KMAKE_OP(move, 8, di, d)
5950 uint res = MASK_OUT_ABOVE_8(DY);
5951 uint ea = EA_AX_DI_8();
5953 m68ki_write_8(ea, res);
5955 FLAG_N = NFLAG_8(res);
5957 FLAG_V = VFLAG_CLEAR;
5958 FLAG_C = CFLAG_CLEAR;
5962 M68KMAKE_OP(move, 8, di, .)
5964 uint res = M68KMAKE_GET_OPER_AY_8;
5965 uint ea = EA_AX_DI_8();
5967 m68ki_write_8(ea, res);
5969 FLAG_N = NFLAG_8(res);
5971 FLAG_V = VFLAG_CLEAR;
5972 FLAG_C = CFLAG_CLEAR;
5976 M68KMAKE_OP(move, 8, ix, d)
5978 uint res = MASK_OUT_ABOVE_8(DY);
5979 uint ea = EA_AX_IX_8();
5981 m68ki_write_8(ea, res);
5983 FLAG_N = NFLAG_8(res);
5985 FLAG_V = VFLAG_CLEAR;
5986 FLAG_C = CFLAG_CLEAR;
5990 M68KMAKE_OP(move, 8, ix, .)
5992 uint res = M68KMAKE_GET_OPER_AY_8;
5993 uint ea = EA_AX_IX_8();
5995 m68ki_write_8(ea, res);
5997 FLAG_N = NFLAG_8(res);
5999 FLAG_V = VFLAG_CLEAR;
6000 FLAG_C = CFLAG_CLEAR;
6004 M68KMAKE_OP(move, 8, aw, d)
6006 uint res = MASK_OUT_ABOVE_8(DY);
6007 uint ea = EA_AW_8();
6009 m68ki_write_8(ea, res);
6011 FLAG_N = NFLAG_8(res);
6013 FLAG_V = VFLAG_CLEAR;
6014 FLAG_C = CFLAG_CLEAR;
6018 M68KMAKE_OP(move, 8, aw, .)
6020 uint res = M68KMAKE_GET_OPER_AY_8;
6021 uint ea = EA_AW_8();
6023 m68ki_write_8(ea, res);
6025 FLAG_N = NFLAG_8(res);
6027 FLAG_V = VFLAG_CLEAR;
6028 FLAG_C = CFLAG_CLEAR;
6032 M68KMAKE_OP(move, 8, al, d)
6034 uint res = MASK_OUT_ABOVE_8(DY);
6035 uint ea = EA_AL_8();
6037 m68ki_write_8(ea, res);
6039 FLAG_N = NFLAG_8(res);
6041 FLAG_V = VFLAG_CLEAR;
6042 FLAG_C = CFLAG_CLEAR;
6046 M68KMAKE_OP(move, 8, al, .)
6048 uint res = M68KMAKE_GET_OPER_AY_8;
6049 uint ea = EA_AL_8();
6051 m68ki_write_8(ea, res);
6053 FLAG_N = NFLAG_8(res);
6055 FLAG_V = VFLAG_CLEAR;
6056 FLAG_C = CFLAG_CLEAR;
6060 M68KMAKE_OP(move, 16, d, d)
6062 uint res = MASK_OUT_ABOVE_16(DY);
6065 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
6067 FLAG_N = NFLAG_16(res);
6069 FLAG_V = VFLAG_CLEAR;
6070 FLAG_C = CFLAG_CLEAR;
6074 M68KMAKE_OP(move, 16, d, a)
6076 uint res = MASK_OUT_ABOVE_16(AY);
6079 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
6081 FLAG_N = NFLAG_16(res);
6083 FLAG_V = VFLAG_CLEAR;
6084 FLAG_C = CFLAG_CLEAR;
6088 M68KMAKE_OP(move, 16, d, .)
6090 uint res = M68KMAKE_GET_OPER_AY_16;
6093 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
6095 FLAG_N = NFLAG_16(res);
6097 FLAG_V = VFLAG_CLEAR;
6098 FLAG_C = CFLAG_CLEAR;
6102 M68KMAKE_OP(move, 16, ai, d)
6104 uint res = MASK_OUT_ABOVE_16(DY);
6105 uint ea = EA_AX_AI_16();
6107 m68ki_write_16(ea, res);
6109 FLAG_N = NFLAG_16(res);
6111 FLAG_V = VFLAG_CLEAR;
6112 FLAG_C = CFLAG_CLEAR;
6116 M68KMAKE_OP(move, 16, ai, a)
6118 uint res = MASK_OUT_ABOVE_16(AY);
6119 uint ea = EA_AX_AI_16();
6121 m68ki_write_16(ea, res);
6123 FLAG_N = NFLAG_16(res);
6125 FLAG_V = VFLAG_CLEAR;
6126 FLAG_C = CFLAG_CLEAR;
6130 M68KMAKE_OP(move, 16, ai, .)
6132 uint res = M68KMAKE_GET_OPER_AY_16;
6133 uint ea = EA_AX_AI_16();
6135 m68ki_write_16(ea, res);
6137 FLAG_N = NFLAG_16(res);
6139 FLAG_V = VFLAG_CLEAR;
6140 FLAG_C = CFLAG_CLEAR;
6144 M68KMAKE_OP(move, 16, pi, d)
6146 uint res = MASK_OUT_ABOVE_16(DY);
6147 uint ea = EA_AX_PI_16();
6149 m68ki_write_16(ea, res);
6151 FLAG_N = NFLAG_16(res);
6153 FLAG_V = VFLAG_CLEAR;
6154 FLAG_C = CFLAG_CLEAR;
6158 M68KMAKE_OP(move, 16, pi, a)
6160 uint res = MASK_OUT_ABOVE_16(AY);
6161 uint ea = EA_AX_PI_16();
6163 m68ki_write_16(ea, res);
6165 FLAG_N = NFLAG_16(res);
6167 FLAG_V = VFLAG_CLEAR;
6168 FLAG_C = CFLAG_CLEAR;
6172 M68KMAKE_OP(move, 16, pi, .)
6174 uint res = M68KMAKE_GET_OPER_AY_16;
6175 uint ea = EA_AX_PI_16();
6177 m68ki_write_16(ea, res);
6179 FLAG_N = NFLAG_16(res);
6181 FLAG_V = VFLAG_CLEAR;
6182 FLAG_C = CFLAG_CLEAR;
6186 M68KMAKE_OP(move, 16, pd, d)
6188 uint res = MASK_OUT_ABOVE_16(DY);
6189 uint ea = EA_AX_PD_16();
6191 m68ki_write_16(ea, res);
6193 FLAG_N = NFLAG_16(res);
6195 FLAG_V = VFLAG_CLEAR;
6196 FLAG_C = CFLAG_CLEAR;
6200 M68KMAKE_OP(move, 16, pd, a)
6202 uint res = MASK_OUT_ABOVE_16(AY);
6203 uint ea = EA_AX_PD_16();
6205 m68ki_write_16(ea, res);
6207 FLAG_N = NFLAG_16(res);
6209 FLAG_V = VFLAG_CLEAR;
6210 FLAG_C = CFLAG_CLEAR;
6214 M68KMAKE_OP(move, 16, pd, .)
6216 uint res = M68KMAKE_GET_OPER_AY_16;
6217 uint ea = EA_AX_PD_16();
6219 m68ki_write_16(ea, res);
6221 FLAG_N = NFLAG_16(res);
6223 FLAG_V = VFLAG_CLEAR;
6224 FLAG_C = CFLAG_CLEAR;
6228 M68KMAKE_OP(move, 16, di, d)
6230 uint res = MASK_OUT_ABOVE_16(DY);
6231 uint ea = EA_AX_DI_16();
6233 m68ki_write_16(ea, res);
6235 FLAG_N = NFLAG_16(res);
6237 FLAG_V = VFLAG_CLEAR;
6238 FLAG_C = CFLAG_CLEAR;
6242 M68KMAKE_OP(move, 16, di, a)
6244 uint res = MASK_OUT_ABOVE_16(AY);
6245 uint ea = EA_AX_DI_16();
6247 m68ki_write_16(ea, res);
6249 FLAG_N = NFLAG_16(res);
6251 FLAG_V = VFLAG_CLEAR;
6252 FLAG_C = CFLAG_CLEAR;
6256 M68KMAKE_OP(move, 16, di, .)
6258 uint res = M68KMAKE_GET_OPER_AY_16;
6259 uint ea = EA_AX_DI_16();
6261 m68ki_write_16(ea, res);
6263 FLAG_N = NFLAG_16(res);
6265 FLAG_V = VFLAG_CLEAR;
6266 FLAG_C = CFLAG_CLEAR;
6270 M68KMAKE_OP(move, 16, ix, d)
6272 uint res = MASK_OUT_ABOVE_16(DY);
6273 uint ea = EA_AX_IX_16();
6275 m68ki_write_16(ea, res);
6277 FLAG_N = NFLAG_16(res);
6279 FLAG_V = VFLAG_CLEAR;
6280 FLAG_C = CFLAG_CLEAR;
6284 M68KMAKE_OP(move, 16, ix, a)
6286 uint res = MASK_OUT_ABOVE_16(AY);
6287 uint ea = EA_AX_IX_16();
6289 m68ki_write_16(ea, res);
6291 FLAG_N = NFLAG_16(res);
6293 FLAG_V = VFLAG_CLEAR;
6294 FLAG_C = CFLAG_CLEAR;
6298 M68KMAKE_OP(move, 16, ix, .)
6300 uint res = M68KMAKE_GET_OPER_AY_16;
6301 uint ea = EA_AX_IX_16();
6303 m68ki_write_16(ea, res);
6305 FLAG_N = NFLAG_16(res);
6307 FLAG_V = VFLAG_CLEAR;
6308 FLAG_C = CFLAG_CLEAR;
6312 M68KMAKE_OP(move, 16, aw, d)
6314 uint res = MASK_OUT_ABOVE_16(DY);
6315 uint ea = EA_AW_16();
6317 m68ki_write_16(ea, res);
6319 FLAG_N = NFLAG_16(res);
6321 FLAG_V = VFLAG_CLEAR;
6322 FLAG_C = CFLAG_CLEAR;
6326 M68KMAKE_OP(move, 16, aw, a)
6328 uint res = MASK_OUT_ABOVE_16(AY);
6329 uint ea = EA_AW_16();
6331 m68ki_write_16(ea, res);
6333 FLAG_N = NFLAG_16(res);
6335 FLAG_V = VFLAG_CLEAR;
6336 FLAG_C = CFLAG_CLEAR;
6340 M68KMAKE_OP(move, 16, aw, .)
6342 uint res = M68KMAKE_GET_OPER_AY_16;
6343 uint ea = EA_AW_16();
6345 m68ki_write_16(ea, res);
6347 FLAG_N = NFLAG_16(res);
6349 FLAG_V = VFLAG_CLEAR;
6350 FLAG_C = CFLAG_CLEAR;
6354 M68KMAKE_OP(move, 16, al, d)
6356 uint res = MASK_OUT_ABOVE_16(DY);
6357 uint ea = EA_AL_16();
6359 m68ki_write_16(ea, res);
6361 FLAG_N = NFLAG_16(res);
6363 FLAG_V = VFLAG_CLEAR;
6364 FLAG_C = CFLAG_CLEAR;
6368 M68KMAKE_OP(move, 16, al, a)
6370 uint res = MASK_OUT_ABOVE_16(AY);
6371 uint ea = EA_AL_16();
6373 m68ki_write_16(ea, res);
6375 FLAG_N = NFLAG_16(res);
6377 FLAG_V = VFLAG_CLEAR;
6378 FLAG_C = CFLAG_CLEAR;
6382 M68KMAKE_OP(move, 16, al, .)
6384 uint res = M68KMAKE_GET_OPER_AY_16;
6385 uint ea = EA_AL_16();
6387 m68ki_write_16(ea, res);
6389 FLAG_N = NFLAG_16(res);
6391 FLAG_V = VFLAG_CLEAR;
6392 FLAG_C = CFLAG_CLEAR;
6396 M68KMAKE_OP(move, 32, d, d)
6403 FLAG_N = NFLAG_32(res);
6405 FLAG_V = VFLAG_CLEAR;
6406 FLAG_C = CFLAG_CLEAR;
6410 M68KMAKE_OP(move, 32, d, a)
6417 FLAG_N = NFLAG_32(res);
6419 FLAG_V = VFLAG_CLEAR;
6420 FLAG_C = CFLAG_CLEAR;
6424 M68KMAKE_OP(move, 32, d, .)
6426 uint res = M68KMAKE_GET_OPER_AY_32;
6431 FLAG_N = NFLAG_32(res);
6433 FLAG_V = VFLAG_CLEAR;
6434 FLAG_C = CFLAG_CLEAR;
6438 M68KMAKE_OP(move, 32, ai, d)
6441 uint ea = EA_AX_AI_32();
6443 m68ki_write_32(ea, res);
6445 FLAG_N = NFLAG_32(res);
6447 FLAG_V = VFLAG_CLEAR;
6448 FLAG_C = CFLAG_CLEAR;
6452 M68KMAKE_OP(move, 32, ai, a)
6455 uint ea = EA_AX_AI_32();
6457 m68ki_write_32(ea, res);
6459 FLAG_N = NFLAG_32(res);
6461 FLAG_V = VFLAG_CLEAR;
6462 FLAG_C = CFLAG_CLEAR;
6466 M68KMAKE_OP(move, 32, ai, .)
6468 uint res = M68KMAKE_GET_OPER_AY_32;
6469 uint ea = EA_AX_AI_32();
6471 m68ki_write_32(ea, res);
6473 FLAG_N = NFLAG_32(res);
6475 FLAG_V = VFLAG_CLEAR;
6476 FLAG_C = CFLAG_CLEAR;
6480 M68KMAKE_OP(move, 32, pi, d)
6483 uint ea = EA_AX_PI_32();
6485 m68ki_write_32(ea, res);
6487 FLAG_N = NFLAG_32(res);
6489 FLAG_V = VFLAG_CLEAR;
6490 FLAG_C = CFLAG_CLEAR;
6494 M68KMAKE_OP(move, 32, pi, a)
6497 uint ea = EA_AX_PI_32();
6499 m68ki_write_32(ea, res);
6501 FLAG_N = NFLAG_32(res);
6503 FLAG_V = VFLAG_CLEAR;
6504 FLAG_C = CFLAG_CLEAR;
6508 M68KMAKE_OP(move, 32, pi, .)
6510 uint res = M68KMAKE_GET_OPER_AY_32;
6511 uint ea = EA_AX_PI_32();
6513 m68ki_write_32(ea, res);
6515 FLAG_N = NFLAG_32(res);
6517 FLAG_V = VFLAG_CLEAR;
6518 FLAG_C = CFLAG_CLEAR;
6522 M68KMAKE_OP(move, 32, pd, d)
6525 uint ea = EA_AX_PD_32();
6527 m68ki_write_16(ea+2, res & 0xFFFF );
6528 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6530 FLAG_N = NFLAG_32(res);
6532 FLAG_V = VFLAG_CLEAR;
6533 FLAG_C = CFLAG_CLEAR;
6537 M68KMAKE_OP(move, 32, pd, a)
6540 uint ea = EA_AX_PD_32();
6542 m68ki_write_16(ea+2, res & 0xFFFF );
6543 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6545 FLAG_N = NFLAG_32(res);
6547 FLAG_V = VFLAG_CLEAR;
6548 FLAG_C = CFLAG_CLEAR;
6552 M68KMAKE_OP(move, 32, pd, .)
6554 uint res = M68KMAKE_GET_OPER_AY_32;
6555 uint ea = EA_AX_PD_32();
6557 m68ki_write_16(ea+2, res & 0xFFFF );
6558 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6560 FLAG_N = NFLAG_32(res);
6562 FLAG_V = VFLAG_CLEAR;
6563 FLAG_C = CFLAG_CLEAR;
6567 M68KMAKE_OP(move, 32, di, d)
6570 uint ea = EA_AX_DI_32();
6572 m68ki_write_32(ea, res);
6574 FLAG_N = NFLAG_32(res);
6576 FLAG_V = VFLAG_CLEAR;
6577 FLAG_C = CFLAG_CLEAR;
6581 M68KMAKE_OP(move, 32, di, a)
6584 uint ea = EA_AX_DI_32();
6586 m68ki_write_32(ea, res);
6588 FLAG_N = NFLAG_32(res);
6590 FLAG_V = VFLAG_CLEAR;
6591 FLAG_C = CFLAG_CLEAR;
6595 M68KMAKE_OP(move, 32, di, .)
6597 uint res = M68KMAKE_GET_OPER_AY_32;
6598 uint ea = EA_AX_DI_32();
6600 m68ki_write_32(ea, res);
6602 FLAG_N = NFLAG_32(res);
6604 FLAG_V = VFLAG_CLEAR;
6605 FLAG_C = CFLAG_CLEAR;
6609 M68KMAKE_OP(move, 32, ix, d)
6612 uint ea = EA_AX_IX_32();
6614 m68ki_write_32(ea, res);
6616 FLAG_N = NFLAG_32(res);
6618 FLAG_V = VFLAG_CLEAR;
6619 FLAG_C = CFLAG_CLEAR;
6623 M68KMAKE_OP(move, 32, ix, a)
6626 uint ea = EA_AX_IX_32();
6628 m68ki_write_32(ea, res);
6630 FLAG_N = NFLAG_32(res);
6632 FLAG_V = VFLAG_CLEAR;
6633 FLAG_C = CFLAG_CLEAR;
6637 M68KMAKE_OP(move, 32, ix, .)
6639 uint res = M68KMAKE_GET_OPER_AY_32;
6640 uint ea = EA_AX_IX_32();
6642 m68ki_write_32(ea, res);
6644 FLAG_N = NFLAG_32(res);
6646 FLAG_V = VFLAG_CLEAR;
6647 FLAG_C = CFLAG_CLEAR;
6651 M68KMAKE_OP(move, 32, aw, d)
6654 uint ea = EA_AW_32();
6656 m68ki_write_32(ea, res);
6658 FLAG_N = NFLAG_32(res);
6660 FLAG_V = VFLAG_CLEAR;
6661 FLAG_C = CFLAG_CLEAR;
6665 M68KMAKE_OP(move, 32, aw, a)
6668 uint ea = EA_AW_32();
6670 m68ki_write_32(ea, res);
6672 FLAG_N = NFLAG_32(res);
6674 FLAG_V = VFLAG_CLEAR;
6675 FLAG_C = CFLAG_CLEAR;
6679 M68KMAKE_OP(move, 32, aw, .)
6681 uint res = M68KMAKE_GET_OPER_AY_32;
6682 uint ea = EA_AW_32();
6684 m68ki_write_32(ea, res);
6686 FLAG_N = NFLAG_32(res);
6688 FLAG_V = VFLAG_CLEAR;
6689 FLAG_C = CFLAG_CLEAR;
6693 M68KMAKE_OP(move, 32, al, d)
6696 uint ea = EA_AL_32();
6698 m68ki_write_32(ea, res);
6700 FLAG_N = NFLAG_32(res);
6702 FLAG_V = VFLAG_CLEAR;
6703 FLAG_C = CFLAG_CLEAR;
6707 M68KMAKE_OP(move, 32, al, a)
6710 uint ea = EA_AL_32();
6712 m68ki_write_32(ea, res);
6714 FLAG_N = NFLAG_32(res);
6716 FLAG_V = VFLAG_CLEAR;
6717 FLAG_C = CFLAG_CLEAR;
6721 M68KMAKE_OP(move, 32, al, .)
6723 uint res = M68KMAKE_GET_OPER_AY_32;
6724 uint ea = EA_AL_32();
6726 m68ki_write_32(ea, res);
6728 FLAG_N = NFLAG_32(res);
6730 FLAG_V = VFLAG_CLEAR;
6731 FLAG_C = CFLAG_CLEAR;
6735 M68KMAKE_OP(movea, 16, ., d)
6737 AX = MAKE_INT_16(DY);
6741 M68KMAKE_OP(movea, 16, ., a)
6743 AX = MAKE_INT_16(AY);
6747 M68KMAKE_OP(movea, 16, ., .)
6749 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
6753 M68KMAKE_OP(movea, 32, ., d)
6759 M68KMAKE_OP(movea, 32, ., a)
6765 M68KMAKE_OP(movea, 32, ., .)
6767 AX = M68KMAKE_GET_OPER_AY_32;
6771 M68KMAKE_OP(move, 16, frc, d)
6773 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6775 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
6778 m68ki_exception_illegal();
6782 M68KMAKE_OP(move, 16, frc, .)
6784 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6786 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
6789 m68ki_exception_illegal();
6793 M68KMAKE_OP(move, 16, toc, d)
6799 M68KMAKE_OP(move, 16, toc, .)
6801 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
6805 M68KMAKE_OP(move, 16, frs, d)
6807 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6809 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
6812 m68ki_exception_privilege_violation();
6816 M68KMAKE_OP(move, 16, frs, .)
6818 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6820 uint ea = M68KMAKE_GET_EA_AY_16;
6821 m68ki_write_16(ea, m68ki_get_sr());
6824 m68ki_exception_privilege_violation();
6828 M68KMAKE_OP(move, 16, tos, d)
6835 m68ki_exception_privilege_violation();
6839 M68KMAKE_OP(move, 16, tos, .)
6843 uint new_sr = M68KMAKE_GET_OPER_AY_16;
6844 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6845 m68ki_set_sr(new_sr);
6848 m68ki_exception_privilege_violation();
6852 M68KMAKE_OP(move, 32, fru, .)
6859 m68ki_exception_privilege_violation();
6863 M68KMAKE_OP(move, 32, tou, .)
6867 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6871 m68ki_exception_privilege_violation();
6875 M68KMAKE_OP(movec, 32, cr, .)
6877 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6881 uint word2 = OPER_I_16();
6883 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6884 switch (word2 & 0xfff)
6886 case 0x000: /* SFC */
6887 REG_DA[(word2 >> 12) & 15] = REG_SFC;
6889 case 0x001: /* DFC */
6890 REG_DA[(word2 >> 12) & 15] = REG_DFC;
6892 case 0x002: /* CACR */
6893 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6895 REG_DA[(word2 >> 12) & 15] = REG_CACR;
6899 case 0x800: /* USP */
6900 REG_DA[(word2 >> 12) & 15] = REG_USP;
6902 case 0x801: /* VBR */
6903 REG_DA[(word2 >> 12) & 15] = REG_VBR;
6905 case 0x802: /* CAAR */
6906 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6908 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
6911 m68ki_exception_illegal();
6913 case 0x803: /* MSP */
6914 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6916 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
6919 m68ki_exception_illegal();
6921 case 0x804: /* ISP */
6922 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6924 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
6927 m68ki_exception_illegal();
6929 case 0x003: /* TC */
6930 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6932 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_tc;
6935 m68ki_exception_illegal();
6937 case 0x004: /* ITT0 */
6938 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6940 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_itt0;
6943 m68ki_exception_illegal();
6945 case 0x005: /* ITT1 */
6946 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6948 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_itt1;
6951 m68ki_exception_illegal();
6953 case 0x006: /* DTT0 */
6954 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6956 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_dtt0;
6959 m68ki_exception_illegal();
6961 case 0x007: /* DTT1 */
6962 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6964 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_dtt1;
6967 m68ki_exception_illegal();
6969 case 0x805: /* MMUSR */
6970 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6972 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_sr_040;
6975 m68ki_exception_illegal();
6977 case 0x806: /* URP */
6978 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6980 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_urp_aptr;
6983 m68ki_exception_illegal();
6985 case 0x807: /* SRP */
6986 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6988 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_srp_aptr;
6991 m68ki_exception_illegal();
6994 m68ki_exception_illegal();
6998 m68ki_exception_privilege_violation();
7001 m68ki_exception_illegal();
7005 M68KMAKE_OP(movec, 32, rc, .)
7007 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7011 uint word2 = OPER_I_16();
7013 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7014 switch (word2 & 0xfff)
7016 case 0x000: /* SFC */
7017 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
7019 case 0x001: /* DFC */
7020 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
7022 case 0x002: /* CACR */
7023 /* Only EC020 and later have CACR */
7024 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7026 /* 68030 can write all bits except 5-7, 040 can write all */
7027 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7029 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0xfffffffe; // Old I cache bit not working on 040
7031 else if (CPU_TYPE_IS_030_PLUS(CPU_TYPE))
7033 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0xff1f;
7037 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
7040 if (REG_CACR & (M68K_CACR_CI | M68K_CACR_CEI)) {
7045 m68ki_exception_illegal();
7047 case 0x800: /* USP */
7048 REG_USP = REG_DA[(word2 >> 12) & 15];
7050 case 0x801: /* VBR */
7051 REG_VBR = REG_DA[(word2 >> 12) & 15];
7053 case 0x802: /* CAAR */
7054 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7056 REG_CAAR = REG_DA[(word2 >> 12) & 15];
7059 m68ki_exception_illegal();
7061 case 0x803: /* MSP */
7062 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7064 /* we are in supervisor mode so just check for M flag */
7067 REG_MSP = REG_DA[(word2 >> 12) & 15];
7070 REG_SP = REG_DA[(word2 >> 12) & 15];
7073 m68ki_exception_illegal();
7075 case 0x804: /* ISP */
7076 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7080 REG_SP = REG_DA[(word2 >> 12) & 15];
7083 REG_ISP = REG_DA[(word2 >> 12) & 15];
7086 m68ki_exception_illegal();
7088 case 0x003: /* TC */
7089 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7091 m68ki_cpu.mmu_tc = REG_DA[(word2 >> 12) & 15];
7093 if (m68ki_cpu.mmu_tc & 0x8000)
7095 m68ki_cpu.pmmu_enabled = 1;
7099 m68ki_cpu.pmmu_enabled = 0;
7103 m68ki_exception_illegal();
7105 case 0x004: /* ITT0 */
7106 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7108 m68ki_cpu.mmu_itt0 = REG_DA[(word2 >> 12) & 15];
7111 m68ki_exception_illegal();
7113 case 0x005: /* ITT1 */
7114 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7116 m68ki_cpu.mmu_itt1 = REG_DA[(word2 >> 12) & 15];
7119 m68ki_exception_illegal();
7121 case 0x006: /* DTT0 */
7122 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7124 m68ki_cpu.mmu_dtt0 = REG_DA[(word2 >> 12) & 15];
7127 m68ki_exception_illegal();
7129 case 0x007: /* DTT1 */
7130 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7132 m68ki_cpu.mmu_dtt1 = REG_DA[(word2 >> 12) & 15];
7135 m68ki_exception_illegal();
7137 case 0x805: /* MMUSR */
7138 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7140 m68ki_cpu.mmu_sr_040 = REG_DA[(word2 >> 12) & 15];
7143 m68ki_exception_illegal();
7145 case 0x806: /* URP */
7146 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7148 m68ki_cpu.mmu_urp_aptr = REG_DA[(word2 >> 12) & 15];
7151 m68ki_exception_illegal();
7153 case 0x807: /* SRP */
7154 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7156 m68ki_cpu.mmu_srp_aptr = REG_DA[(word2 >> 12) & 15];
7159 m68ki_exception_illegal();
7162 m68ki_exception_illegal();
7166 m68ki_exception_privilege_violation();
7169 m68ki_exception_illegal();
7173 M68KMAKE_OP(movem, 16, re, pd)
7176 uint register_list = OPER_I_16();
7181 if(register_list & (1 << i))
7184 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
7189 USE_CYCLES(count<<CYC_MOVEM_W);
7193 M68KMAKE_OP(movem, 16, re, .)
7196 uint register_list = OPER_I_16();
7197 uint ea = M68KMAKE_GET_EA_AY_16;
7201 if(register_list & (1 << i))
7203 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
7208 USE_CYCLES(count<<CYC_MOVEM_W);
7212 M68KMAKE_OP(movem, 32, re, pd)
7215 uint register_list = OPER_I_16();
7220 if(register_list & (1 << i))
7223 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
7224 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
7229 USE_CYCLES(count<<CYC_MOVEM_L);
7233 M68KMAKE_OP(movem, 32, re, .)
7236 uint register_list = OPER_I_16();
7237 uint ea = M68KMAKE_GET_EA_AY_32;
7241 if(register_list & (1 << i))
7243 m68ki_write_32(ea, REG_DA[i]);
7248 USE_CYCLES(count<<CYC_MOVEM_L);
7252 M68KMAKE_OP(movem, 16, er, pi)
7255 uint register_list = OPER_I_16();
7260 if(register_list & (1 << i))
7262 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7268 USE_CYCLES(count<<CYC_MOVEM_W);
7272 M68KMAKE_OP(movem, 16, er, pcdi)
7275 uint register_list = OPER_I_16();
7276 uint ea = EA_PCDI_16();
7280 if(register_list & (1 << i))
7282 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7287 USE_CYCLES(count<<CYC_MOVEM_W);
7291 M68KMAKE_OP(movem, 16, er, pcix)
7294 uint register_list = OPER_I_16();
7295 uint ea = EA_PCIX_16();
7299 if(register_list & (1 << i))
7301 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7306 USE_CYCLES(count<<CYC_MOVEM_W);
7310 M68KMAKE_OP(movem, 16, er, .)
7313 uint register_list = OPER_I_16();
7314 uint ea = M68KMAKE_GET_EA_AY_16;
7318 if(register_list & (1 << i))
7320 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7325 USE_CYCLES(count<<CYC_MOVEM_W);
7329 M68KMAKE_OP(movem, 32, er, pi)
7332 uint register_list = OPER_I_16();
7337 if(register_list & (1 << i))
7339 REG_DA[i] = m68ki_read_32(ea);
7345 USE_CYCLES(count<<CYC_MOVEM_L);
7349 M68KMAKE_OP(movem, 32, er, pcdi)
7352 uint register_list = OPER_I_16();
7353 uint ea = EA_PCDI_32();
7357 if(register_list & (1 << i))
7359 REG_DA[i] = m68ki_read_pcrel_32(ea);
7364 USE_CYCLES(count<<CYC_MOVEM_L);
7368 M68KMAKE_OP(movem, 32, er, pcix)
7371 uint register_list = OPER_I_16();
7372 uint ea = EA_PCIX_32();
7376 if(register_list & (1 << i))
7378 REG_DA[i] = m68ki_read_pcrel_32(ea);
7383 USE_CYCLES(count<<CYC_MOVEM_L);
7387 M68KMAKE_OP(movem, 32, er, .)
7390 uint register_list = OPER_I_16();
7391 uint ea = M68KMAKE_GET_EA_AY_32;
7395 if(register_list & (1 << i))
7397 REG_DA[i] = m68ki_read_32(ea);
7402 USE_CYCLES(count<<CYC_MOVEM_L);
7406 M68KMAKE_OP(movep, 16, re, .)
7408 uint ea = EA_AY_DI_16();
7411 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
7412 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7416 M68KMAKE_OP(movep, 32, re, .)
7418 uint ea = EA_AY_DI_32();
7421 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
7422 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
7423 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
7424 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7428 M68KMAKE_OP(movep, 16, er, .)
7430 uint ea = EA_AY_DI_16();
7433 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
7437 M68KMAKE_OP(movep, 32, er, .)
7439 uint ea = EA_AY_DI_32();
7441 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
7442 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
7446 M68KMAKE_OP(moves, 8, ., .)
7448 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7452 uint word2 = OPER_I_16();
7453 uint ea = M68KMAKE_GET_EA_AY_8;
7455 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7456 if(BIT_B(word2)) /* Register to memory */
7458 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
7461 if(BIT_F(word2)) /* Memory to address register */
7463 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
7464 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7468 /* Memory to data register */
7469 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
7470 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7474 m68ki_exception_privilege_violation();
7477 m68ki_exception_illegal();
7481 M68KMAKE_OP(moves, 16, ., .)
7483 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7487 uint word2 = OPER_I_16();
7488 uint ea = M68KMAKE_GET_EA_AY_16;
7490 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7491 if(BIT_B(word2)) /* Register to memory */
7493 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
7496 if(BIT_F(word2)) /* Memory to address register */
7498 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
7499 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7503 /* Memory to data register */
7504 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
7505 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7509 m68ki_exception_privilege_violation();
7512 m68ki_exception_illegal();
7516 M68KMAKE_OP(moves, 32, ., .)
7518 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7522 uint word2 = OPER_I_16();
7523 uint ea = M68KMAKE_GET_EA_AY_32;
7525 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7526 if(BIT_B(word2)) /* Register to memory */
7528 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
7529 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7533 /* Memory to register */
7534 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
7535 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7539 m68ki_exception_privilege_violation();
7542 m68ki_exception_illegal();
7546 M68KMAKE_OP(moveq, 32, ., .)
7548 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
7550 FLAG_N = NFLAG_32(res);
7552 FLAG_V = VFLAG_CLEAR;
7553 FLAG_C = CFLAG_CLEAR;
7557 M68KMAKE_OP(move16, 32, ., .)
7559 uint16 w2 = OPER_I_16();
7560 int ax = REG_IR & 7;
7561 int ay = (w2 >> 12) & 7;
7563 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
7564 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
7565 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
7566 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
7573 M68KMAKE_OP(muls, 16, ., d)
7576 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7581 FLAG_N = NFLAG_32(res);
7582 FLAG_V = VFLAG_CLEAR;
7583 FLAG_C = CFLAG_CLEAR;
7587 M68KMAKE_OP(muls, 16, ., .)
7590 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7595 FLAG_N = NFLAG_32(res);
7596 FLAG_V = VFLAG_CLEAR;
7597 FLAG_C = CFLAG_CLEAR;
7601 M68KMAKE_OP(mulu, 16, ., d)
7604 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
7609 FLAG_N = NFLAG_32(res);
7610 FLAG_V = VFLAG_CLEAR;
7611 FLAG_C = CFLAG_CLEAR;
7615 M68KMAKE_OP(mulu, 16, ., .)
7618 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
7623 FLAG_N = NFLAG_32(res);
7624 FLAG_V = VFLAG_CLEAR;
7625 FLAG_C = CFLAG_CLEAR;
7629 M68KMAKE_OP(mull, 32, ., d)
7633 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7635 uint word2 = OPER_I_16();
7637 uint64 dst = REG_D[(word2 >> 12) & 7];
7640 FLAG_C = CFLAG_CLEAR;
7642 if(BIT_B(word2)) /* signed */
7644 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7647 FLAG_Z = MASK_OUT_ABOVE_32(res);
7648 FLAG_N = NFLAG_32(res);
7649 FLAG_V = ((sint64)res != (sint32)res)<<7;
7650 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7653 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7654 FLAG_N = NFLAG_64(res);
7655 FLAG_V = VFLAG_CLEAR;
7656 REG_D[word2 & 7] = (res >> 32);
7657 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7664 FLAG_Z = MASK_OUT_ABOVE_32(res);
7665 FLAG_N = NFLAG_32(res);
7666 FLAG_V = (res > 0xffffffff)<<7;
7667 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7670 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7671 FLAG_N = NFLAG_64(res);
7672 FLAG_V = VFLAG_CLEAR;
7673 REG_D[word2 & 7] = (res >> 32);
7674 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7677 m68ki_exception_illegal();
7681 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7683 uint word2 = OPER_I_16();
7685 uint dst = REG_D[(word2 >> 12) & 7];
7686 uint neg = GET_MSB_32(src ^ dst);
7698 FLAG_C = CFLAG_CLEAR;
7700 if(BIT_B(word2)) /* signed */
7703 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7705 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7708 src1 = MASK_OUT_ABOVE_16(src);
7710 dst1 = MASK_OUT_ABOVE_16(dst);
7719 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7720 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7722 if(BIT_B(word2) && neg)
7724 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7725 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7730 REG_D[word2 & 7] = hi;
7731 REG_D[(word2 >> 12) & 7] = lo;
7732 FLAG_N = NFLAG_32(hi);
7734 FLAG_V = VFLAG_CLEAR;
7738 REG_D[(word2 >> 12) & 7] = lo;
7739 FLAG_N = NFLAG_32(lo);
7742 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7744 FLAG_V = (hi != 0) << 7;
7747 m68ki_exception_illegal();
7753 M68KMAKE_OP(mull, 32, ., .)
7757 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7759 uint word2 = OPER_I_16();
7760 uint64 src = M68KMAKE_GET_OPER_AY_32;
7761 uint64 dst = REG_D[(word2 >> 12) & 7];
7764 FLAG_C = CFLAG_CLEAR;
7766 if(BIT_B(word2)) /* signed */
7768 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7771 FLAG_Z = MASK_OUT_ABOVE_32(res);
7772 FLAG_N = NFLAG_32(res);
7773 FLAG_V = ((sint64)res != (sint32)res)<<7;
7774 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7777 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7778 FLAG_N = NFLAG_64(res);
7779 FLAG_V = VFLAG_CLEAR;
7780 REG_D[word2 & 7] = (res >> 32);
7781 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7788 FLAG_Z = MASK_OUT_ABOVE_32(res);
7789 FLAG_N = NFLAG_32(res);
7790 FLAG_V = (res > 0xffffffff)<<7;
7791 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7794 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7795 FLAG_N = NFLAG_64(res);
7796 FLAG_V = VFLAG_CLEAR;
7797 REG_D[word2 & 7] = (res >> 32);
7798 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7801 m68ki_exception_illegal();
7805 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7807 uint word2 = OPER_I_16();
7808 uint src = M68KMAKE_GET_OPER_AY_32;
7809 uint dst = REG_D[(word2 >> 12) & 7];
7810 uint neg = GET_MSB_32(src ^ dst);
7822 FLAG_C = CFLAG_CLEAR;
7824 if(BIT_B(word2)) /* signed */
7827 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7829 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7832 src1 = MASK_OUT_ABOVE_16(src);
7834 dst1 = MASK_OUT_ABOVE_16(dst);
7843 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7844 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7846 if(BIT_B(word2) && neg)
7848 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7849 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7854 REG_D[word2 & 7] = hi;
7855 REG_D[(word2 >> 12) & 7] = lo;
7856 FLAG_N = NFLAG_32(hi);
7858 FLAG_V = VFLAG_CLEAR;
7862 REG_D[(word2 >> 12) & 7] = lo;
7863 FLAG_N = NFLAG_32(lo);
7866 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7868 FLAG_V = (hi != 0) << 7;
7871 m68ki_exception_illegal();
7877 M68KMAKE_OP(nbcd, 8, ., d)
7880 uint dst = MASK_OUT_ABOVE_8(*r_dst);
7881 uint res = - dst - XFLAG_AS_1();
7885 FLAG_V = res; /* Undefined V behavior */
7887 if(((res|dst) & 0x0f) == 0)
7888 res = (res & 0xf0) + 6;
7890 res = MASK_OUT_ABOVE_8(res + 0x9a);
7892 FLAG_V &= ~res; /* Undefined V behavior part II */
7894 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7902 FLAG_V = VFLAG_CLEAR;
7903 FLAG_C = CFLAG_CLEAR;
7904 FLAG_X = XFLAG_CLEAR;
7906 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7910 M68KMAKE_OP(nbcd, 8, ., .)
7912 uint ea = M68KMAKE_GET_EA_AY_8;
7913 uint dst = m68ki_read_8(ea);
7914 uint res = - dst - XFLAG_AS_1();
7918 FLAG_V = res; /* Undefined V behavior */
7920 if(((res|dst) & 0x0f) == 0)
7921 res = (res & 0xf0) + 6;
7923 res = MASK_OUT_ABOVE_8(res + 0x9a);
7925 FLAG_V &= ~res; /* Undefined V behavior part II */
7927 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
7935 FLAG_V = VFLAG_CLEAR;
7936 FLAG_C = CFLAG_CLEAR;
7937 FLAG_X = XFLAG_CLEAR;
7939 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7943 M68KMAKE_OP(neg, 8, ., d)
7946 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
7948 FLAG_N = NFLAG_8(res);
7949 FLAG_C = FLAG_X = CFLAG_8(res);
7950 FLAG_V = *r_dst & res;
7951 FLAG_Z = MASK_OUT_ABOVE_8(res);
7953 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
7957 M68KMAKE_OP(neg, 8, ., .)
7959 uint ea = M68KMAKE_GET_EA_AY_8;
7960 uint src = m68ki_read_8(ea);
7963 FLAG_N = NFLAG_8(res);
7964 FLAG_C = FLAG_X = CFLAG_8(res);
7966 FLAG_Z = MASK_OUT_ABOVE_8(res);
7968 m68ki_write_8(ea, FLAG_Z);
7972 M68KMAKE_OP(neg, 16, ., d)
7975 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
7977 FLAG_N = NFLAG_16(res);
7978 FLAG_C = FLAG_X = CFLAG_16(res);
7979 FLAG_V = (*r_dst & res)>>8;
7980 FLAG_Z = MASK_OUT_ABOVE_16(res);
7982 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
7986 M68KMAKE_OP(neg, 16, ., .)
7988 uint ea = M68KMAKE_GET_EA_AY_16;
7989 uint src = m68ki_read_16(ea);
7992 FLAG_N = NFLAG_16(res);
7993 FLAG_C = FLAG_X = CFLAG_16(res);
7994 FLAG_V = (src & res)>>8;
7995 FLAG_Z = MASK_OUT_ABOVE_16(res);
7997 m68ki_write_16(ea, FLAG_Z);
8001 M68KMAKE_OP(neg, 32, ., d)
8004 uint res = 0 - *r_dst;
8006 FLAG_N = NFLAG_32(res);
8007 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
8008 FLAG_V = (*r_dst & res)>>24;
8009 FLAG_Z = MASK_OUT_ABOVE_32(res);
8015 M68KMAKE_OP(neg, 32, ., .)
8017 uint ea = M68KMAKE_GET_EA_AY_32;
8018 uint src = m68ki_read_32(ea);
8021 FLAG_N = NFLAG_32(res);
8022 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
8023 FLAG_V = (src & res)>>24;
8024 FLAG_Z = MASK_OUT_ABOVE_32(res);
8026 m68ki_write_32(ea, FLAG_Z);
8030 M68KMAKE_OP(negx, 8, ., d)
8033 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
8035 FLAG_N = NFLAG_8(res);
8036 FLAG_X = FLAG_C = CFLAG_8(res);
8037 FLAG_V = *r_dst & res;
8039 res = MASK_OUT_ABOVE_8(res);
8042 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8046 M68KMAKE_OP(negx, 8, ., .)
8048 uint ea = M68KMAKE_GET_EA_AY_8;
8049 uint src = m68ki_read_8(ea);
8050 uint res = 0 - src - XFLAG_AS_1();
8052 FLAG_N = NFLAG_8(res);
8053 FLAG_X = FLAG_C = CFLAG_8(res);
8056 res = MASK_OUT_ABOVE_8(res);
8059 m68ki_write_8(ea, res);
8063 M68KMAKE_OP(negx, 16, ., d)
8066 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
8068 FLAG_N = NFLAG_16(res);
8069 FLAG_X = FLAG_C = CFLAG_16(res);
8070 FLAG_V = (*r_dst & res)>>8;
8072 res = MASK_OUT_ABOVE_16(res);
8075 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8079 M68KMAKE_OP(negx, 16, ., .)
8081 uint ea = M68KMAKE_GET_EA_AY_16;
8082 uint src = m68ki_read_16(ea);
8083 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
8085 FLAG_N = NFLAG_16(res);
8086 FLAG_X = FLAG_C = CFLAG_16(res);
8087 FLAG_V = (src & res)>>8;
8089 res = MASK_OUT_ABOVE_16(res);
8092 m68ki_write_16(ea, res);
8096 M68KMAKE_OP(negx, 32, ., d)
8099 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
8101 FLAG_N = NFLAG_32(res);
8102 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
8103 FLAG_V = (*r_dst & res)>>24;
8105 res = MASK_OUT_ABOVE_32(res);
8112 M68KMAKE_OP(negx, 32, ., .)
8114 uint ea = M68KMAKE_GET_EA_AY_32;
8115 uint src = m68ki_read_32(ea);
8116 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
8118 FLAG_N = NFLAG_32(res);
8119 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
8120 FLAG_V = (src & res)>>24;
8122 res = MASK_OUT_ABOVE_32(res);
8125 m68ki_write_32(ea, res);
8129 M68KMAKE_OP(nop, 0, ., .)
8131 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8135 M68KMAKE_OP(not, 8, ., d)
8138 uint res = MASK_OUT_ABOVE_8(~*r_dst);
8140 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8142 FLAG_N = NFLAG_8(res);
8144 FLAG_C = CFLAG_CLEAR;
8145 FLAG_V = VFLAG_CLEAR;
8149 M68KMAKE_OP(not, 8, ., .)
8151 uint ea = M68KMAKE_GET_EA_AY_8;
8152 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
8154 m68ki_write_8(ea, res);
8156 FLAG_N = NFLAG_8(res);
8158 FLAG_C = CFLAG_CLEAR;
8159 FLAG_V = VFLAG_CLEAR;
8163 M68KMAKE_OP(not, 16, ., d)
8166 uint res = MASK_OUT_ABOVE_16(~*r_dst);
8168 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8170 FLAG_N = NFLAG_16(res);
8172 FLAG_C = CFLAG_CLEAR;
8173 FLAG_V = VFLAG_CLEAR;
8177 M68KMAKE_OP(not, 16, ., .)
8179 uint ea = M68KMAKE_GET_EA_AY_16;
8180 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
8182 m68ki_write_16(ea, res);
8184 FLAG_N = NFLAG_16(res);
8186 FLAG_C = CFLAG_CLEAR;
8187 FLAG_V = VFLAG_CLEAR;
8191 M68KMAKE_OP(not, 32, ., d)
8194 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
8196 FLAG_N = NFLAG_32(res);
8198 FLAG_C = CFLAG_CLEAR;
8199 FLAG_V = VFLAG_CLEAR;
8203 M68KMAKE_OP(not, 32, ., .)
8205 uint ea = M68KMAKE_GET_EA_AY_32;
8206 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
8208 m68ki_write_32(ea, res);
8210 FLAG_N = NFLAG_32(res);
8212 FLAG_C = CFLAG_CLEAR;
8213 FLAG_V = VFLAG_CLEAR;
8217 M68KMAKE_OP(or, 8, er, d)
8219 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
8221 FLAG_N = NFLAG_8(res);
8223 FLAG_C = CFLAG_CLEAR;
8224 FLAG_V = VFLAG_CLEAR;
8228 M68KMAKE_OP(or, 8, er, .)
8230 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
8232 FLAG_N = NFLAG_8(res);
8234 FLAG_C = CFLAG_CLEAR;
8235 FLAG_V = VFLAG_CLEAR;
8239 M68KMAKE_OP(or, 16, er, d)
8241 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
8243 FLAG_N = NFLAG_16(res);
8245 FLAG_C = CFLAG_CLEAR;
8246 FLAG_V = VFLAG_CLEAR;
8250 M68KMAKE_OP(or, 16, er, .)
8252 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
8254 FLAG_N = NFLAG_16(res);
8256 FLAG_C = CFLAG_CLEAR;
8257 FLAG_V = VFLAG_CLEAR;
8261 M68KMAKE_OP(or, 32, er, d)
8263 uint res = DX |= DY;
8265 FLAG_N = NFLAG_32(res);
8267 FLAG_C = CFLAG_CLEAR;
8268 FLAG_V = VFLAG_CLEAR;
8272 M68KMAKE_OP(or, 32, er, .)
8274 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
8276 FLAG_N = NFLAG_32(res);
8278 FLAG_C = CFLAG_CLEAR;
8279 FLAG_V = VFLAG_CLEAR;
8283 M68KMAKE_OP(or, 8, re, .)
8285 uint ea = M68KMAKE_GET_EA_AY_8;
8286 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
8288 m68ki_write_8(ea, res);
8290 FLAG_N = NFLAG_8(res);
8292 FLAG_C = CFLAG_CLEAR;
8293 FLAG_V = VFLAG_CLEAR;
8297 M68KMAKE_OP(or, 16, re, .)
8299 uint ea = M68KMAKE_GET_EA_AY_16;
8300 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
8302 m68ki_write_16(ea, res);
8304 FLAG_N = NFLAG_16(res);
8306 FLAG_C = CFLAG_CLEAR;
8307 FLAG_V = VFLAG_CLEAR;
8311 M68KMAKE_OP(or, 32, re, .)
8313 uint ea = M68KMAKE_GET_EA_AY_32;
8314 uint res = DX | m68ki_read_32(ea);
8316 m68ki_write_32(ea, res);
8318 FLAG_N = NFLAG_32(res);
8320 FLAG_C = CFLAG_CLEAR;
8321 FLAG_V = VFLAG_CLEAR;
8325 M68KMAKE_OP(ori, 8, ., d)
8327 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
8329 FLAG_N = NFLAG_8(res);
8331 FLAG_C = CFLAG_CLEAR;
8332 FLAG_V = VFLAG_CLEAR;
8336 M68KMAKE_OP(ori, 8, ., .)
8338 uint src = OPER_I_8();
8339 uint ea = M68KMAKE_GET_EA_AY_8;
8340 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
8342 m68ki_write_8(ea, res);
8344 FLAG_N = NFLAG_8(res);
8346 FLAG_C = CFLAG_CLEAR;
8347 FLAG_V = VFLAG_CLEAR;
8351 M68KMAKE_OP(ori, 16, ., d)
8353 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
8355 FLAG_N = NFLAG_16(res);
8357 FLAG_C = CFLAG_CLEAR;
8358 FLAG_V = VFLAG_CLEAR;
8362 M68KMAKE_OP(ori, 16, ., .)
8364 uint src = OPER_I_16();
8365 uint ea = M68KMAKE_GET_EA_AY_16;
8366 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
8368 m68ki_write_16(ea, res);
8370 FLAG_N = NFLAG_16(res);
8372 FLAG_C = CFLAG_CLEAR;
8373 FLAG_V = VFLAG_CLEAR;
8377 M68KMAKE_OP(ori, 32, ., d)
8379 uint res = DY |= OPER_I_32();
8381 FLAG_N = NFLAG_32(res);
8383 FLAG_C = CFLAG_CLEAR;
8384 FLAG_V = VFLAG_CLEAR;
8388 M68KMAKE_OP(ori, 32, ., .)
8390 uint src = OPER_I_32();
8391 uint ea = M68KMAKE_GET_EA_AY_32;
8392 uint res = src | m68ki_read_32(ea);
8394 m68ki_write_32(ea, res);
8396 FLAG_N = NFLAG_32(res);
8398 FLAG_C = CFLAG_CLEAR;
8399 FLAG_V = VFLAG_CLEAR;
8403 M68KMAKE_OP(ori, 16, toc, .)
8405 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8());
8409 M68KMAKE_OP(ori, 16, tos, .)
8413 uint src = OPER_I_16();
8414 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8415 m68ki_set_sr(m68ki_get_sr() | src);
8418 m68ki_exception_privilege_violation();
8422 M68KMAKE_OP(pack, 16, rr, .)
8424 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8426 /* Note: DX and DY are reversed in Motorola's docs */
8427 uint src = DY + OPER_I_16();
8430 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
8433 m68ki_exception_illegal();
8437 M68KMAKE_OP(pack, 16, mm, ax7)
8439 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8441 /* Note: AX and AY are reversed in Motorola's docs */
8442 uint ea_src = EA_AY_PD_8();
8443 uint src = m68ki_read_8(ea_src);
8444 ea_src = EA_AY_PD_8();
8445 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8447 m68ki_write_8(EA_A7_PD_8(), ((src >> 8) & 0x000f) | ((src<<4) & 0x00f0));
8450 m68ki_exception_illegal();
8454 M68KMAKE_OP(pack, 16, mm, ay7)
8456 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8458 /* Note: AX and AY are reversed in Motorola's docs */
8459 uint ea_src = EA_A7_PD_8();
8460 uint src = m68ki_read_8(ea_src);
8461 ea_src = EA_A7_PD_8();
8462 src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16();
8464 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8467 m68ki_exception_illegal();
8471 M68KMAKE_OP(pack, 16, mm, axy7)
8473 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8475 uint ea_src = EA_A7_PD_8();
8476 uint src = m68ki_read_8(ea_src);
8477 ea_src = EA_A7_PD_8();
8478 src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16();
8480 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8483 m68ki_exception_illegal();
8487 M68KMAKE_OP(pack, 16, mm, .)
8489 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8491 /* Note: AX and AY are reversed in Motorola's docs */
8492 uint ea_src = EA_AY_PD_8();
8493 uint src = m68ki_read_8(ea_src);
8494 ea_src = EA_AY_PD_8();
8495 src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16();
8497 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8500 m68ki_exception_illegal();
8504 M68KMAKE_OP(pea, 32, ., .)
8506 uint ea = M68KMAKE_GET_EA_AY_32;
8511 M68KMAKE_OP(pflusha, 32, ., .)
8515 fprintf(stderr,"68040: unhandled PFLUSHA (ir=%04x)\n", REG_IR);
8518 m68ki_exception_1111();
8521 M68KMAKE_OP(pflushan, 32, ., .)
8525 fprintf(stderr,"68040: unhandled PFLUSHAN (ir=%04x)\n", REG_IR);
8528 m68ki_exception_1111();
8531 M68KMAKE_OP(pmmu, 32, ., .)
8533 if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU))
8539 m68ki_exception_1111();
8543 M68KMAKE_OP(reset, 0, ., .)
8547 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
8548 USE_CYCLES(CYC_RESET);
8551 m68ki_exception_privilege_violation();
8555 M68KMAKE_OP(ror, 8, s, .)
8558 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8559 uint shift = orig_shift & 7;
8560 uint src = MASK_OUT_ABOVE_8(*r_dst);
8561 uint res = ROR_8(src, shift);
8564 USE_CYCLES(orig_shift<<CYC_SHIFT);
8566 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8568 FLAG_N = NFLAG_8(res);
8570 FLAG_C = src << (9-orig_shift);
8571 FLAG_V = VFLAG_CLEAR;
8575 M68KMAKE_OP(ror, 16, s, .)
8578 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8579 uint src = MASK_OUT_ABOVE_16(*r_dst);
8580 uint res = ROR_16(src, shift);
8583 USE_CYCLES(shift<<CYC_SHIFT);
8585 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8587 FLAG_N = NFLAG_16(res);
8589 FLAG_C = src << (9-shift);
8590 FLAG_V = VFLAG_CLEAR;
8594 M68KMAKE_OP(ror, 32, s, .)
8597 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8598 uint64 src = *r_dst;
8599 uint res = ROR_32(src, shift);
8602 USE_CYCLES(shift<<CYC_SHIFT);
8606 FLAG_N = NFLAG_32(res);
8608 FLAG_C = src << (9-shift);
8609 FLAG_V = VFLAG_CLEAR;
8613 M68KMAKE_OP(ror, 8, r, .)
8616 uint orig_shift = DX & 0x3f;
8617 uint shift = orig_shift & 7;
8618 uint src = MASK_OUT_ABOVE_8(*r_dst);
8619 uint res = ROR_8(src, shift);
8623 USE_CYCLES(orig_shift<<CYC_SHIFT);
8625 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8626 FLAG_C = src << (8-((shift-1)&7));
8627 FLAG_N = NFLAG_8(res);
8629 FLAG_V = VFLAG_CLEAR;
8633 FLAG_C = CFLAG_CLEAR;
8634 FLAG_N = NFLAG_8(src);
8636 FLAG_V = VFLAG_CLEAR;
8640 M68KMAKE_OP(ror, 16, r, .)
8643 uint orig_shift = DX & 0x3f;
8644 uint shift = orig_shift & 15;
8645 uint src = MASK_OUT_ABOVE_16(*r_dst);
8646 uint res = ROR_16(src, shift);
8650 USE_CYCLES(orig_shift<<CYC_SHIFT);
8652 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8653 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
8654 FLAG_N = NFLAG_16(res);
8656 FLAG_V = VFLAG_CLEAR;
8660 FLAG_C = CFLAG_CLEAR;
8661 FLAG_N = NFLAG_16(src);
8663 FLAG_V = VFLAG_CLEAR;
8667 M68KMAKE_OP(ror, 32, r, .)
8670 uint orig_shift = DX & 0x3f;
8671 uint shift = orig_shift & 31;
8672 uint64 src = *r_dst;
8673 uint res = ROR_32(src, shift);
8677 USE_CYCLES(orig_shift<<CYC_SHIFT);
8680 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
8681 FLAG_N = NFLAG_32(res);
8683 FLAG_V = VFLAG_CLEAR;
8687 FLAG_C = CFLAG_CLEAR;
8688 FLAG_N = NFLAG_32(src);
8690 FLAG_V = VFLAG_CLEAR;
8694 M68KMAKE_OP(ror, 16, ., .)
8696 uint ea = M68KMAKE_GET_EA_AY_16;
8697 uint src = m68ki_read_16(ea);
8698 uint res = ROR_16(src, 1);
8700 m68ki_write_16(ea, res);
8702 FLAG_N = NFLAG_16(res);
8705 FLAG_V = VFLAG_CLEAR;
8709 M68KMAKE_OP(rol, 8, s, .)
8712 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8713 uint shift = orig_shift & 7;
8714 uint src = MASK_OUT_ABOVE_8(*r_dst);
8715 uint res = ROL_8(src, shift);
8718 USE_CYCLES(orig_shift<<CYC_SHIFT);
8720 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8722 FLAG_N = NFLAG_8(res);
8724 FLAG_C = src << orig_shift;
8725 FLAG_V = VFLAG_CLEAR;
8729 M68KMAKE_OP(rol, 16, s, .)
8732 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8733 uint src = MASK_OUT_ABOVE_16(*r_dst);
8734 uint res = ROL_16(src, shift);
8737 USE_CYCLES(shift<<CYC_SHIFT);
8739 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8741 FLAG_N = NFLAG_16(res);
8743 FLAG_C = src >> (8-shift);
8744 FLAG_V = VFLAG_CLEAR;
8748 M68KMAKE_OP(rol, 32, s, .)
8751 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8752 uint64 src = *r_dst;
8753 uint res = ROL_32(src, shift);
8756 USE_CYCLES(shift<<CYC_SHIFT);
8760 FLAG_N = NFLAG_32(res);
8762 FLAG_C = src >> (24-shift);
8763 FLAG_V = VFLAG_CLEAR;
8767 M68KMAKE_OP(rol, 8, r, .)
8770 uint orig_shift = DX & 0x3f;
8771 uint shift = orig_shift & 7;
8772 uint src = MASK_OUT_ABOVE_8(*r_dst);
8773 uint res = ROL_8(src, shift);
8777 USE_CYCLES(orig_shift<<CYC_SHIFT);
8781 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8782 FLAG_C = src << shift;
8783 FLAG_N = NFLAG_8(res);
8785 FLAG_V = VFLAG_CLEAR;
8788 FLAG_C = (src & 1)<<8;
8789 FLAG_N = NFLAG_8(src);
8791 FLAG_V = VFLAG_CLEAR;
8795 FLAG_C = CFLAG_CLEAR;
8796 FLAG_N = NFLAG_8(src);
8798 FLAG_V = VFLAG_CLEAR;
8802 M68KMAKE_OP(rol, 16, r, .)
8805 uint orig_shift = DX & 0x3f;
8806 uint shift = orig_shift & 15;
8807 uint src = MASK_OUT_ABOVE_16(*r_dst);
8808 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
8812 USE_CYCLES(orig_shift<<CYC_SHIFT);
8816 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8817 FLAG_C = (src << shift) >> 8;
8818 FLAG_N = NFLAG_16(res);
8820 FLAG_V = VFLAG_CLEAR;
8823 FLAG_C = (src & 1)<<8;
8824 FLAG_N = NFLAG_16(src);
8826 FLAG_V = VFLAG_CLEAR;
8830 FLAG_C = CFLAG_CLEAR;
8831 FLAG_N = NFLAG_16(src);
8833 FLAG_V = VFLAG_CLEAR;
8837 M68KMAKE_OP(rol, 32, r, .)
8840 uint orig_shift = DX & 0x3f;
8841 uint shift = orig_shift & 31;
8842 uint64 src = *r_dst;
8843 uint res = ROL_32(src, shift);
8847 USE_CYCLES(orig_shift<<CYC_SHIFT);
8851 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
8852 FLAG_N = NFLAG_32(res);
8854 FLAG_V = VFLAG_CLEAR;
8858 FLAG_C = CFLAG_CLEAR;
8859 FLAG_N = NFLAG_32(src);
8861 FLAG_V = VFLAG_CLEAR;
8865 M68KMAKE_OP(rol, 16, ., .)
8867 uint ea = M68KMAKE_GET_EA_AY_16;
8868 uint src = m68ki_read_16(ea);
8869 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
8871 m68ki_write_16(ea, res);
8873 FLAG_N = NFLAG_16(res);
8876 FLAG_V = VFLAG_CLEAR;
8880 M68KMAKE_OP(roxr, 8, s, .)
8883 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8884 uint src = MASK_OUT_ABOVE_8(*r_dst);
8885 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8888 USE_CYCLES(shift<<CYC_SHIFT);
8890 FLAG_C = FLAG_X = res;
8891 res = MASK_OUT_ABOVE_8(res);
8893 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8895 FLAG_N = NFLAG_8(res);
8897 FLAG_V = VFLAG_CLEAR;
8901 M68KMAKE_OP(roxr, 16, s, .)
8904 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8905 uint src = MASK_OUT_ABOVE_16(*r_dst);
8906 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8909 USE_CYCLES(shift<<CYC_SHIFT);
8911 FLAG_C = FLAG_X = res >> 8;
8912 res = MASK_OUT_ABOVE_16(res);
8914 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8916 FLAG_N = NFLAG_16(res);
8918 FLAG_V = VFLAG_CLEAR;
8922 M68KMAKE_OP(roxr, 32, s, .)
8927 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8928 uint64 src = *r_dst;
8929 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8932 USE_CYCLES(shift<<CYC_SHIFT);
8934 res = ROR_33_64(res, shift);
8936 FLAG_C = FLAG_X = res >> 24;
8937 res = MASK_OUT_ABOVE_32(res);
8941 FLAG_N = NFLAG_32(res);
8943 FLAG_V = VFLAG_CLEAR;
8948 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8950 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8951 uint new_x_flag = src & (1 << (shift - 1));
8954 USE_CYCLES(shift<<CYC_SHIFT);
8958 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
8959 FLAG_N = NFLAG_32(res);
8961 FLAG_V = VFLAG_CLEAR;
8967 M68KMAKE_OP(roxr, 8, r, .)
8970 uint orig_shift = DX & 0x3f;
8974 uint shift = orig_shift % 9;
8975 uint src = MASK_OUT_ABOVE_8(*r_dst);
8976 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8978 USE_CYCLES(orig_shift<<CYC_SHIFT);
8980 FLAG_C = FLAG_X = res;
8981 res = MASK_OUT_ABOVE_8(res);
8983 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8984 FLAG_N = NFLAG_8(res);
8986 FLAG_V = VFLAG_CLEAR;
8991 FLAG_N = NFLAG_8(*r_dst);
8992 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
8993 FLAG_V = VFLAG_CLEAR;
8997 M68KMAKE_OP(roxr, 16, r, .)
9000 uint orig_shift = DX & 0x3f;
9004 uint shift = orig_shift % 17;
9005 uint src = MASK_OUT_ABOVE_16(*r_dst);
9006 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
9008 USE_CYCLES(orig_shift<<CYC_SHIFT);
9010 FLAG_C = FLAG_X = res >> 8;
9011 res = MASK_OUT_ABOVE_16(res);
9013 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9014 FLAG_N = NFLAG_16(res);
9016 FLAG_V = VFLAG_CLEAR;
9021 FLAG_N = NFLAG_16(*r_dst);
9022 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
9023 FLAG_V = VFLAG_CLEAR;
9027 M68KMAKE_OP(roxr, 32, r, .)
9032 uint orig_shift = DX & 0x3f;
9036 uint shift = orig_shift % 33;
9037 uint64 src = *r_dst;
9038 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9040 res = ROR_33_64(res, shift);
9042 USE_CYCLES(orig_shift<<CYC_SHIFT);
9044 FLAG_C = FLAG_X = res >> 24;
9045 res = MASK_OUT_ABOVE_32(res);
9048 FLAG_N = NFLAG_32(res);
9050 FLAG_V = VFLAG_CLEAR;
9055 FLAG_N = NFLAG_32(*r_dst);
9057 FLAG_V = VFLAG_CLEAR;
9062 uint orig_shift = DX & 0x3f;
9063 uint shift = orig_shift % 33;
9065 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
9066 uint new_x_flag = src & (1 << (shift - 1));
9069 USE_CYCLES(orig_shift<<CYC_SHIFT);
9074 FLAG_X = (new_x_flag != 0)<<8;
9079 FLAG_N = NFLAG_32(res);
9081 FLAG_V = VFLAG_CLEAR;
9087 M68KMAKE_OP(roxr, 16, ., .)
9089 uint ea = M68KMAKE_GET_EA_AY_16;
9090 uint src = m68ki_read_16(ea);
9091 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
9093 FLAG_C = FLAG_X = res >> 8;
9094 res = MASK_OUT_ABOVE_16(res);
9096 m68ki_write_16(ea, res);
9098 FLAG_N = NFLAG_16(res);
9100 FLAG_V = VFLAG_CLEAR;
9104 M68KMAKE_OP(roxl, 8, s, .)
9107 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9108 uint src = MASK_OUT_ABOVE_8(*r_dst);
9109 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9112 USE_CYCLES(shift<<CYC_SHIFT);
9114 FLAG_C = FLAG_X = res;
9115 res = MASK_OUT_ABOVE_8(res);
9117 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9119 FLAG_N = NFLAG_8(res);
9121 FLAG_V = VFLAG_CLEAR;
9125 M68KMAKE_OP(roxl, 16, s, .)
9128 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9129 uint src = MASK_OUT_ABOVE_16(*r_dst);
9130 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9133 USE_CYCLES(shift<<CYC_SHIFT);
9135 FLAG_C = FLAG_X = res >> 8;
9136 res = MASK_OUT_ABOVE_16(res);
9138 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9140 FLAG_N = NFLAG_16(res);
9142 FLAG_V = VFLAG_CLEAR;
9146 M68KMAKE_OP(roxl, 32, s, .)
9151 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9152 uint64 src = *r_dst;
9153 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9156 USE_CYCLES(shift<<CYC_SHIFT);
9158 res = ROL_33_64(res, shift);
9160 FLAG_C = FLAG_X = res >> 24;
9161 res = MASK_OUT_ABOVE_32(res);
9165 FLAG_N = NFLAG_32(res);
9167 FLAG_V = VFLAG_CLEAR;
9172 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9174 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9175 uint new_x_flag = src & (1 << (32 - shift));
9178 USE_CYCLES(shift<<CYC_SHIFT);
9182 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
9183 FLAG_N = NFLAG_32(res);
9185 FLAG_V = VFLAG_CLEAR;
9191 M68KMAKE_OP(roxl, 8, r, .)
9194 uint orig_shift = DX & 0x3f;
9199 uint shift = orig_shift % 9;
9200 uint src = MASK_OUT_ABOVE_8(*r_dst);
9201 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9203 USE_CYCLES(orig_shift<<CYC_SHIFT);
9205 FLAG_C = FLAG_X = res;
9206 res = MASK_OUT_ABOVE_8(res);
9208 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9209 FLAG_N = NFLAG_8(res);
9211 FLAG_V = VFLAG_CLEAR;
9216 FLAG_N = NFLAG_8(*r_dst);
9217 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
9218 FLAG_V = VFLAG_CLEAR;
9222 M68KMAKE_OP(roxl, 16, r, .)
9225 uint orig_shift = DX & 0x3f;
9229 uint shift = orig_shift % 17;
9230 uint src = MASK_OUT_ABOVE_16(*r_dst);
9231 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9233 USE_CYCLES(orig_shift<<CYC_SHIFT);
9235 FLAG_C = FLAG_X = res >> 8;
9236 res = MASK_OUT_ABOVE_16(res);
9238 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9239 FLAG_N = NFLAG_16(res);
9241 FLAG_V = VFLAG_CLEAR;
9246 FLAG_N = NFLAG_16(*r_dst);
9247 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
9248 FLAG_V = VFLAG_CLEAR;
9252 M68KMAKE_OP(roxl, 32, r, .)
9257 uint orig_shift = DX & 0x3f;
9261 uint shift = orig_shift % 33;
9262 uint64 src = *r_dst;
9263 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9265 res = ROL_33_64(res, shift);
9267 USE_CYCLES(orig_shift<<CYC_SHIFT);
9269 FLAG_C = FLAG_X = res >> 24;
9270 res = MASK_OUT_ABOVE_32(res);
9273 FLAG_N = NFLAG_32(res);
9275 FLAG_V = VFLAG_CLEAR;
9280 FLAG_N = NFLAG_32(*r_dst);
9282 FLAG_V = VFLAG_CLEAR;
9287 uint orig_shift = DX & 0x3f;
9288 uint shift = orig_shift % 33;
9290 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9291 uint new_x_flag = src & (1 << (32 - shift));
9294 USE_CYCLES(orig_shift<<CYC_SHIFT);
9299 FLAG_X = (new_x_flag != 0)<<8;
9304 FLAG_N = NFLAG_32(res);
9306 FLAG_V = VFLAG_CLEAR;
9312 M68KMAKE_OP(roxl, 16, ., .)
9314 uint ea = M68KMAKE_GET_EA_AY_16;
9315 uint src = m68ki_read_16(ea);
9316 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
9318 FLAG_C = FLAG_X = res >> 8;
9319 res = MASK_OUT_ABOVE_16(res);
9321 m68ki_write_16(ea, res);
9323 FLAG_N = NFLAG_16(res);
9325 FLAG_V = VFLAG_CLEAR;
9329 M68KMAKE_OP(rtd, 32, ., .)
9331 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
9333 uint new_pc = m68ki_pull_32();
9335 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9336 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
9340 m68ki_exception_illegal();
9344 M68KMAKE_OP(rte, 32, ., .)
9352 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
9353 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9355 if(CPU_TYPE_IS_000(CPU_TYPE))
9357 new_sr = m68ki_pull_16();
9358 new_pc = m68ki_pull_32();
9360 m68ki_set_sr(new_sr);
9362 CPU_INSTR_MODE = INSTRUCTION_YES;
9363 CPU_RUN_MODE = RUN_MODE_NORMAL;
9368 if(CPU_TYPE_IS_010(CPU_TYPE))
9370 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9371 if(format_word == 0)
9373 new_sr = m68ki_pull_16();
9374 new_pc = m68ki_pull_32();
9375 m68ki_fake_pull_16(); /* format word */
9377 m68ki_set_sr(new_sr);
9378 CPU_INSTR_MODE = INSTRUCTION_YES;
9379 CPU_RUN_MODE = RUN_MODE_NORMAL;
9381 } else if (format_word == 8) {
9382 /* Format 8 stack frame -- 68010 only. 29 word bus/address error */
9383 new_sr = m68ki_pull_16();
9384 new_pc = m68ki_pull_32();
9385 m68ki_fake_pull_16(); /* format word */
9387 m68ki_set_sr(new_sr);
9388 CPU_INSTR_MODE = INSTRUCTION_YES;
9389 CPU_RUN_MODE = RUN_MODE_NORMAL;
9390 m68ki_fake_pull_16(); /* special status */
9391 m68ki_fake_pull_32(); /* fault address */
9392 m68ki_fake_pull_32(); /* reserved and data output buffer */
9393 m68ki_fake_pull_32(); /* reserved and data input buffer */
9394 m68ki_fake_pull_32(); /* reserved and instruction input buffer */
9395 m68ki_fake_pull_32(); /* 8 dwords of CPU specific undocumented data */
9396 m68ki_fake_pull_32();
9397 m68ki_fake_pull_32();
9398 m68ki_fake_pull_32();
9399 m68ki_fake_pull_32();
9400 m68ki_fake_pull_32();
9401 m68ki_fake_pull_32();
9402 m68ki_fake_pull_32();
9405 CPU_INSTR_MODE = INSTRUCTION_YES;
9406 CPU_RUN_MODE = RUN_MODE_NORMAL;
9407 /* Not handling other exception types (9) */
9408 m68ki_exception_format_error();
9412 /* Otherwise it's 020 */
9414 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9417 case 0: /* Normal */
9418 new_sr = m68ki_pull_16();
9419 new_pc = m68ki_pull_32();
9420 m68ki_fake_pull_16(); /* format word */
9422 m68ki_set_sr(new_sr);
9423 CPU_INSTR_MODE = INSTRUCTION_YES;
9424 CPU_RUN_MODE = RUN_MODE_NORMAL;
9426 case 1: /* Throwaway */
9427 new_sr = m68ki_pull_16();
9428 m68ki_fake_pull_32(); /* program counter */
9429 m68ki_fake_pull_16(); /* format word */
9430 m68ki_set_sr_noint(new_sr);
9433 new_sr = m68ki_pull_16();
9434 new_pc = m68ki_pull_32();
9435 m68ki_fake_pull_16(); /* format word */
9436 m68ki_fake_pull_32(); /* address */
9438 m68ki_set_sr(new_sr);
9439 CPU_INSTR_MODE = INSTRUCTION_YES;
9440 CPU_RUN_MODE = RUN_MODE_NORMAL;
9442 case 7: /* 68040 access error */
9443 new_sr = m68ki_pull_16();
9444 new_pc = m68ki_pull_32();
9445 m68ki_fake_pull_16(); /* $06: format word */
9446 m68ki_fake_pull_32(); /* $08: effective address */
9447 m68ki_fake_pull_16(); /* $0c: special status word */
9448 m68ki_fake_pull_16(); /* $0e: wb3s */
9449 m68ki_fake_pull_16(); /* $10: wb2s */
9450 m68ki_fake_pull_16(); /* $12: wb1s */
9451 m68ki_fake_pull_32(); /* $14: data fault address */
9452 m68ki_fake_pull_32(); /* $18: wb3a */
9453 m68ki_fake_pull_32(); /* $1c: wb3d */
9454 m68ki_fake_pull_32(); /* $20: wb2a */
9455 m68ki_fake_pull_32(); /* $24: wb2d */
9456 m68ki_fake_pull_32(); /* $28: wb1a */
9457 m68ki_fake_pull_32(); /* $2c: wb1d/pd0 */
9458 m68ki_fake_pull_32(); /* $30: pd1 */
9459 m68ki_fake_pull_32(); /* $34: pd2 */
9460 m68ki_fake_pull_32(); /* $38: pd3 */
9462 m68ki_set_sr(new_sr);
9463 CPU_INSTR_MODE = INSTRUCTION_YES;
9464 CPU_RUN_MODE = RUN_MODE_NORMAL;
9467 case 0x0a: /* Bus Error at instruction boundary */
9468 new_sr = m68ki_pull_16();
9469 new_pc = m68ki_pull_32();
9470 m68ki_fake_pull_16(); /* $06: format word */
9471 m68ki_fake_pull_16(); /* $08: internal register */
9472 m68ki_fake_pull_16(); /* $0a: special status word */
9473 m68ki_fake_pull_16(); /* $0c: instruction pipe stage c */
9474 m68ki_fake_pull_16(); /* $0e: instruction pipe stage b */
9475 m68ki_fake_pull_32(); /* $10: data fault address */
9476 m68ki_fake_pull_32(); /* $14: internal registers */
9477 m68ki_fake_pull_32(); /* $18: data output buffer */
9478 m68ki_fake_pull_32(); /* $1c: internal registers */
9481 m68ki_set_sr(new_sr);
9482 CPU_INSTR_MODE = INSTRUCTION_YES;
9483 CPU_RUN_MODE = RUN_MODE_NORMAL;
9486 case 0x0b: /* Bus Error - Instruction Execution in Progress */
9487 new_sr = m68ki_pull_16();
9488 new_pc = m68ki_pull_32();
9489 m68ki_fake_pull_16(); /* $06: format word */
9490 m68ki_fake_pull_16(); /* $08: internal register */
9491 m68ki_fake_pull_16(); /* $0a: special status word */
9492 m68ki_fake_pull_16(); /* $0c: instruction pipe stage c */
9493 m68ki_fake_pull_16(); /* $0e: instruction pipe stage b */
9494 m68ki_fake_pull_32(); /* $10: data fault address */
9495 m68ki_fake_pull_32(); /* $14: internal registers */
9496 m68ki_fake_pull_32(); /* $18: data output buffer */
9497 m68ki_fake_pull_32(); /* $1c: internal registers */
9498 m68ki_fake_pull_32(); /* $20: */
9499 m68ki_fake_pull_32(); /* $24: stage B address */
9500 m68ki_fake_pull_32(); /* $28: */
9501 m68ki_fake_pull_32(); /* $2c: data input buffer */
9502 m68ki_fake_pull_32(); /* $30: */
9503 m68ki_fake_pull_16(); /* $34: */
9504 m68ki_fake_pull_16(); /* $36: version #, internal information */
9505 m68ki_fake_pull_32(); /* $38: */
9506 m68ki_fake_pull_32(); /* $3c: */
9507 m68ki_fake_pull_32(); /* $40: */
9508 m68ki_fake_pull_32(); /* $44: */
9509 m68ki_fake_pull_32(); /* $48: */
9510 m68ki_fake_pull_32(); /* $4c: */
9511 m68ki_fake_pull_32(); /* $50: */
9512 m68ki_fake_pull_32(); /* $54: */
9513 m68ki_fake_pull_32(); /* $58: */
9516 m68ki_set_sr(new_sr);
9517 CPU_INSTR_MODE = INSTRUCTION_YES;
9518 CPU_RUN_MODE = RUN_MODE_NORMAL;
9521 /* Not handling long or short bus fault */
9522 CPU_INSTR_MODE = INSTRUCTION_YES;
9523 CPU_RUN_MODE = RUN_MODE_NORMAL;
9524 m68ki_exception_format_error();
9527 m68ki_exception_privilege_violation();
9531 M68KMAKE_OP(rtm, 32, ., .)
9533 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
9535 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9536 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
9537 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
9538 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
9541 m68ki_exception_illegal();
9545 M68KMAKE_OP(rtr, 32, ., .)
9547 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9548 m68ki_set_ccr(m68ki_pull_16());
9549 m68ki_jump(m68ki_pull_32());
9553 M68KMAKE_OP(rts, 32, ., .)
9555 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9556 m68ki_jump(m68ki_pull_32());
9560 M68KMAKE_OP(sbcd, 8, rr, .)
9565 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9570 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9571 FLAG_V = res; /* Undefined V behavior */
9574 FLAG_X = FLAG_C = CFLAG_SET;
9575 } else if(res < corf)
9576 FLAG_X = FLAG_C = CFLAG_SET;
9578 FLAG_N = FLAG_X = FLAG_C = 0;
9580 res = MASK_OUT_ABOVE_8(res - corf);
9582 FLAG_V &= ~res; /* Undefined V behavior part II */
9583 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9586 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9590 M68KMAKE_OP(sbcd, 8, mm, ax7)
9592 uint src = OPER_AY_PD_8();
9593 uint ea = EA_A7_PD_8();
9594 uint dst = m68ki_read_8(ea);
9595 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9600 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9601 FLAG_V = res; /* Undefined V behavior */
9604 FLAG_X = FLAG_C = CFLAG_SET;
9605 } else if(res < corf)
9606 FLAG_X = FLAG_C = CFLAG_SET;
9608 FLAG_N = FLAG_X = FLAG_C = 0;
9610 res = MASK_OUT_ABOVE_8(res - corf);
9612 FLAG_V &= ~res; /* Undefined V behavior part II */
9613 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9616 m68ki_write_8(ea, res);
9620 M68KMAKE_OP(sbcd, 8, mm, ay7)
9622 uint src = OPER_A7_PD_8();
9623 uint ea = EA_AX_PD_8();
9624 uint dst = m68ki_read_8(ea);
9625 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9630 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9631 FLAG_V = res; /* Undefined V behavior */
9634 FLAG_X = FLAG_C = CFLAG_SET;
9635 } else if(res < corf)
9636 FLAG_X = FLAG_C = CFLAG_SET;
9638 FLAG_N = FLAG_X = FLAG_C = 0;
9640 res = MASK_OUT_ABOVE_8(res - corf);
9642 FLAG_V &= ~res; /* Undefined V behavior part II */
9643 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9646 m68ki_write_8(ea, res);
9650 M68KMAKE_OP(sbcd, 8, mm, axy7)
9652 uint src = OPER_A7_PD_8();
9653 uint ea = EA_A7_PD_8();
9654 uint dst = m68ki_read_8(ea);
9655 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9660 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9661 FLAG_V = res; /* Undefined V behavior */
9664 FLAG_X = FLAG_C = CFLAG_SET;
9665 } else if(res < corf)
9666 FLAG_X = FLAG_C = CFLAG_SET;
9668 FLAG_N = FLAG_X = FLAG_C = 0;
9670 res = MASK_OUT_ABOVE_8(res - corf);
9672 FLAG_V &= ~res; /* Undefined V behavior part II */
9673 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9676 m68ki_write_8(ea, res);
9680 M68KMAKE_OP(sbcd, 8, mm, .)
9682 uint src = OPER_AY_PD_8();
9683 uint ea = EA_AX_PD_8();
9684 uint dst = m68ki_read_8(ea);
9685 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9690 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9691 FLAG_V = res; /* Undefined V behavior */
9694 FLAG_X = FLAG_C = CFLAG_SET;
9695 } else if(res < corf)
9696 FLAG_X = FLAG_C = CFLAG_SET;
9698 FLAG_N = FLAG_X = FLAG_C = 0;
9700 res = MASK_OUT_ABOVE_8(res - corf);
9702 FLAG_V &= ~res; /* Undefined V behavior part II */
9703 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9706 m68ki_write_8(ea, res);
9710 M68KMAKE_OP(st, 8, ., d)
9716 M68KMAKE_OP(st, 8, ., .)
9718 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
9722 M68KMAKE_OP(sf, 8, ., d)
9728 M68KMAKE_OP(sf, 8, ., .)
9730 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
9734 M68KMAKE_OP(scc, 8, ., d)
9739 USE_CYCLES(CYC_SCC_R_TRUE);
9746 M68KMAKE_OP(scc, 8, ., .)
9748 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
9752 M68KMAKE_OP(stop, 0, ., .)
9756 uint new_sr = OPER_I_16();
9757 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9758 CPU_STOPPED |= STOP_LEVEL_STOP;
9759 m68ki_set_sr(new_sr);
9760 if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR])
9761 m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR];
9766 m68ki_exception_privilege_violation();
9770 M68KMAKE_OP(sub, 8, er, d)
9773 uint src = MASK_OUT_ABOVE_8(DY);
9774 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9775 uint res = dst - src;
9777 FLAG_N = NFLAG_8(res);
9778 FLAG_X = FLAG_C = CFLAG_8(res);
9779 FLAG_V = VFLAG_SUB_8(src, dst, res);
9780 FLAG_Z = MASK_OUT_ABOVE_8(res);
9782 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9786 M68KMAKE_OP(sub, 8, er, .)
9789 uint src = M68KMAKE_GET_OPER_AY_8;
9790 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9791 uint res = dst - src;
9793 FLAG_N = NFLAG_8(res);
9794 FLAG_X = FLAG_C = CFLAG_8(res);
9795 FLAG_V = VFLAG_SUB_8(src, dst, res);
9796 FLAG_Z = MASK_OUT_ABOVE_8(res);
9798 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9802 M68KMAKE_OP(sub, 16, er, d)
9805 uint src = MASK_OUT_ABOVE_16(DY);
9806 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9807 uint res = dst - src;
9809 FLAG_N = NFLAG_16(res);
9810 FLAG_X = FLAG_C = CFLAG_16(res);
9811 FLAG_V = VFLAG_SUB_16(src, dst, res);
9812 FLAG_Z = MASK_OUT_ABOVE_16(res);
9814 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9818 M68KMAKE_OP(sub, 16, er, a)
9821 uint src = MASK_OUT_ABOVE_16(AY);
9822 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9823 uint res = dst - src;
9825 FLAG_N = NFLAG_16(res);
9826 FLAG_X = FLAG_C = CFLAG_16(res);
9827 FLAG_V = VFLAG_SUB_16(src, dst, res);
9828 FLAG_Z = MASK_OUT_ABOVE_16(res);
9830 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9834 M68KMAKE_OP(sub, 16, er, .)
9837 uint src = M68KMAKE_GET_OPER_AY_16;
9838 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9839 uint res = dst - src;
9841 FLAG_N = NFLAG_16(res);
9842 FLAG_X = FLAG_C = CFLAG_16(res);
9843 FLAG_V = VFLAG_SUB_16(src, dst, res);
9844 FLAG_Z = MASK_OUT_ABOVE_16(res);
9846 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9850 M68KMAKE_OP(sub, 32, er, d)
9855 uint res = dst - src;
9857 FLAG_N = NFLAG_32(res);
9858 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9859 FLAG_V = VFLAG_SUB_32(src, dst, res);
9860 FLAG_Z = MASK_OUT_ABOVE_32(res);
9866 M68KMAKE_OP(sub, 32, er, a)
9871 uint res = dst - src;
9873 FLAG_N = NFLAG_32(res);
9874 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9875 FLAG_V = VFLAG_SUB_32(src, dst, res);
9876 FLAG_Z = MASK_OUT_ABOVE_32(res);
9882 M68KMAKE_OP(sub, 32, er, .)
9885 uint src = M68KMAKE_GET_OPER_AY_32;
9887 uint res = dst - src;
9889 FLAG_N = NFLAG_32(res);
9890 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9891 FLAG_V = VFLAG_SUB_32(src, dst, res);
9892 FLAG_Z = MASK_OUT_ABOVE_32(res);
9898 M68KMAKE_OP(sub, 8, re, .)
9900 uint ea = M68KMAKE_GET_EA_AY_8;
9901 uint src = MASK_OUT_ABOVE_8(DX);
9902 uint dst = m68ki_read_8(ea);
9903 uint res = dst - src;
9905 FLAG_N = NFLAG_8(res);
9906 FLAG_Z = MASK_OUT_ABOVE_8(res);
9907 FLAG_X = FLAG_C = CFLAG_8(res);
9908 FLAG_V = VFLAG_SUB_8(src, dst, res);
9910 m68ki_write_8(ea, FLAG_Z);
9914 M68KMAKE_OP(sub, 16, re, .)
9916 uint ea = M68KMAKE_GET_EA_AY_16;
9917 uint src = MASK_OUT_ABOVE_16(DX);
9918 uint dst = m68ki_read_16(ea);
9919 uint res = dst - src;
9921 FLAG_N = NFLAG_16(res);
9922 FLAG_Z = MASK_OUT_ABOVE_16(res);
9923 FLAG_X = FLAG_C = CFLAG_16(res);
9924 FLAG_V = VFLAG_SUB_16(src, dst, res);
9926 m68ki_write_16(ea, FLAG_Z);
9930 M68KMAKE_OP(sub, 32, re, .)
9932 uint ea = M68KMAKE_GET_EA_AY_32;
9934 uint dst = m68ki_read_32(ea);
9935 uint res = dst - src;
9937 FLAG_N = NFLAG_32(res);
9938 FLAG_Z = MASK_OUT_ABOVE_32(res);
9939 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9940 FLAG_V = VFLAG_SUB_32(src, dst, res);
9942 m68ki_write_32(ea, FLAG_Z);
9946 M68KMAKE_OP(suba, 16, ., d)
9950 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
9954 M68KMAKE_OP(suba, 16, ., a)
9958 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
9962 M68KMAKE_OP(suba, 16, ., .)
9965 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
9967 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9971 M68KMAKE_OP(suba, 32, ., d)
9975 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
9979 M68KMAKE_OP(suba, 32, ., a)
9983 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
9987 M68KMAKE_OP(suba, 32, ., .)
9989 uint src = M68KMAKE_GET_OPER_AY_32;
9992 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9996 M68KMAKE_OP(subi, 8, ., d)
9999 uint src = OPER_I_8();
10000 uint dst = MASK_OUT_ABOVE_8(*r_dst);
10001 uint res = dst - src;
10003 FLAG_N = NFLAG_8(res);
10004 FLAG_Z = MASK_OUT_ABOVE_8(res);
10005 FLAG_X = FLAG_C = CFLAG_8(res);
10006 FLAG_V = VFLAG_SUB_8(src, dst, res);
10008 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
10012 M68KMAKE_OP(subi, 8, ., .)
10014 uint src = OPER_I_8();
10015 uint ea = M68KMAKE_GET_EA_AY_8;
10016 uint dst = m68ki_read_8(ea);
10017 uint res = dst - src;
10019 FLAG_N = NFLAG_8(res);
10020 FLAG_Z = MASK_OUT_ABOVE_8(res);
10021 FLAG_X = FLAG_C = CFLAG_8(res);
10022 FLAG_V = VFLAG_SUB_8(src, dst, res);
10024 m68ki_write_8(ea, FLAG_Z);
10028 M68KMAKE_OP(subi, 16, ., d)
10031 uint src = OPER_I_16();
10032 uint dst = MASK_OUT_ABOVE_16(*r_dst);
10033 uint res = dst - src;
10035 FLAG_N = NFLAG_16(res);
10036 FLAG_Z = MASK_OUT_ABOVE_16(res);
10037 FLAG_X = FLAG_C = CFLAG_16(res);
10038 FLAG_V = VFLAG_SUB_16(src, dst, res);
10040 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
10044 M68KMAKE_OP(subi, 16, ., .)
10046 uint src = OPER_I_16();
10047 uint ea = M68KMAKE_GET_EA_AY_16;
10048 uint dst = m68ki_read_16(ea);
10049 uint res = dst - src;
10051 FLAG_N = NFLAG_16(res);
10052 FLAG_Z = MASK_OUT_ABOVE_16(res);
10053 FLAG_X = FLAG_C = CFLAG_16(res);
10054 FLAG_V = VFLAG_SUB_16(src, dst, res);
10056 m68ki_write_16(ea, FLAG_Z);
10060 M68KMAKE_OP(subi, 32, ., d)
10063 uint src = OPER_I_32();
10065 uint res = dst - src;
10067 FLAG_N = NFLAG_32(res);
10068 FLAG_Z = MASK_OUT_ABOVE_32(res);
10069 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10070 FLAG_V = VFLAG_SUB_32(src, dst, res);
10076 M68KMAKE_OP(subi, 32, ., .)
10078 uint src = OPER_I_32();
10079 uint ea = M68KMAKE_GET_EA_AY_32;
10080 uint dst = m68ki_read_32(ea);
10081 uint res = dst - src;
10083 FLAG_N = NFLAG_32(res);
10084 FLAG_Z = MASK_OUT_ABOVE_32(res);
10085 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10086 FLAG_V = VFLAG_SUB_32(src, dst, res);
10088 m68ki_write_32(ea, FLAG_Z);
10092 M68KMAKE_OP(subq, 8, ., d)
10095 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10096 uint dst = MASK_OUT_ABOVE_8(*r_dst);
10097 uint res = dst - src;
10099 FLAG_N = NFLAG_8(res);
10100 FLAG_Z = MASK_OUT_ABOVE_8(res);
10101 FLAG_X = FLAG_C = CFLAG_8(res);
10102 FLAG_V = VFLAG_SUB_8(src, dst, res);
10104 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
10108 M68KMAKE_OP(subq, 8, ., .)
10110 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10111 uint ea = M68KMAKE_GET_EA_AY_8;
10112 uint dst = m68ki_read_8(ea);
10113 uint res = dst - src;
10115 FLAG_N = NFLAG_8(res);
10116 FLAG_Z = MASK_OUT_ABOVE_8(res);
10117 FLAG_X = FLAG_C = CFLAG_8(res);
10118 FLAG_V = VFLAG_SUB_8(src, dst, res);
10120 m68ki_write_8(ea, FLAG_Z);
10124 M68KMAKE_OP(subq, 16, ., d)
10127 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10128 uint dst = MASK_OUT_ABOVE_16(*r_dst);
10129 uint res = dst - src;
10131 FLAG_N = NFLAG_16(res);
10132 FLAG_Z = MASK_OUT_ABOVE_16(res);
10133 FLAG_X = FLAG_C = CFLAG_16(res);
10134 FLAG_V = VFLAG_SUB_16(src, dst, res);
10136 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
10140 M68KMAKE_OP(subq, 16, ., a)
10144 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
10148 M68KMAKE_OP(subq, 16, ., .)
10150 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10151 uint ea = M68KMAKE_GET_EA_AY_16;
10152 uint dst = m68ki_read_16(ea);
10153 uint res = dst - src;
10155 FLAG_N = NFLAG_16(res);
10156 FLAG_Z = MASK_OUT_ABOVE_16(res);
10157 FLAG_X = FLAG_C = CFLAG_16(res);
10158 FLAG_V = VFLAG_SUB_16(src, dst, res);
10160 m68ki_write_16(ea, FLAG_Z);
10164 M68KMAKE_OP(subq, 32, ., d)
10167 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10169 uint res = dst - src;
10171 FLAG_N = NFLAG_32(res);
10172 FLAG_Z = MASK_OUT_ABOVE_32(res);
10173 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10174 FLAG_V = VFLAG_SUB_32(src, dst, res);
10180 M68KMAKE_OP(subq, 32, ., a)
10184 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
10188 M68KMAKE_OP(subq, 32, ., .)
10190 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10191 uint ea = M68KMAKE_GET_EA_AY_32;
10192 uint dst = m68ki_read_32(ea);
10193 uint res = dst - src;
10195 FLAG_N = NFLAG_32(res);
10196 FLAG_Z = MASK_OUT_ABOVE_32(res);
10197 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10198 FLAG_V = VFLAG_SUB_32(src, dst, res);
10200 m68ki_write_32(ea, FLAG_Z);
10204 M68KMAKE_OP(subx, 8, rr, .)
10207 uint src = MASK_OUT_ABOVE_8(DY);
10208 uint dst = MASK_OUT_ABOVE_8(*r_dst);
10209 uint res = dst - src - XFLAG_AS_1();
10211 FLAG_N = NFLAG_8(res);
10212 FLAG_X = FLAG_C = CFLAG_8(res);
10213 FLAG_V = VFLAG_SUB_8(src, dst, res);
10215 res = MASK_OUT_ABOVE_8(res);
10218 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
10222 M68KMAKE_OP(subx, 16, rr, .)
10225 uint src = MASK_OUT_ABOVE_16(DY);
10226 uint dst = MASK_OUT_ABOVE_16(*r_dst);
10227 uint res = dst - src - XFLAG_AS_1();
10229 FLAG_N = NFLAG_16(res);
10230 FLAG_X = FLAG_C = CFLAG_16(res);
10231 FLAG_V = VFLAG_SUB_16(src, dst, res);
10233 res = MASK_OUT_ABOVE_16(res);
10236 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
10240 M68KMAKE_OP(subx, 32, rr, .)
10245 uint res = dst - src - XFLAG_AS_1();
10247 FLAG_N = NFLAG_32(res);
10248 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10249 FLAG_V = VFLAG_SUB_32(src, dst, res);
10251 res = MASK_OUT_ABOVE_32(res);
10258 M68KMAKE_OP(subx, 8, mm, ax7)
10260 uint src = OPER_AY_PD_8();
10261 uint ea = EA_A7_PD_8();
10262 uint dst = m68ki_read_8(ea);
10263 uint res = dst - src - XFLAG_AS_1();
10265 FLAG_N = NFLAG_8(res);
10266 FLAG_X = FLAG_C = CFLAG_8(res);
10267 FLAG_V = VFLAG_SUB_8(src, dst, res);
10269 res = MASK_OUT_ABOVE_8(res);
10272 m68ki_write_8(ea, res);
10276 M68KMAKE_OP(subx, 8, mm, ay7)
10278 uint src = OPER_A7_PD_8();
10279 uint ea = EA_AX_PD_8();
10280 uint dst = m68ki_read_8(ea);
10281 uint res = dst - src - XFLAG_AS_1();
10283 FLAG_N = NFLAG_8(res);
10284 FLAG_X = FLAG_C = CFLAG_8(res);
10285 FLAG_V = VFLAG_SUB_8(src, dst, res);
10287 res = MASK_OUT_ABOVE_8(res);
10290 m68ki_write_8(ea, res);
10294 M68KMAKE_OP(subx, 8, mm, axy7)
10296 uint src = OPER_A7_PD_8();
10297 uint ea = EA_A7_PD_8();
10298 uint dst = m68ki_read_8(ea);
10299 uint res = dst - src - XFLAG_AS_1();
10301 FLAG_N = NFLAG_8(res);
10302 FLAG_X = FLAG_C = CFLAG_8(res);
10303 FLAG_V = VFLAG_SUB_8(src, dst, res);
10305 res = MASK_OUT_ABOVE_8(res);
10308 m68ki_write_8(ea, res);
10312 M68KMAKE_OP(subx, 8, mm, .)
10314 uint src = OPER_AY_PD_8();
10315 uint ea = EA_AX_PD_8();
10316 uint dst = m68ki_read_8(ea);
10317 uint res = dst - src - XFLAG_AS_1();
10319 FLAG_N = NFLAG_8(res);
10320 FLAG_X = FLAG_C = CFLAG_8(res);
10321 FLAG_V = VFLAG_SUB_8(src, dst, res);
10323 res = MASK_OUT_ABOVE_8(res);
10326 m68ki_write_8(ea, res);
10330 M68KMAKE_OP(subx, 16, mm, .)
10332 uint src = OPER_AY_PD_16();
10333 uint ea = EA_AX_PD_16();
10334 uint dst = m68ki_read_16(ea);
10335 uint res = dst - src - XFLAG_AS_1();
10337 FLAG_N = NFLAG_16(res);
10338 FLAG_X = FLAG_C = CFLAG_16(res);
10339 FLAG_V = VFLAG_SUB_16(src, dst, res);
10341 res = MASK_OUT_ABOVE_16(res);
10344 m68ki_write_16(ea, res);
10348 M68KMAKE_OP(subx, 32, mm, .)
10350 uint src = OPER_AY_PD_32();
10351 uint ea = EA_AX_PD_32();
10352 uint dst = m68ki_read_32(ea);
10353 uint res = dst - src - XFLAG_AS_1();
10355 FLAG_N = NFLAG_32(res);
10356 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10357 FLAG_V = VFLAG_SUB_32(src, dst, res);
10359 res = MASK_OUT_ABOVE_32(res);
10362 m68ki_write_32(ea, res);
10366 M68KMAKE_OP(swap, 32, ., .)
10370 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
10371 *r_dst = (*r_dst>>16) | FLAG_Z;
10374 FLAG_N = NFLAG_32(*r_dst);
10375 FLAG_C = CFLAG_CLEAR;
10376 FLAG_V = VFLAG_CLEAR;
10380 M68KMAKE_OP(tas, 8, ., d)
10384 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
10385 FLAG_N = NFLAG_8(*r_dst);
10386 FLAG_V = VFLAG_CLEAR;
10387 FLAG_C = CFLAG_CLEAR;
10392 M68KMAKE_OP(tas, 8, ., .)
10394 uint ea = M68KMAKE_GET_EA_AY_8;
10395 uint dst = m68ki_read_8(ea);
10396 uint allow_writeback;
10399 FLAG_N = NFLAG_8(dst);
10400 FLAG_V = VFLAG_CLEAR;
10401 FLAG_C = CFLAG_CLEAR;
10403 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
10404 disabled in order to function properly. Some Amiga software may also rely
10405 on this, but only when accessing specific addresses so additional functionality
10407 allow_writeback = m68ki_tas_callback();
10409 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
10413 M68KMAKE_OP(trap, 0, ., .)
10415 /* Trap#n stacks exception frame type 0 */
10416 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
10420 M68KMAKE_OP(trapt, 0, ., .)
10422 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10424 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10427 m68ki_exception_illegal();
10431 M68KMAKE_OP(trapt, 16, ., .)
10433 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10435 // TODO: review this... as mame is not using it...
10436 REG_PC += 2; // JFF else stackframe & return addresses are incorrect
10437 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10440 m68ki_exception_illegal();
10444 M68KMAKE_OP(trapt, 32, ., .)
10446 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10448 // TODO: review this... as mame is not using it...
10449 REG_PC += 4; // JFF else stackframe & return addresses are incorrect
10450 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10453 m68ki_exception_illegal();
10457 M68KMAKE_OP(trapf, 0, ., .)
10459 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10463 m68ki_exception_illegal();
10467 M68KMAKE_OP(trapf, 16, ., .)
10469 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10474 m68ki_exception_illegal();
10478 M68KMAKE_OP(trapf, 32, ., .)
10480 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10485 m68ki_exception_illegal();
10489 M68KMAKE_OP(trapcc, 0, ., .)
10491 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10494 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10497 m68ki_exception_illegal();
10501 M68KMAKE_OP(trapcc, 16, ., .)
10503 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10505 // TODO: review this... as mame is not using it...
10506 REG_PC += 2; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10509 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10515 m68ki_exception_illegal();
10519 M68KMAKE_OP(trapcc, 32, ., .)
10521 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10523 // TODO: review this... as mame is not using it...
10524 REG_PC += 4; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10527 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10532 m68ki_exception_illegal();
10536 M68KMAKE_OP(trapv, 0, ., .)
10542 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10546 M68KMAKE_OP(tst, 8, ., d)
10548 uint res = MASK_OUT_ABOVE_8(DY);
10550 FLAG_N = NFLAG_8(res);
10552 FLAG_V = VFLAG_CLEAR;
10553 FLAG_C = CFLAG_CLEAR;
10557 M68KMAKE_OP(tst, 8, ., .)
10559 uint res = M68KMAKE_GET_OPER_AY_8;
10561 FLAG_N = NFLAG_8(res);
10563 FLAG_V = VFLAG_CLEAR;
10564 FLAG_C = CFLAG_CLEAR;
10568 M68KMAKE_OP(tst, 8, ., pcdi)
10570 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10572 uint res = OPER_PCDI_8();
10574 FLAG_N = NFLAG_8(res);
10576 FLAG_V = VFLAG_CLEAR;
10577 FLAG_C = CFLAG_CLEAR;
10580 m68ki_exception_illegal();
10584 M68KMAKE_OP(tst, 8, ., pcix)
10586 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10588 uint res = OPER_PCIX_8();
10590 FLAG_N = NFLAG_8(res);
10592 FLAG_V = VFLAG_CLEAR;
10593 FLAG_C = CFLAG_CLEAR;
10596 m68ki_exception_illegal();
10600 M68KMAKE_OP(tst, 8, ., i)
10602 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10604 uint res = OPER_I_8();
10606 FLAG_N = NFLAG_8(res);
10608 FLAG_V = VFLAG_CLEAR;
10609 FLAG_C = CFLAG_CLEAR;
10612 m68ki_exception_illegal();
10616 M68KMAKE_OP(tst, 16, ., d)
10618 uint res = MASK_OUT_ABOVE_16(DY);
10620 FLAG_N = NFLAG_16(res);
10622 FLAG_V = VFLAG_CLEAR;
10623 FLAG_C = CFLAG_CLEAR;
10627 M68KMAKE_OP(tst, 16, ., a)
10629 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10631 uint res = MAKE_INT_16(AY);
10633 FLAG_N = NFLAG_16(res);
10635 FLAG_V = VFLAG_CLEAR;
10636 FLAG_C = CFLAG_CLEAR;
10639 m68ki_exception_illegal();
10643 M68KMAKE_OP(tst, 16, ., .)
10645 uint res = M68KMAKE_GET_OPER_AY_16;
10647 FLAG_N = NFLAG_16(res);
10649 FLAG_V = VFLAG_CLEAR;
10650 FLAG_C = CFLAG_CLEAR;
10654 M68KMAKE_OP(tst, 16, ., pcdi)
10656 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10658 uint res = OPER_PCDI_16();
10660 FLAG_N = NFLAG_16(res);
10662 FLAG_V = VFLAG_CLEAR;
10663 FLAG_C = CFLAG_CLEAR;
10666 m68ki_exception_illegal();
10670 M68KMAKE_OP(tst, 16, ., pcix)
10672 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10674 uint res = OPER_PCIX_16();
10676 FLAG_N = NFLAG_16(res);
10678 FLAG_V = VFLAG_CLEAR;
10679 FLAG_C = CFLAG_CLEAR;
10682 m68ki_exception_illegal();
10686 M68KMAKE_OP(tst, 16, ., i)
10688 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10690 uint res = OPER_I_16();
10692 FLAG_N = NFLAG_16(res);
10694 FLAG_V = VFLAG_CLEAR;
10695 FLAG_C = CFLAG_CLEAR;
10698 m68ki_exception_illegal();
10702 M68KMAKE_OP(tst, 32, ., d)
10706 FLAG_N = NFLAG_32(res);
10708 FLAG_V = VFLAG_CLEAR;
10709 FLAG_C = CFLAG_CLEAR;
10713 M68KMAKE_OP(tst, 32, ., a)
10715 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10719 FLAG_N = NFLAG_32(res);
10721 FLAG_V = VFLAG_CLEAR;
10722 FLAG_C = CFLAG_CLEAR;
10725 m68ki_exception_illegal();
10729 M68KMAKE_OP(tst, 32, ., .)
10731 uint res = M68KMAKE_GET_OPER_AY_32;
10733 FLAG_N = NFLAG_32(res);
10735 FLAG_V = VFLAG_CLEAR;
10736 FLAG_C = CFLAG_CLEAR;
10740 M68KMAKE_OP(tst, 32, ., pcdi)
10742 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10744 uint res = OPER_PCDI_32();
10746 FLAG_N = NFLAG_32(res);
10748 FLAG_V = VFLAG_CLEAR;
10749 FLAG_C = CFLAG_CLEAR;
10752 m68ki_exception_illegal();
10756 M68KMAKE_OP(tst, 32, ., pcix)
10758 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10760 uint res = OPER_PCIX_32();
10762 FLAG_N = NFLAG_32(res);
10764 FLAG_V = VFLAG_CLEAR;
10765 FLAG_C = CFLAG_CLEAR;
10768 m68ki_exception_illegal();
10772 M68KMAKE_OP(tst, 32, ., i)
10774 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10776 uint res = OPER_I_32();
10778 FLAG_N = NFLAG_32(res);
10780 FLAG_V = VFLAG_CLEAR;
10781 FLAG_C = CFLAG_CLEAR;
10784 m68ki_exception_illegal();
10788 M68KMAKE_OP(unlk, 32, ., a7)
10790 REG_A[7] = m68ki_read_32(REG_A[7]);
10794 M68KMAKE_OP(unlk, 32, ., .)
10799 *r_dst = m68ki_pull_32();
10803 M68KMAKE_OP(unpk, 16, rr, .)
10805 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10807 /* Note: DX and DY are reversed in Motorola's docs */
10811 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
10814 m68ki_exception_illegal();
10818 M68KMAKE_OP(unpk, 16, mm, ax7)
10820 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10822 /* Note: AX and AY are reversed in Motorola's docs */
10823 uint src = OPER_AY_PD_8();
10826 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10827 ea_dst = EA_A7_PD_8();
10828 m68ki_write_8(ea_dst, src & 0xff);
10829 ea_dst = EA_A7_PD_8();
10830 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10833 m68ki_exception_illegal();
10837 M68KMAKE_OP(unpk, 16, mm, ay7)
10839 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10841 /* Note: AX and AY are reversed in Motorola's docs */
10842 uint src = OPER_A7_PD_8();
10845 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10846 ea_dst = EA_AX_PD_8();
10847 m68ki_write_8(ea_dst, src & 0xff);
10848 ea_dst = EA_AX_PD_8();
10849 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10852 m68ki_exception_illegal();
10856 M68KMAKE_OP(unpk, 16, mm, axy7)
10858 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10860 uint src = OPER_A7_PD_8();
10863 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10864 ea_dst = EA_A7_PD_8();
10865 m68ki_write_8(ea_dst, src & 0xff);
10866 ea_dst = EA_A7_PD_8();
10867 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10870 m68ki_exception_illegal();
10874 M68KMAKE_OP(unpk, 16, mm, .)
10876 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10878 /* Note: AX and AY are reversed in Motorola's docs */
10879 uint src = OPER_AY_PD_8();
10882 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10883 ea_dst = EA_AX_PD_8();
10884 m68ki_write_8(ea_dst, src & 0xff);
10885 ea_dst = EA_AX_PD_8();
10886 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10889 m68ki_exception_illegal();
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projects / pistorm / blob