6 /* ======================================================================== */
7 /* ========================= LICENSING & COPYRIGHT ======================== */
8 /* ======================================================================== */
13 * A portable Motorola M680x0 processor emulation engine.
14 * Copyright Karl Stenerud. All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a copy
17 * of this software and associated documentation files (the "Software"), to deal
18 * in the Software without restriction, including without limitation the rights
19 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
20 * copies of the Software, and to permit persons to whom the Software is
21 * furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice shall be included in
24 * all copies or substantial portions of the Software.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
28 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
29 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
30 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
31 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 /* Special thanks to Bart Trzynadlowski for his insight into the
36 * undocumented features of this chip:
38 * http://dynarec.com/~bart/files/68knotes.txt
42 /* Input file for m68kmake
43 * -----------------------
45 * All sections begin with 80 X's in a row followed by an end-of-line
47 * After this, m68kmake will expect to find one of the following section
49 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
50 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
51 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
52 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
53 * M68KMAKE_TABLE_BODY - the table itself
54 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
55 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
56 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
58 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
59 * M68KMAKE_TABLE_BODY must be second last in the file.
61 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
62 * primitives themselves. Each opcode handler begins with:
63 * M68KMAKE_OP(A, B, C, D)
65 * where A is the opcode handler name, B is the size of the operation,
66 * C denotes any special processing mode, and D denotes a specific
68 * For C and D where nothing is specified, use "."
71 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
72 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
73 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
75 * All opcode handler primitives end with a closing curly brace "}" at column 1
77 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
78 * and do not put a closing curly brace at column 1 unless it is
79 * marking the end of the handler!
81 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
82 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
83 * opcode handlers to handle variations in the opcode handler.
84 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
85 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
86 * be interpreted on instructions where the corresponding table entry
87 * specifies multiple effective addressing modes.
89 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
91 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
92 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
93 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
96 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
97 M68KMAKE_PROTOTYPE_HEADER
99 #ifndef M68KOPS__HEADER
100 #define M68KOPS__HEADER
102 /* ======================================================================== */
103 /* ============================ OPCODE HANDLERS =========================== */
104 /* ======================================================================== */
108 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
109 M68KMAKE_PROTOTYPE_FOOTER
112 /* Build the opcode handler table */
113 void m68ki_build_opcode_table(void);
115 struct m68ki_cpu_core;
117 extern void (*m68ki_instruction_jump_table[0x10000])(struct m68ki_cpu_core *state); /* opcode handler jump table */
118 extern unsigned char m68ki_cycles[][0x10000];
121 /* ======================================================================== */
122 /* ============================== END OF FILE ============================= */
123 /* ======================================================================== */
125 #endif /* M68KOPS__HEADER */
129 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
130 M68KMAKE_TABLE_HEADER
132 /* ======================================================================== */
133 /* ========================= OPCODE TABLE BUILDER ========================= */
134 /* ======================================================================== */
139 #define NUM_CPU_TYPES 5
141 void (*m68ki_instruction_jump_table[0x10000])(m68ki_cpu_core *state); /* opcode handler jump table */
142 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
144 /* This is used to generate the opcode handler jump table */
147 void (*opcode_handler)(m68ki_cpu_core *state); /* handler function */
148 unsigned int mask; /* mask on opcode */
149 unsigned int match; /* what to match after masking */
150 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
151 } opcode_handler_struct;
154 /* Opcode handler table */
155 static const opcode_handler_struct m68k_opcode_handler_table[] =
157 /* function mask match 000 010 020 040 */
161 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
162 M68KMAKE_TABLE_FOOTER
164 {0, 0, 0, {0, 0, 0, 0, 0}}
168 /* Build the opcode handler jump table */
169 void m68ki_build_opcode_table(void)
171 const opcode_handler_struct *ostruct;
178 for(i = 0; i < 0x10000; i++)
180 /* default to illegal */
181 m68ki_instruction_jump_table[i] = m68k_op_illegal;
182 for(k=0;k<NUM_CPU_TYPES;k++)
183 m68ki_cycles[k][i] = 0;
186 ostruct = m68k_opcode_handler_table;
187 while(ostruct->mask != 0xff00)
189 for(i = 0;i < 0x10000;i++)
191 if((i & ostruct->mask) == ostruct->match)
193 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
194 for(k=0;k<NUM_CPU_TYPES;k++)
195 m68ki_cycles[k][i] = ostruct->cycles[k];
200 while(ostruct->mask == 0xff00)
202 for(i = 0;i <= 0xff;i++)
204 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
205 for(k=0;k<NUM_CPU_TYPES;k++)
206 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
210 while(ostruct->mask == 0xf1f8)
216 instr = ostruct->match | (i << 9) | j;
217 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
218 for(k=0;k<NUM_CPU_TYPES;k++)
219 m68ki_cycles[k][instr] = ostruct->cycles[k];
220 // For all shift operations with known shift distance (encoded in instruction word)
221 if((instr & 0xf000) == 0xe000 && (!(instr & 0x20)))
223 // On the 68000 and 68010 shift distance affect execution time.
224 // Add the cycle cost of shifting; 2 times the shift distance
225 cycle_cost = ((((i-1)&7)+1)<<1);
226 m68ki_cycles[0][instr] += cycle_cost;
227 m68ki_cycles[1][instr] += cycle_cost;
228 // On the 68020 shift distance does not affect execution time
229 m68ki_cycles[2][instr] += 0;
235 while(ostruct->mask == 0xfff0)
237 for(i = 0;i <= 0x0f;i++)
239 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
240 for(k=0;k<NUM_CPU_TYPES;k++)
241 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
245 while(ostruct->mask == 0xf1ff)
247 for(i = 0;i <= 0x07;i++)
249 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
250 for(k=0;k<NUM_CPU_TYPES;k++)
251 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
255 while(ostruct->mask == 0xfff8)
257 for(i = 0;i <= 0x07;i++)
259 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
260 for(k=0;k<NUM_CPU_TYPES;k++)
261 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
265 while(ostruct->mask == 0xffff)
267 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
268 for(k=0;k<NUM_CPU_TYPES;k++)
269 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
275 /* ======================================================================== */
276 /* ============================== END OF FILE ============================= */
277 /* ======================================================================== */
281 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
282 M68KMAKE_OPCODE_HANDLER_HEADER
286 extern void m68040_fpu_op0(m68ki_cpu_core *state);
287 extern void m68040_fpu_op1(m68ki_cpu_core *state);
288 extern void m68851_mmu_ops(m68ki_cpu_core *state);
289 extern void m68881_ftrap(m68ki_cpu_core *state);
291 /* ======================================================================== */
292 /* ========================= INSTRUCTION HANDLERS ========================= */
293 /* ======================================================================== */
297 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
298 M68KMAKE_OPCODE_HANDLER_FOOTER
300 /* ======================================================================== */
301 /* ============================== END OF FILE ============================= */
302 /* ======================================================================== */
306 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
309 The following table is arranged as follows:
311 name: Opcode mnemonic
315 spec proc: Special processing mode:
319 rr: register to register
321 er: effective address to register
322 re: register to effective address
323 dd: data register to data register
324 da: data register to address register
325 aa: address register to address register
326 cr: control register to register
327 rc: register to control register
328 toc: to condition code register
329 tos: to status register
330 tou: to user stack pointer
331 frc: from condition code register
332 frs: from status register
333 fru: from user stack pointer
334 * for move.x, the special processing mode is a specific
335 destination effective addressing mode.
337 spec ea: Specific effective addressing mode:
342 ai: address register indirect
343 pi: address register indirect with postincrement
344 pd: address register indirect with predecrement
345 di: address register indirect with displacement
346 ix: address register indirect with index
347 aw: absolute word address
348 al: absolute long address
349 pcdi: program counter relative with displacement
350 pcix: program counter relative with index
351 a7: register specified in instruction is A7
352 ax7: register field X of instruction is A7
353 ay7: register field Y of instruction is A7
354 axy7: register fields X and Y of instruction are A7
356 bit pattern: Pattern to recognize this opcode. "." means don't care.
358 allowed ea: List of allowed addressing modes:
360 A: address register indirect
361 +: ARI (address register indirect) with postincrement
362 -: ARI with predecrement
363 D: ARI with displacement
365 W: absolute word address
366 L: absolute long address
367 d: program counter indirect with displacement
368 x: program counter indirect with index
370 mode: CPU operating mode for each cpu type. U = user or supervisor,
371 S = supervisor only, "." = opcode not present.
373 cpu cycles: Base number of cycles required to execute this opcode on the
375 Use "." if CPU does not have this opcode.
379 spec spec allowed ea mode cpu cycles
380 name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 000 010 020 030 040 comments
381 ====== ==== ==== ==== ================ ========== = = = = = === === === === === =============
383 1010 0 . . 1010............ .......... U U U U U 4 4 4 4 4
384 1111 0 . . 1111............ .......... U U U U U 4 4 4 4 4
385 040fpu0 32 . . 11110010........ .......... . . . . U . . . . 0
386 040fpu1 32 . . 11110011........ .......... . . . . U . . . . 0
387 abcd 8 rr . 1100...100000... .......... U U U U U 6 6 4 4 4
388 abcd 8 mm ax7 1100111100001... .......... U U U U U 18 18 16 16 16
389 abcd 8 mm ay7 1100...100001111 .......... U U U U U 18 18 16 16 16
390 abcd 8 mm axy7 1100111100001111 .......... U U U U U 18 18 16 16 16
391 abcd 8 mm . 1100...100001... .......... U U U U U 18 18 16 16 16
392 add 8 er d 1101...000000... .......... U U U U U 4 4 2 2 2
393 add 8 er . 1101...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
394 add 16 er d 1101...001000... .......... U U U U U 4 4 2 2 2
395 add 16 er a 1101...001001... .......... U U U U U 4 4 2 2 2
396 add 16 er . 1101...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
397 add 32 er d 1101...010000... .......... U U U U U 6 6 2 2 2
398 add 32 er a 1101...010001... .......... U U U U U 6 6 2 2 2
399 add 32 er . 1101...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
400 add 8 re . 1101...100...... A+-DXWL... U U U U U 8 8 4 4 4
401 add 16 re . 1101...101...... A+-DXWL... U U U U U 8 8 4 4 4
402 add 32 re . 1101...110...... A+-DXWL... U U U U U 12 12 4 4 4
403 adda 16 . d 1101...011000... .......... U U U U U 8 8 2 2 2
404 adda 16 . a 1101...011001... .......... U U U U U 8 8 2 2 2
405 adda 16 . . 1101...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
406 adda 32 . d 1101...111000... .......... U U U U U 6 6 2 2 2
407 adda 32 . a 1101...111001... .......... U U U U U 6 6 2 2 2
408 adda 32 . . 1101...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
409 addi 8 . d 0000011000000... .......... U U U U U 8 8 2 2 2
410 addi 8 . . 0000011000...... A+-DXWL... U U U U U 12 12 4 4 4
411 addi 16 . d 0000011001000... .......... U U U U U 8 8 2 2 2
412 addi 16 . . 0000011001...... A+-DXWL... U U U U U 12 12 4 4 4
413 addi 32 . d 0000011010000... .......... U U U U U 16 14 2 2 2
414 addi 32 . . 0000011010...... A+-DXWL... U U U U U 20 20 4 4 4
415 addq 8 . d 0101...000000... .......... U U U U U 4 4 2 2 2
416 addq 8 . . 0101...000...... A+-DXWL... U U U U U 8 8 4 4 4
417 addq 16 . d 0101...001000... .......... U U U U U 4 4 2 2 2
418 addq 16 . a 0101...001001... .......... U U U U U 4 4 2 2 2
419 addq 16 . . 0101...001...... A+-DXWL... U U U U U 8 8 4 4 4
420 addq 32 . d 0101...010000... .......... U U U U U 8 8 2 2 2
421 addq 32 . a 0101...010001... .......... U U U U U 8 8 2 2 2
422 addq 32 . . 0101...010...... A+-DXWL... U U U U U 12 12 4 4 4
423 addx 8 rr . 1101...100000... .......... U U U U U 4 4 2 2 2
424 addx 16 rr . 1101...101000... .......... U U U U U 4 4 2 2 2
425 addx 32 rr . 1101...110000... .......... U U U U U 8 6 2 2 2
426 addx 8 mm ax7 1101111100001... .......... U U U U U 18 18 12 12 12
427 addx 8 mm ay7 1101...100001111 .......... U U U U U 18 18 12 12 12
428 addx 8 mm axy7 1101111100001111 .......... U U U U U 18 18 12 12 12
429 addx 8 mm . 1101...100001... .......... U U U U U 18 18 12 12 12
430 addx 16 mm . 1101...101001... .......... U U U U U 18 18 12 12 12
431 addx 32 mm . 1101...110001... .......... U U U U U 30 30 12 12 12
432 and 8 er d 1100...000000... .......... U U U U U 4 4 2 2 2
433 and 8 er . 1100...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
434 and 16 er d 1100...001000... .......... U U U U U 4 4 2 2 2
435 and 16 er . 1100...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
436 and 32 er d 1100...010000... .......... U U U U U 6 6 2 2 2
437 and 32 er . 1100...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
438 and 8 re . 1100...100...... A+-DXWL... U U U U U 8 8 4 4 4
439 and 16 re . 1100...101...... A+-DXWL... U U U U U 8 8 4 4 4
440 and 32 re . 1100...110...... A+-DXWL... U U U U U 12 12 4 4 4
441 andi 16 toc . 0000001000111100 .......... U U U U U 20 16 12 12 12
442 andi 16 tos . 0000001001111100 .......... S S S S S 20 16 12 12 12
443 andi 8 . d 0000001000000... .......... U U U U U 8 8 2 2 2
444 andi 8 . . 0000001000...... A+-DXWL... U U U U U 12 12 4 4 4
445 andi 16 . d 0000001001000... .......... U U U U U 8 8 2 2 2
446 andi 16 . . 0000001001...... A+-DXWL... U U U U U 12 12 4 4 4
447 andi 32 . d 0000001010000... .......... U U U U U 14 14 2 2 2
448 andi 32 . . 0000001010...... A+-DXWL... U U U U U 20 20 4 4 4
449 asr 8 s . 1110...000000... .......... U U U U U 6 6 6 6 6
450 asr 16 s . 1110...001000... .......... U U U U U 6 6 6 6 6
451 asr 32 s . 1110...010000... .......... U U U U U 8 8 6 6 6
452 asr 8 r . 1110...000100... .......... U U U U U 6 6 6 6 6
453 asr 16 r . 1110...001100... .......... U U U U U 6 6 6 6 6
454 asr 32 r . 1110...010100... .......... U U U U U 8 8 6 6 6
455 asr 16 . . 1110000011...... A+-DXWL... U U U U U 8 8 5 5 5
456 asl 8 s . 1110...100000... .......... U U U U U 6 6 8 8 8
457 asl 16 s . 1110...101000... .......... U U U U U 6 6 8 8 8
458 asl 32 s . 1110...110000... .......... U U U U U 8 8 8 8 8
459 asl 8 r . 1110...100100... .......... U U U U U 6 6 8 8 8
460 asl 16 r . 1110...101100... .......... U U U U U 6 6 8 8 8
461 asl 32 r . 1110...110100... .......... U U U U U 8 8 8 8 8
462 asl 16 . . 1110000111...... A+-DXWL... U U U U U 8 8 6 6 6
463 bcc 8 . . 0110............ .......... U U U U U 10 10 6 6 6
464 bcc 16 . . 0110....00000000 .......... U U U U U 10 10 6 6 6
465 bcc 32 . . 0110....11111111 .......... U U U U U 10 10 6 6 6
466 bchg 8 r . 0000...101...... A+-DXWL... U U U U U 8 8 4 4 4
467 bchg 32 r d 0000...101000... .......... U U U U U 8 8 4 4 4
468 bchg 8 s . 0000100001...... A+-DXWL... U U U U U 12 12 4 4 4
469 bchg 32 s d 0000100001000... .......... U U U U U 12 12 4 4 4
470 bclr 8 r . 0000...110...... A+-DXWL... U U U U U 8 10 4 4 4
471 bclr 32 r d 0000...110000... .......... U U U U U 10 10 4 4 4
472 bclr 8 s . 0000100010...... A+-DXWL... U U U U U 12 12 4 4 4
473 bclr 32 s d 0000100010000... .......... U U U U U 14 14 4 4 4
474 bfchg 32 . d 1110101011000... .......... . . U U U . . 12 12 12 timing not quite correct
475 bfchg 32 . . 1110101011...... A..DXWL... . . U U U . . 20 20 20
476 bfclr 32 . d 1110110011000... .......... . . U U U . . 12 12 12
477 bfclr 32 . . 1110110011...... A..DXWL... . . U U U . . 20 20 20
478 bfexts 32 . d 1110101111000... .......... . . U U U . . 8 8 8
479 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U . . 15 15 15
480 bfextu 32 . d 1110100111000... .......... . . U U U . . 8 8 8
481 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U . . 15 15 15
482 bfffo 32 . d 1110110111000... .......... . . U U U . . 18 18 18
483 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U . . 28 28 28
484 bfins 32 . d 1110111111000... .......... . . U U U . . 10 10 10
485 bfins 32 . . 1110111111...... A..DXWL... . . U U U . . 17 17 17
486 bfset 32 . d 1110111011000... .......... . . U U U . . 12 12 12
487 bfset 32 . . 1110111011...... A..DXWL... . . U U U . . 20 20 20
488 bftst 32 . d 1110100011000... .......... . . U U U . . 6 6 6
489 bftst 32 . . 1110100011...... A..DXWLdx. . . U U U . . 13 13 13
490 bkpt 0 . . 0100100001001... .......... . U U U U . 10 10 10 10
491 bra 8 . . 01100000........ .......... U U U U U 10 10 10 10 10
492 bra 16 . . 0110000000000000 .......... U U U U U 10 10 10 10 10
493 bra 32 . . 0110000011111111 .......... U U U U U 10 10 10 10 10
494 bset 32 r d 0000...111000... .......... U U U U U 8 8 4 4 4
495 bset 8 r . 0000...111...... A+-DXWL... U U U U U 8 8 4 4 4
496 bset 8 s . 0000100011...... A+-DXWL... U U U U U 12 12 4 4 4
497 bset 32 s d 0000100011000... .......... U U U U U 12 12 4 4 4
498 bsr 8 . . 01100001........ .......... U U U U U 18 18 7 7 7
499 bsr 16 . . 0110000100000000 .......... U U U U U 18 18 7 7 7
500 bsr 32 . . 0110000111111111 .......... U U U U U 18 18 7 7 7
501 btst 8 r . 0000...100...... A+-DXWLdxI U U U U U 4 4 4 4 4
502 btst 32 r d 0000...100000... .......... U U U U U 6 6 4 4 4
503 btst 8 s . 0000100000...... A+-DXWLdx. U U U U U 8 8 4 4 4
504 btst 32 s d 0000100000000... .......... U U U U U 10 10 4 4 4
505 callm 32 . . 0000011011...... A..DXWLdx. . . U U U . . 60 60 60 not properly emulated
506 cas 8 . . 0000101011...... A+-DXWL... . . U U U . . 12 12 12
507 cas 16 . . 0000110011...... A+-DXWL... . . U U U . . 12 12 12
508 cas 32 . . 0000111011...... A+-DXWL... . . U U U . . 12 12 12
509 cas2 16 . . 0000110011111100 .......... . . U U U . . 12 12 12
510 cas2 32 . . 0000111011111100 .......... . . U U U . . 12 12 12
511 chk 16 . d 0100...110000... .......... U U U U U 10 8 8 8 8
512 chk 16 . . 0100...110...... A+-DXWLdxI U U U U U 10 8 8 8 8
513 chk 32 . d 0100...100000... .......... . . U U U . . 8 8 8
514 chk 32 . . 0100...100...... A+-DXWLdxI . . U U U . . 8 8 8
515 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U . . 23 23 23
516 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U . . 23 23 23
517 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U . . 18 18 18
518 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U . . 23 23 23
519 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U . . 23 23 23
520 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U . . 18 18 18
521 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U . . 23 23 23
522 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U . . 23 23 23
523 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U . . 18 18 18
524 clr 8 . d 0100001000000... .......... U U U U U 4 4 2 2 2
525 clr 8 . . 0100001000...... A+-DXWL... U U U U U 8 4 4 4 4
526 clr 16 . d 0100001001000... .......... U U U U U 4 4 2 2 2
527 clr 16 . . 0100001001...... A+-DXWL... U U U U U 8 4 4 4 4
528 clr 32 . d 0100001010000... .......... U U U U U 6 6 2 2 2
529 clr 32 . . 0100001010...... A+-DXWL... U U U U U 12 6 4 4 4
530 cmp 8 . d 1011...000000... .......... U U U U U 4 4 2 2 2
531 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
532 cmp 16 . d 1011...001000... .......... U U U U U 4 4 2 2 2
533 cmp 16 . a 1011...001001... .......... U U U U U 4 4 2 2 2
534 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
535 cmp 32 . d 1011...010000... .......... U U U U U 6 6 2 2 2
536 cmp 32 . a 1011...010001... .......... U U U U U 6 6 2 2 2
537 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
538 cmpa 16 . d 1011...011000... .......... U U U U U 6 6 4 4 4
539 cmpa 16 . a 1011...011001... .......... U U U U U 6 6 4 4 4
540 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U 6 6 4 4 4
541 cmpa 32 . d 1011...111000... .......... U U U U U 6 6 4 4 4
542 cmpa 32 . a 1011...111001... .......... U U U U U 6 6 4 4 4
543 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U 6 6 4 4 4
544 cmpi 8 . d 0000110000000... .......... U U U U U 8 8 2 2 2
545 cmpi 8 . . 0000110000...... A+-DXWL... U U U U U 8 8 2 2 2
546 cmpi 8 . pcdi 0000110000111010 .......... . . U U U . . 7 7 7
547 cmpi 8 . pcix 0000110000111011 .......... . . U U U . . 9 9 9
548 cmpi 16 . d 0000110001000... .......... U U U U U 8 8 2 2 2
549 cmpi 16 . . 0000110001...... A+-DXWL... U U U U U 8 8 2 2 2
550 cmpi 16 . pcdi 0000110001111010 .......... . . U U U . . 7 7 7
551 cmpi 16 . pcix 0000110001111011 .......... . . U U U . . 9 9 9
552 cmpi 32 . d 0000110010000... .......... U U U U U 14 12 2 2 2
553 cmpi 32 . . 0000110010...... A+-DXWL... U U U U U 12 12 2 2 2
554 cmpi 32 . pcdi 0000110010111010 .......... . . U U U . . 7 7 7
555 cmpi 32 . pcix 0000110010111011 .......... . . U U U . . 9 9 9
556 cmpm 8 . ax7 1011111100001... .......... U U U U U 12 12 9 9 9
557 cmpm 8 . ay7 1011...100001111 .......... U U U U U 12 12 9 9 9
558 cmpm 8 . axy7 1011111100001111 .......... U U U U U 12 12 9 9 9
559 cmpm 8 . . 1011...100001... .......... U U U U U 12 12 9 9 9
560 cmpm 16 . . 1011...101001... .......... U U U U U 12 12 9 9 9
561 cmpm 32 . . 1011...110001... .......... U U U U U 20 20 9 9 9
562 cpbcc 32 . . 1111...01....... .......... . . U U . . . 4 4 . unemulated
563 cpdbcc 32 . . 1111...001001... .......... . . U U . . . 4 4 . unemulated
564 cpgen 32 . . 1111...000...... .......... . . U U . . . 4 4 . unemulated
565 cpscc 32 . . 1111...001...... .......... . . U U . . . 4 4 . unemulated
566 cptrapcc 32 . . 1111...001111... .......... . . U U . . . 4 4 . unemulated
567 ftrapcc 32 . . 1111001001111... .......... . . U U . . . 4 4 .
568 dbt 16 . . 0101000011001... .......... U U U U U 12 12 6 6 6
569 dbf 16 . . 0101000111001... .......... U U U U U 12 12 6 6 6
570 dbcc 16 . . 0101....11001... .......... U U U U U 12 12 6 6 6
571 divs 16 . d 1000...111000... .......... U U U U U 158 122 56 56 56
572 divs 16 . . 1000...111...... A+-DXWLdxI U U U U U 158 122 56 56 56
573 divu 16 . d 1000...011000... .......... U U U U U 140 108 44 44 44
574 divu 16 . . 1000...011...... A+-DXWLdxI U U U U U 140 108 44 44 44
575 divl 32 . d 0100110001000... .......... . . U U U . . 84 84 84
576 divl 32 . . 0100110001...... A+-DXWLdxI . . U U U . . 84 84 84
577 eor 8 . d 1011...100000... .......... U U U U U 4 4 2 2 2
578 eor 8 . . 1011...100...... A+-DXWL... U U U U U 8 8 4 4 4
579 eor 16 . d 1011...101000... .......... U U U U U 4 4 2 2 2
580 eor 16 . . 1011...101...... A+-DXWL... U U U U U 8 8 4 4 4
581 eor 32 . d 1011...110000... .......... U U U U U 8 6 2 2 2
582 eor 32 . . 1011...110...... A+-DXWL... U U U U U 12 12 4 4 4
583 eori 16 toc . 0000101000111100 .......... U U U U U 20 16 12 12 12
584 eori 16 tos . 0000101001111100 .......... S S S S S 20 16 12 12 12
585 eori 8 . d 0000101000000... .......... U U U U U 8 8 2 2 2
586 eori 8 . . 0000101000...... A+-DXWL... U U U U U 12 12 4 4 4
587 eori 16 . d 0000101001000... .......... U U U U U 8 8 2 2 2
588 eori 16 . . 0000101001...... A+-DXWL... U U U U U 12 12 4 4 4
589 eori 32 . d 0000101010000... .......... U U U U U 16 14 2 2 2
590 eori 32 . . 0000101010...... A+-DXWL... U U U U U 20 20 4 4 4
591 exg 32 dd . 1100...101000... .......... U U U U U 6 6 2 2 2
592 exg 32 aa . 1100...101001... .......... U U U U U 6 6 2 2 2
593 exg 32 da . 1100...110001... .......... U U U U U 6 6 2 2 2
594 ext 16 . . 0100100010000... .......... U U U U U 4 4 4 4 4
595 ext 32 . . 0100100011000... .......... U U U U U 4 4 4 4 4
596 extb 32 . . 0100100111000... .......... . . U U U . . 4 4 4
597 illegal 0 . . 0100101011111100 .......... U U U U U 4 4 4 4 4
598 jmp 32 . . 0100111011...... A..DXWLdx. U U U U U 4 4 0 0 0
599 jsr 32 . . 0100111010...... A..DXWLdx. U U U U U 12 12 0 0 0
600 lea 32 . . 0100...111...... A..DXWLdx. U U U U U 0 0 2 2 2
601 link 16 . a7 0100111001010111 .......... U U U U U 16 16 5 5 5
602 link 16 . . 0100111001010... .......... U U U U U 16 16 5 5 5
603 link 32 . a7 0100100000001111 .......... . . U U U . . 6 6 6
604 link 32 . . 0100100000001... .......... . . U U U . . 6 6 6
605 lsr 8 s . 1110...000001... .......... U U U U U 6 6 4 4 4
606 lsr 16 s . 1110...001001... .......... U U U U U 6 6 4 4 4
607 lsr 32 s . 1110...010001... .......... U U U U U 8 8 4 4 4
608 lsr 8 r . 1110...000101... .......... U U U U U 6 6 6 6 6
609 lsr 16 r . 1110...001101... .......... U U U U U 6 6 6 6 6
610 lsr 32 r . 1110...010101... .......... U U U U U 8 8 6 6 6
611 lsr 16 . . 1110001011...... A+-DXWL... U U U U U 8 8 5 5 5
612 lsl 8 s . 1110...100001... .......... U U U U U 6 6 4 4 4
613 lsl 16 s . 1110...101001... .......... U U U U U 6 6 4 4 4
614 lsl 32 s . 1110...110001... .......... U U U U U 8 8 4 4 4
615 lsl 8 r . 1110...100101... .......... U U U U U 6 6 6 6 6
616 lsl 16 r . 1110...101101... .......... U U U U U 6 6 6 6 6
617 lsl 32 r . 1110...110101... .......... U U U U U 8 8 6 6 6
618 lsl 16 . . 1110001111...... A+-DXWL... U U U U U 8 8 5 5 5
619 move 8 d d 0001...000000... .......... U U U U U 4 4 2 2 2
620 move 8 d . 0001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
621 move 8 ai d 0001...010000... .......... U U U U U 8 8 4 4 4
622 move 8 ai . 0001...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
623 move 8 pi d 0001...011000... .......... U U U U U 8 8 4 4 4
624 move 8 pi . 0001...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
625 move 8 pi7 d 0001111011000... .......... U U U U U 8 8 4 4 4
626 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U 8 8 4 4 4
627 move 8 pd d 0001...100000... .......... U U U U U 8 8 5 5 5
628 move 8 pd . 0001...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
629 move 8 pd7 d 0001111100000... .......... U U U U U 8 8 5 5 5
630 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U 8 8 5 5 5
631 move 8 di d 0001...101000... .......... U U U U U 12 12 5 5 5
632 move 8 di . 0001...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
633 move 8 ix d 0001...110000... .......... U U U U U 14 14 7 7 7
634 move 8 ix . 0001...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
635 move 8 aw d 0001000111000... .......... U U U U U 12 12 4 4 4
636 move 8 aw . 0001000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
637 move 8 al d 0001001111000... .......... U U U U U 16 16 6 6 6
638 move 8 al . 0001001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
639 move 16 d d 0011...000000... .......... U U U U U 4 4 2 2 2
640 move 16 d a 0011...000001... .......... U U U U U 4 4 2 2 2
641 move 16 d . 0011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
642 move 16 ai d 0011...010000... .......... U U U U U 8 8 4 4 4
643 move 16 ai a 0011...010001... .......... U U U U U 8 8 4 4 4
644 move 16 ai . 0011...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
645 move 16 pi d 0011...011000... .......... U U U U U 8 8 4 4 4
646 move 16 pi a 0011...011001... .......... U U U U U 8 8 4 4 4
647 move 16 pi . 0011...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
648 move 16 pd d 0011...100000... .......... U U U U U 8 8 5 5 5
649 move 16 pd a 0011...100001... .......... U U U U U 8 8 5 5 5
650 move 16 pd . 0011...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
651 move 16 di d 0011...101000... .......... U U U U U 12 12 5 5 5
652 move 16 di a 0011...101001... .......... U U U U U 12 12 5 5 5
653 move 16 di . 0011...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
654 move 16 ix d 0011...110000... .......... U U U U U 14 14 7 7 7
655 move 16 ix a 0011...110001... .......... U U U U U 14 14 7 7 7
656 move 16 ix . 0011...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
657 move 16 aw d 0011000111000... .......... U U U U U 12 12 4 4 4
658 move 16 aw a 0011000111001... .......... U U U U U 12 12 4 4 4
659 move 16 aw . 0011000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
660 move 16 al d 0011001111000... .......... U U U U U 16 16 6 6 6
661 move 16 al a 0011001111001... .......... U U U U U 16 16 6 6 6
662 move 16 al . 0011001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
663 move 32 d d 0010...000000... .......... U U U U U 4 4 2 2 2
664 move 32 d a 0010...000001... .......... U U U U U 4 4 2 2 2
665 move 32 d . 0010...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
666 move 32 ai d 0010...010000... .......... U U U U U 12 12 4 4 4
667 move 32 ai a 0010...010001... .......... U U U U U 12 12 4 4 4
668 move 32 ai . 0010...010...... A+-DXWLdxI U U U U U 12 12 4 4 4
669 move 32 pi d 0010...011000... .......... U U U U U 12 12 4 4 4
670 move 32 pi a 0010...011001... .......... U U U U U 12 12 4 4 4
671 move 32 pi . 0010...011...... A+-DXWLdxI U U U U U 12 12 4 4 4
672 move 32 pd d 0010...100000... .......... U U U U U 12 14 5 5 5
673 move 32 pd a 0010...100001... .......... U U U U U 12 14 5 5 5
674 move 32 pd . 0010...100...... A+-DXWLdxI U U U U U 12 14 5 5 5
675 move 32 di d 0010...101000... .......... U U U U U 16 16 5 5 5
676 move 32 di a 0010...101001... .......... U U U U U 16 16 5 5 5
677 move 32 di . 0010...101...... A+-DXWLdxI U U U U U 16 16 5 5 5
678 move 32 ix d 0010...110000... .......... U U U U U 18 18 7 7 7
679 move 32 ix a 0010...110001... .......... U U U U U 18 18 7 7 7
680 move 32 ix . 0010...110...... A+-DXWLdxI U U U U U 18 18 7 7 7
681 move 32 aw d 0010000111000... .......... U U U U U 16 16 4 4 4
682 move 32 aw a 0010000111001... .......... U U U U U 16 16 4 4 4
683 move 32 aw . 0010000111...... A+-DXWLdxI U U U U U 16 16 4 4 4
684 move 32 al d 0010001111000... .......... U U U U U 20 20 6 6 6
685 move 32 al a 0010001111001... .......... U U U U U 20 20 6 6 6
686 move 32 al . 0010001111...... A+-DXWLdxI U U U U U 20 20 6 6 6
687 movea 16 . d 0011...001000... .......... U U U U U 4 4 2 2 2
688 movea 16 . a 0011...001001... .......... U U U U U 4 4 2 2 2
689 movea 16 . . 0011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
690 movea 32 . d 0010...001000... .......... U U U U U 4 4 2 2 2
691 movea 32 . a 0010...001001... .......... U U U U U 4 4 2 2 2
692 movea 32 . . 0010...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
693 move 16 frc d 0100001011000... .......... . U U U U . 4 4 4 4
694 move 16 frc . 0100001011...... A+-DXWL... . U U U U . 8 4 4 4
695 move 16 toc d 0100010011000... .......... U U U U U 12 12 4 4 4
696 move 16 toc . 0100010011...... A+-DXWLdxI U U U U U 12 12 4 4 4
697 move 16 frs d 0100000011000... .......... U S S S S 6 4 8 8 8 U only for 000
698 move 16 frs . 0100000011...... A+-DXWL... U S S S S 8 8 8 8 8 U only for 000
699 move 16 tos d 0100011011000... .......... S S S S S 12 12 8 8 8
700 move 16 tos . 0100011011...... A+-DXWLdxI S S S S S 12 12 8 8 8
701 move 32 fru . 0100111001101... .......... S S S S S 4 6 2 2 2
702 move 32 tou . 0100111001100... .......... S S S S S 4 6 2 2 2
703 movec 32 cr . 0100111001111010 .......... . S S S S . 12 6 6 6
704 movec 32 rc . 0100111001111011 .......... . S S S S . 10 12 12 12
705 movem 16 re pd 0100100010100... .......... U U U U U 8 8 4 4 4
706 movem 16 re . 0100100010...... A..DXWL... U U U U U 8 8 4 4 4
707 movem 32 re pd 0100100011100... .......... U U U U U 8 8 4 4 4
708 movem 32 re . 0100100011...... A..DXWL... U U U U U 8 8 4 4 4
709 movem 16 er pi 0100110010011... .......... U U U U U 12 12 8 8 8
710 movem 16 er pcdi 0100110010111010 .......... U U U U U 16 16 9 9 9
711 movem 16 er pcix 0100110010111011 .......... U U U U U 18 18 11 11 11
712 movem 16 er . 0100110010...... A..DXWL... U U U U U 12 12 8 8 8
713 movem 32 er pi 0100110011011... .......... U U U U U 12 12 8 8 8
714 movem 32 er pcdi 0100110011111010 .......... U U U U U 16 16 9 9 9
715 movem 32 er pcix 0100110011111011 .......... U U U U U 18 18 11 11 11
716 movem 32 er . 0100110011...... A..DXWL... U U U U U 12 12 8 8 8
717 movep 16 er . 0000...100001... .......... U U U U U 16 16 12 12 12
718 movep 32 er . 0000...101001... .......... U U U U U 24 24 18 18 18
719 movep 16 re . 0000...110001... .......... U U U U U 16 16 11 11 11
720 movep 32 re . 0000...111001... .......... U U U U U 24 24 17 17 17
721 moveq 32 . . 0111...0........ .......... U U U U U 4 4 2 2 2
722 moves 8 . . 0000111000...... A+-DXWL... . S S S S . 14 5 5 5
723 moves 16 . . 0000111001...... A+-DXWL... . S S S S . 14 5 5 5
724 moves 32 . . 0000111010...... A+-DXWL... . S S S S . 16 5 5 5
725 move16 32 . . 1111011000100... .......... . . . . U . . . . 4 TODO: correct timing
726 muls 16 . d 1100...111000... .......... U U U U U 54 32 27 27 27
727 muls 16 . . 1100...111...... A+-DXWLdxI U U U U U 54 32 27 27 27
728 mulu 16 . d 1100...011000... .......... U U U U U 54 30 27 27 27
729 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U 54 30 27 27 27
730 mull 32 . d 0100110000000... .......... . . U U U . . 43 43 43
731 mull 32 . . 0100110000...... A+-DXWLdxI . . U U U . . 43 43 43
732 nbcd 8 . d 0100100000000... .......... U U U U U 6 6 6 6 6
733 nbcd 8 . . 0100100000...... A+-DXWL... U U U U U 8 8 6 6 6
734 neg 8 . d 0100010000000... .......... U U U U U 4 4 2 2 2
735 neg 8 . . 0100010000...... A+-DXWL... U U U U U 8 8 4 4 4
736 neg 16 . d 0100010001000... .......... U U U U U 4 4 2 2 2
737 neg 16 . . 0100010001...... A+-DXWL... U U U U U 8 8 4 4 4
738 neg 32 . d 0100010010000... .......... U U U U U 6 6 2 2 2
739 neg 32 . . 0100010010...... A+-DXWL... U U U U U 12 12 4 4 4
740 negx 8 . d 0100000000000... .......... U U U U U 4 4 2 2 2
741 negx 8 . . 0100000000...... A+-DXWL... U U U U U 8 8 4 4 4
742 negx 16 . d 0100000001000... .......... U U U U U 4 4 2 2 2
743 negx 16 . . 0100000001...... A+-DXWL... U U U U U 8 8 4 4 4
744 negx 32 . d 0100000010000... .......... U U U U U 6 6 2 2 2
745 negx 32 . . 0100000010...... A+-DXWL... U U U U U 12 12 4 4 4
746 nop 0 . . 0100111001110001 .......... U U U U U 4 4 2 2 2
747 not 8 . d 0100011000000... .......... U U U U U 4 4 2 2 2
748 not 8 . . 0100011000...... A+-DXWL... U U U U U 8 8 4 4 4
749 not 16 . d 0100011001000... .......... U U U U U 4 4 2 2 2
750 not 16 . . 0100011001...... A+-DXWL... U U U U U 8 8 4 4 4
751 not 32 . d 0100011010000... .......... U U U U U 6 6 2 2 2
752 not 32 . . 0100011010...... A+-DXWL... U U U U U 12 12 4 4 4
753 or 8 er d 1000...000000... .......... U U U U U 4 4 2 2 2
754 or 8 er . 1000...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
755 or 16 er d 1000...001000... .......... U U U U U 4 4 2 2 2
756 or 16 er . 1000...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
757 or 32 er d 1000...010000... .......... U U U U U 6 6 2 2 2
758 or 32 er . 1000...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
759 or 8 re . 1000...100...... A+-DXWL... U U U U U 8 8 4 4 4
760 or 16 re . 1000...101...... A+-DXWL... U U U U U 8 8 4 4 4
761 or 32 re . 1000...110...... A+-DXWL... U U U U U 12 12 4 4 4
762 ori 16 toc . 0000000000111100 .......... U U U U U 20 16 12 12 12
763 ori 16 tos . 0000000001111100 .......... S S S S S 20 16 12 12 12
764 ori 8 . d 0000000000000... .......... U U U U U 8 8 2 2 2
765 ori 8 . . 0000000000...... A+-DXWL... U U U U U 12 12 4 4 4
766 ori 16 . d 0000000001000... .......... U U U U U 8 8 2 2 2
767 ori 16 . . 0000000001...... A+-DXWL... U U U U U 12 12 4 4 4
768 ori 32 . d 0000000010000... .......... U U U U U 16 14 2 2 2
769 ori 32 . . 0000000010...... A+-DXWL... U U U U U 20 20 4 4 4
770 pack 16 rr . 1000...101000... .......... . . U U U . . 6 6 6
771 pack 16 mm ax7 1000111101001... .......... . . U U U . . 13 13 13
772 pack 16 mm ay7 1000...101001111 .......... . . U U U . . 13 13 13
773 pack 16 mm axy7 1000111101001111 .......... . . U U U . . 13 13 13
774 pack 16 mm . 1000...101001... .......... . . U U U . . 13 13 13
775 pea 32 . . 0100100001...... A..DXWLdx. U U U U U 6 6 5 5 5
776 pflusha 32 . . 1111010100011... .......... . . . . S . . . . 4 TODO: correct timing
777 pflushan 32 . . 1111010100010... .......... . . . . S . . . . 4 TODO: correct timing
778 pmmu 32 . . 1111000......... .......... . . S S S . . 8 8 8
779 reset 0 . . 0100111001110000 .......... S S S S S 0 0 0 0 0
780 ror 8 s . 1110...000011... .......... U U U U U 6 6 8 8 8
781 ror 16 s . 1110...001011... .......... U U U U U 6 6 8 8 8
782 ror 32 s . 1110...010011... .......... U U U U U 8 8 8 8 8
783 ror 8 r . 1110...000111... .......... U U U U U 6 6 8 8 8
784 ror 16 r . 1110...001111... .......... U U U U U 6 6 8 8 8
785 ror 32 r . 1110...010111... .......... U U U U U 8 8 8 8 8
786 ror 16 . . 1110011011...... A+-DXWL... U U U U U 8 8 7 7 7
787 rol 8 s . 1110...100011... .......... U U U U U 6 6 8 8 8
788 rol 16 s . 1110...101011... .......... U U U U U 6 6 8 8 8
789 rol 32 s . 1110...110011... .......... U U U U U 8 8 8 8 8
790 rol 8 r . 1110...100111... .......... U U U U U 6 6 8 8 8
791 rol 16 r . 1110...101111... .......... U U U U U 6 6 8 8 8
792 rol 32 r . 1110...110111... .......... U U U U U 8 8 8 8 8
793 rol 16 . . 1110011111...... A+-DXWL... U U U U U 8 8 7 7 7
794 roxr 8 s . 1110...000010... .......... U U U U U 6 6 12 12 12
795 roxr 16 s . 1110...001010... .......... U U U U U 6 6 12 12 12
796 roxr 32 s . 1110...010010... .......... U U U U U 8 8 12 12 12
797 roxr 8 r . 1110...000110... .......... U U U U U 6 6 12 12 12
798 roxr 16 r . 1110...001110... .......... U U U U U 6 6 12 12 12
799 roxr 32 r . 1110...010110... .......... U U U U U 8 8 12 12 12
800 roxr 16 . . 1110010011...... A+-DXWL... U U U U U 8 8 5 5 5
801 roxl 8 s . 1110...100010... .......... U U U U U 6 6 12 12 12
802 roxl 16 s . 1110...101010... .......... U U U U U 6 6 12 12 12
803 roxl 32 s . 1110...110010... .......... U U U U U 8 8 12 12 12
804 roxl 8 r . 1110...100110... .......... U U U U U 6 6 12 12 12
805 roxl 16 r . 1110...101110... .......... U U U U U 6 6 12 12 12
806 roxl 32 r . 1110...110110... .......... U U U U U 8 8 12 12 12
807 roxl 16 . . 1110010111...... A+-DXWL... U U U U U 8 8 5 5 5
808 rtd 32 . . 0100111001110100 .......... . U U U U . 16 10 10 10
809 rte 32 . . 0100111001110011 .......... S S S S S 20 24 20 20 20 bus fault not emulated
810 rtm 32 . . 000001101100.... .......... . . U U U . . 19 19 19 not properly emulated
811 rtr 32 . . 0100111001110111 .......... U U U U U 20 20 14 14 14
812 rts 32 . . 0100111001110101 .......... U U U U U 16 16 10 10 10
813 sbcd 8 rr . 1000...100000... .......... U U U U U 6 6 4 4 4
814 sbcd 8 mm ax7 1000111100001... .......... U U U U U 18 18 16 16 16
815 sbcd 8 mm ay7 1000...100001111 .......... U U U U U 18 18 16 16 16
816 sbcd 8 mm axy7 1000111100001111 .......... U U U U U 18 18 16 16 16
817 sbcd 8 mm . 1000...100001... .......... U U U U U 18 18 16 16 16
818 st 8 . d 0101000011000... .......... U U U U U 6 4 4 4 4
819 st 8 . . 0101000011...... A+-DXWL... U U U U U 8 8 6 6 6
820 sf 8 . d 0101000111000... .......... U U U U U 4 4 4 4 4
821 sf 8 . . 0101000111...... A+-DXWL... U U U U U 8 8 6 6 6
822 scc 8 . d 0101....11000... .......... U U U U U 4 4 4 4 4
823 scc 8 . . 0101....11...... A+-DXWL... U U U U U 8 8 6 6 6
824 stop 0 . . 0100111001110010 .......... S S S S S 4 4 8 8 8
825 sub 8 er d 1001...000000... .......... U U U U U 4 4 2 2 2
826 sub 8 er . 1001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
827 sub 16 er d 1001...001000... .......... U U U U U 4 4 2 2 2
828 sub 16 er a 1001...001001... .......... U U U U U 4 4 2 2 2
829 sub 16 er . 1001...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
830 sub 32 er d 1001...010000... .......... U U U U U 6 6 2 2 2
831 sub 32 er a 1001...010001... .......... U U U U U 6 6 2 2 2
832 sub 32 er . 1001...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
833 sub 8 re . 1001...100...... A+-DXWL... U U U U U 8 8 4 4 4
834 sub 16 re . 1001...101...... A+-DXWL... U U U U U 8 8 4 4 4
835 sub 32 re . 1001...110...... A+-DXWL... U U U U U 12 12 4 4 4
836 suba 16 . d 1001...011000... .......... U U U U U 8 8 2 2 2
837 suba 16 . a 1001...011001... .......... U U U U U 8 8 2 2 2
838 suba 16 . . 1001...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
839 suba 32 . d 1001...111000... .......... U U U U U 6 6 2 2 2
840 suba 32 . a 1001...111001... .......... U U U U U 6 6 2 2 2
841 suba 32 . . 1001...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
842 subi 8 . d 0000010000000... .......... U U U U U 8 8 2 2 2
843 subi 8 . . 0000010000...... A+-DXWL... U U U U U 12 12 4 4 4
844 subi 16 . d 0000010001000... .......... U U U U U 8 8 2 2 2
845 subi 16 . . 0000010001...... A+-DXWL... U U U U U 12 12 4 4 4
846 subi 32 . d 0000010010000... .......... U U U U U 16 14 2 2 2
847 subi 32 . . 0000010010...... A+-DXWL... U U U U U 20 20 4 4 4
848 subq 8 . d 0101...100000... .......... U U U U U 4 4 2 2 2
849 subq 8 . . 0101...100...... A+-DXWL... U U U U U 8 8 4 4 4
850 subq 16 . d 0101...101000... .......... U U U U U 4 4 2 2 2
851 subq 16 . a 0101...101001... .......... U U U U U 8 4 2 2 2
852 subq 16 . . 0101...101...... A+-DXWL... U U U U U 8 8 4 4 4
853 subq 32 . d 0101...110000... .......... U U U U U 8 8 2 2 2
854 subq 32 . a 0101...110001... .......... U U U U U 8 8 2 2 2
855 subq 32 . . 0101...110...... A+-DXWL... U U U U U 12 12 4 4 4
856 subx 8 rr . 1001...100000... .......... U U U U U 4 4 2 2 2
857 subx 16 rr . 1001...101000... .......... U U U U U 4 4 2 2 2
858 subx 32 rr . 1001...110000... .......... U U U U U 8 6 2 2 2
859 subx 8 mm ax7 1001111100001... .......... U U U U U 18 18 12 12 12
860 subx 8 mm ay7 1001...100001111 .......... U U U U U 18 18 12 12 12
861 subx 8 mm axy7 1001111100001111 .......... U U U U U 18 18 12 12 12
862 subx 8 mm . 1001...100001... .......... U U U U U 18 18 12 12 12
863 subx 16 mm . 1001...101001... .......... U U U U U 18 18 12 12 12
864 subx 32 mm . 1001...110001... .......... U U U U U 30 30 12 12 12
865 swap 32 . . 0100100001000... .......... U U U U U 4 4 4 4 4
866 tas 8 . d 0100101011000... .......... U U U U U 4 4 4 4 4
867 tas 8 . . 0100101011...... A+-DXWL... U U U U U 14 14 12 12 12
868 trap 0 . . 010011100100.... .......... U U U U U 4 4 4 4 4
869 trapt 0 . . 0101000011111100 .......... . . U U U . . 4 4 4
870 trapt 16 . . 0101000011111010 .......... . . U U U . . 6 6 6
871 trapt 32 . . 0101000011111011 .......... . . U U U . . 8 8 8
872 trapf 0 . . 0101000111111100 .......... . . U U U . . 4 4 4
873 trapf 16 . . 0101000111111010 .......... . . U U U . . 6 6 6
874 trapf 32 . . 0101000111111011 .......... . . U U U . . 8 8 8
875 trapcc 0 . . 0101....11111100 .......... . . U U U . . 4 4 4
876 trapcc 16 . . 0101....11111010 .......... . . U U U . . 6 6 6
877 trapcc 32 . . 0101....11111011 .......... . . U U U . . 8 8 8
878 trapv 0 . . 0100111001110110 .......... U U U U U 4 4 4 4 4
879 tst 8 . d 0100101000000... .......... U U U U U 4 4 2 2 2
880 tst 8 . . 0100101000...... A+-DXWL... U U U U U 4 4 2 2 2
881 tst 8 . pcdi 0100101000111010 .......... . . U U U . . 7 7 7
882 tst 8 . pcix 0100101000111011 .......... . . U U U . . 9 9 9
883 tst 8 . i 0100101000111100 .......... . . U U U . . 6 6 6
884 tst 16 . d 0100101001000... .......... U U U U U 4 4 2 2 2
885 tst 16 . a 0100101001001... .......... . . U U U . . 2 2 2
886 tst 16 . . 0100101001...... A+-DXWL... U U U U U 4 4 2 2 2
887 tst 16 . pcdi 0100101001111010 .......... . . U U U . . 7 7 7
888 tst 16 . pcix 0100101001111011 .......... . . U U U . . 9 9 9
889 tst 16 . i 0100101001111100 .......... . . U U U . . 6 6 6
890 tst 32 . d 0100101010000... .......... U U U U U 4 4 2 2 2
891 tst 32 . a 0100101010001... .......... . . U U U . . 2 2 2
892 tst 32 . . 0100101010...... A+-DXWL... U U U U U 4 4 2 2 2
893 tst 32 . pcdi 0100101010111010 .......... . . U U U . . 7 7 7
894 tst 32 . pcix 0100101010111011 .......... . . U U U . . 9 9 9
895 tst 32 . i 0100101010111100 .......... . . U U U . . 6 6 6
896 unlk 32 . a7 0100111001011111 .......... U U U U U 12 12 6 6 6
897 unlk 32 . . 0100111001011... .......... U U U U U 12 12 6 6 6
898 unpk 16 rr . 1000...110000... .......... . . U U U . . 8 8 8
899 unpk 16 mm ax7 1000111110001... .......... . . U U U . . 13 13 13
900 unpk 16 mm ay7 1000...110001111 .......... . . U U U . . 13 13 13
901 unpk 16 mm axy7 1000111110001111 .......... . . U U U . . 13 13 13
902 unpk 16 mm . 1000...110001... .......... . . U U U . . 13 13 13
906 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
907 M68KMAKE_OPCODE_HANDLER_BODY
909 M68KMAKE_OP(1010, 0, ., .)
911 m68ki_exception_1010(state);
915 M68KMAKE_OP(1111, 0, ., .)
917 m68ki_exception_1111(state);
921 M68KMAKE_OP(040fpu0, 32, ., .)
923 // printf("FPU 040fpu0 HAS_FPU=%d\n",!!HAS_FPU);
926 m68040_fpu_op0(state);
929 m68ki_exception_1111(state);
933 M68KMAKE_OP(040fpu1, 32, ., .)
935 // printf("FPU 040fpu1 HAS_FPU=%d\n",!!HAS_FPU);
938 m68040_fpu_op1(state);
941 m68ki_exception_1111(state);
946 M68KMAKE_OP(abcd, 8, rr, .)
951 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
956 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
957 FLAG_V = ~res; /* Undefined V behavior */
959 FLAG_X = FLAG_C = (res > 0x9f) << 8;
963 FLAG_V &= res; /* Undefined V behavior part II */
964 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
966 res = MASK_OUT_ABOVE_8(res);
969 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
973 M68KMAKE_OP(abcd, 8, mm, ax7)
975 uint src = OPER_AY_PD_8(state);
976 uint ea = EA_A7_PD_8();
977 uint dst = m68ki_read_8(state, ea);
978 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
983 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
984 FLAG_V = ~res; /* Undefined V behavior */
986 FLAG_X = FLAG_C = (res > 0x9f) << 8;
990 FLAG_V &= res; /* Undefined V behavior part II */
991 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
993 res = MASK_OUT_ABOVE_8(res);
996 m68ki_write_8(state, ea, res);
1000 M68KMAKE_OP(abcd, 8, mm, ay7)
1002 uint src = OPER_A7_PD_8(state);
1003 uint ea = EA_AX_PD_8();
1004 uint dst = m68ki_read_8(state, ea);
1005 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1010 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1011 FLAG_V = ~res; /* Undefined V behavior */
1013 FLAG_X = FLAG_C = (res > 0x9f) << 8;
1017 FLAG_V &= res; /* Undefined V behavior part II */
1018 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1020 res = MASK_OUT_ABOVE_8(res);
1023 m68ki_write_8(state, ea, res);
1027 M68KMAKE_OP(abcd, 8, mm, axy7)
1029 uint src = OPER_A7_PD_8(state);
1030 uint ea = EA_A7_PD_8();
1031 uint dst = m68ki_read_8(state, ea);
1032 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1037 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1038 FLAG_V = ~res; /* Undefined V behavior */
1040 FLAG_X = FLAG_C = (res > 0x9f) << 8;
1044 FLAG_V &= res; /* Undefined V behavior part II */
1045 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1047 res = MASK_OUT_ABOVE_8(res);
1050 m68ki_write_8(state, ea, res);
1054 M68KMAKE_OP(abcd, 8, mm, .)
1056 uint src = OPER_AY_PD_8(state);
1057 uint ea = EA_AX_PD_8();
1058 uint dst = m68ki_read_8(state, ea);
1059 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1064 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1065 FLAG_V = ~res; /* Undefined V behavior */
1067 FLAG_X = FLAG_C = (res > 0x9f) << 8;
1071 FLAG_V &= res; /* Undefined V behavior part II */
1072 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1074 res = MASK_OUT_ABOVE_8(res);
1077 m68ki_write_8(state, ea, res);
1081 M68KMAKE_OP(add, 8, er, d)
1084 uint src = MASK_OUT_ABOVE_8(DY);
1085 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1086 uint res = src + dst;
1088 FLAG_N = NFLAG_8(res);
1089 FLAG_V = VFLAG_ADD_8(src, dst, res);
1090 FLAG_X = FLAG_C = CFLAG_8(res);
1091 FLAG_Z = MASK_OUT_ABOVE_8(res);
1093 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1097 M68KMAKE_OP(add, 8, er, .)
1100 uint src = M68KMAKE_GET_OPER_AY_8;
1101 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1102 uint res = src + dst;
1104 FLAG_N = NFLAG_8(res);
1105 FLAG_V = VFLAG_ADD_8(src, dst, res);
1106 FLAG_X = FLAG_C = CFLAG_8(res);
1107 FLAG_Z = MASK_OUT_ABOVE_8(res);
1109 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1113 M68KMAKE_OP(add, 16, er, d)
1116 uint src = MASK_OUT_ABOVE_16(DY);
1117 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1118 uint res = src + dst;
1120 FLAG_N = NFLAG_16(res);
1121 FLAG_V = VFLAG_ADD_16(src, dst, res);
1122 FLAG_X = FLAG_C = CFLAG_16(res);
1123 FLAG_Z = MASK_OUT_ABOVE_16(res);
1125 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1129 M68KMAKE_OP(add, 16, er, a)
1132 uint src = MASK_OUT_ABOVE_16(AY);
1133 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1134 uint res = src + dst;
1136 FLAG_N = NFLAG_16(res);
1137 FLAG_V = VFLAG_ADD_16(src, dst, res);
1138 FLAG_X = FLAG_C = CFLAG_16(res);
1139 FLAG_Z = MASK_OUT_ABOVE_16(res);
1141 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1145 M68KMAKE_OP(add, 16, er, .)
1148 uint src = M68KMAKE_GET_OPER_AY_16;
1149 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1150 uint res = src + dst;
1152 FLAG_N = NFLAG_16(res);
1153 FLAG_V = VFLAG_ADD_16(src, dst, res);
1154 FLAG_X = FLAG_C = CFLAG_16(res);
1155 FLAG_Z = MASK_OUT_ABOVE_16(res);
1157 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1161 M68KMAKE_OP(add, 32, er, d)
1166 uint res = src + dst;
1168 FLAG_N = NFLAG_32(res);
1169 FLAG_V = VFLAG_ADD_32(src, dst, res);
1170 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1171 FLAG_Z = MASK_OUT_ABOVE_32(res);
1177 M68KMAKE_OP(add, 32, er, a)
1182 uint res = src + dst;
1184 FLAG_N = NFLAG_32(res);
1185 FLAG_V = VFLAG_ADD_32(src, dst, res);
1186 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1187 FLAG_Z = MASK_OUT_ABOVE_32(res);
1193 M68KMAKE_OP(add, 32, er, .)
1196 uint src = M68KMAKE_GET_OPER_AY_32;
1198 uint res = src + dst;
1200 FLAG_N = NFLAG_32(res);
1201 FLAG_V = VFLAG_ADD_32(src, dst, res);
1202 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1203 FLAG_Z = MASK_OUT_ABOVE_32(res);
1209 M68KMAKE_OP(add, 8, re, .)
1211 uint ea = M68KMAKE_GET_EA_AY_8;
1212 uint src = MASK_OUT_ABOVE_8(DX);
1213 uint dst = m68ki_read_8(state, ea);
1214 uint res = src + dst;
1216 FLAG_N = NFLAG_8(res);
1217 FLAG_V = VFLAG_ADD_8(src, dst, res);
1218 FLAG_X = FLAG_C = CFLAG_8(res);
1219 FLAG_Z = MASK_OUT_ABOVE_8(res);
1221 m68ki_write_8(state, ea, FLAG_Z);
1225 M68KMAKE_OP(add, 16, re, .)
1227 uint ea = M68KMAKE_GET_EA_AY_16;
1228 uint src = MASK_OUT_ABOVE_16(DX);
1229 uint dst = m68ki_read_16(state, ea);
1230 uint res = src + dst;
1232 FLAG_N = NFLAG_16(res);
1233 FLAG_V = VFLAG_ADD_16(src, dst, res);
1234 FLAG_X = FLAG_C = CFLAG_16(res);
1235 FLAG_Z = MASK_OUT_ABOVE_16(res);
1237 m68ki_write_16(state, ea, FLAG_Z);
1241 M68KMAKE_OP(add, 32, re, .)
1243 uint ea = M68KMAKE_GET_EA_AY_32;
1245 uint dst = m68ki_read_32(state, ea);
1246 uint res = src + dst;
1248 FLAG_N = NFLAG_32(res);
1249 FLAG_V = VFLAG_ADD_32(src, dst, res);
1250 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1251 FLAG_Z = MASK_OUT_ABOVE_32(res);
1253 m68ki_write_32(state, ea, FLAG_Z);
1257 M68KMAKE_OP(adda, 16, ., d)
1261 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
1265 M68KMAKE_OP(adda, 16, ., a)
1269 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
1273 M68KMAKE_OP(adda, 16, ., .)
1276 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
1278 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1282 M68KMAKE_OP(adda, 32, ., d)
1286 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
1290 M68KMAKE_OP(adda, 32, ., a)
1294 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
1298 M68KMAKE_OP(adda, 32, ., .)
1300 uint src = M68KMAKE_GET_OPER_AY_32;
1303 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1307 M68KMAKE_OP(addi, 8, ., d)
1310 uint src = OPER_I_8(state);
1311 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1312 uint res = src + dst;
1314 FLAG_N = NFLAG_8(res);
1315 FLAG_V = VFLAG_ADD_8(src, dst, res);
1316 FLAG_X = FLAG_C = CFLAG_8(res);
1317 FLAG_Z = MASK_OUT_ABOVE_8(res);
1319 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1323 M68KMAKE_OP(addi, 8, ., .)
1325 uint src = OPER_I_8(state);
1326 uint ea = M68KMAKE_GET_EA_AY_8;
1327 uint dst = m68ki_read_8(state, ea);
1328 uint res = src + dst;
1330 FLAG_N = NFLAG_8(res);
1331 FLAG_V = VFLAG_ADD_8(src, dst, res);
1332 FLAG_X = FLAG_C = CFLAG_8(res);
1333 FLAG_Z = MASK_OUT_ABOVE_8(res);
1335 m68ki_write_8(state, ea, FLAG_Z);
1339 M68KMAKE_OP(addi, 16, ., d)
1342 uint src = OPER_I_16(state);
1343 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1344 uint res = src + dst;
1346 FLAG_N = NFLAG_16(res);
1347 FLAG_V = VFLAG_ADD_16(src, dst, res);
1348 FLAG_X = FLAG_C = CFLAG_16(res);
1349 FLAG_Z = MASK_OUT_ABOVE_16(res);
1351 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1355 M68KMAKE_OP(addi, 16, ., .)
1357 uint src = OPER_I_16(state);
1358 uint ea = M68KMAKE_GET_EA_AY_16;
1359 uint dst = m68ki_read_16(state, ea);
1360 uint res = src + dst;
1362 FLAG_N = NFLAG_16(res);
1363 FLAG_V = VFLAG_ADD_16(src, dst, res);
1364 FLAG_X = FLAG_C = CFLAG_16(res);
1365 FLAG_Z = MASK_OUT_ABOVE_16(res);
1367 m68ki_write_16(state, ea, FLAG_Z);
1371 M68KMAKE_OP(addi, 32, ., d)
1374 uint src = OPER_I_32(state);
1376 uint res = src + dst;
1378 FLAG_N = NFLAG_32(res);
1379 FLAG_V = VFLAG_ADD_32(src, dst, res);
1380 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1381 FLAG_Z = MASK_OUT_ABOVE_32(res);
1387 M68KMAKE_OP(addi, 32, ., .)
1389 uint src = OPER_I_32(state);
1390 uint ea = M68KMAKE_GET_EA_AY_32;
1391 uint dst = m68ki_read_32(state, ea);
1392 uint res = src + dst;
1394 FLAG_N = NFLAG_32(res);
1395 FLAG_V = VFLAG_ADD_32(src, dst, res);
1396 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1397 FLAG_Z = MASK_OUT_ABOVE_32(res);
1399 m68ki_write_32(state, ea, FLAG_Z);
1403 M68KMAKE_OP(addq, 8, ., d)
1406 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1407 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1408 uint res = src + dst;
1410 FLAG_N = NFLAG_8(res);
1411 FLAG_V = VFLAG_ADD_8(src, dst, res);
1412 FLAG_X = FLAG_C = CFLAG_8(res);
1413 FLAG_Z = MASK_OUT_ABOVE_8(res);
1415 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1419 M68KMAKE_OP(addq, 8, ., .)
1421 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1422 uint ea = M68KMAKE_GET_EA_AY_8;
1423 uint dst = m68ki_read_8(state, ea);
1424 uint res = src + dst;
1426 FLAG_N = NFLAG_8(res);
1427 FLAG_V = VFLAG_ADD_8(src, dst, res);
1428 FLAG_X = FLAG_C = CFLAG_8(res);
1429 FLAG_Z = MASK_OUT_ABOVE_8(res);
1431 m68ki_write_8(state, ea, FLAG_Z);
1435 M68KMAKE_OP(addq, 16, ., d)
1438 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1439 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1440 uint res = src + dst;
1442 FLAG_N = NFLAG_16(res);
1443 FLAG_V = VFLAG_ADD_16(src, dst, res);
1444 FLAG_X = FLAG_C = CFLAG_16(res);
1445 FLAG_Z = MASK_OUT_ABOVE_16(res);
1447 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1451 M68KMAKE_OP(addq, 16, ., a)
1455 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1459 M68KMAKE_OP(addq, 16, ., .)
1461 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1462 uint ea = M68KMAKE_GET_EA_AY_16;
1463 uint dst = m68ki_read_16(state, ea);
1464 uint res = src + dst;
1466 FLAG_N = NFLAG_16(res);
1467 FLAG_V = VFLAG_ADD_16(src, dst, res);
1468 FLAG_X = FLAG_C = CFLAG_16(res);
1469 FLAG_Z = MASK_OUT_ABOVE_16(res);
1471 m68ki_write_16(state, ea, FLAG_Z);
1475 M68KMAKE_OP(addq, 32, ., d)
1478 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1480 uint res = src + dst;
1482 FLAG_N = NFLAG_32(res);
1483 FLAG_V = VFLAG_ADD_32(src, dst, res);
1484 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1485 FLAG_Z = MASK_OUT_ABOVE_32(res);
1491 M68KMAKE_OP(addq, 32, ., a)
1495 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1499 M68KMAKE_OP(addq, 32, ., .)
1501 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1502 uint ea = M68KMAKE_GET_EA_AY_32;
1503 uint dst = m68ki_read_32(state, ea);
1504 uint res = src + dst;
1507 FLAG_N = NFLAG_32(res);
1508 FLAG_V = VFLAG_ADD_32(src, dst, res);
1509 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1510 FLAG_Z = MASK_OUT_ABOVE_32(res);
1512 m68ki_write_32(state, ea, FLAG_Z);
1516 M68KMAKE_OP(addx, 8, rr, .)
1519 uint src = MASK_OUT_ABOVE_8(DY);
1520 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1521 uint res = src + dst + XFLAG_AS_1();
1523 FLAG_N = NFLAG_8(res);
1524 FLAG_V = VFLAG_ADD_8(src, dst, res);
1525 FLAG_X = FLAG_C = CFLAG_8(res);
1527 res = MASK_OUT_ABOVE_8(res);
1530 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1534 M68KMAKE_OP(addx, 16, rr, .)
1537 uint src = MASK_OUT_ABOVE_16(DY);
1538 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1539 uint res = src + dst + XFLAG_AS_1();
1541 FLAG_N = NFLAG_16(res);
1542 FLAG_V = VFLAG_ADD_16(src, dst, res);
1543 FLAG_X = FLAG_C = CFLAG_16(res);
1545 res = MASK_OUT_ABOVE_16(res);
1548 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1552 M68KMAKE_OP(addx, 32, rr, .)
1557 uint res = src + dst + XFLAG_AS_1();
1559 FLAG_N = NFLAG_32(res);
1560 FLAG_V = VFLAG_ADD_32(src, dst, res);
1561 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1563 res = MASK_OUT_ABOVE_32(res);
1570 M68KMAKE_OP(addx, 8, mm, ax7)
1572 uint src = OPER_AY_PD_8(state);
1573 uint ea = EA_A7_PD_8();
1574 uint dst = m68ki_read_8(state, ea);
1575 uint res = src + dst + XFLAG_AS_1();
1577 FLAG_N = NFLAG_8(res);
1578 FLAG_V = VFLAG_ADD_8(src, dst, res);
1579 FLAG_X = FLAG_C = CFLAG_8(res);
1581 res = MASK_OUT_ABOVE_8(res);
1584 m68ki_write_8(state, ea, res);
1588 M68KMAKE_OP(addx, 8, mm, ay7)
1590 uint src = OPER_A7_PD_8(state);
1591 uint ea = EA_AX_PD_8();
1592 uint dst = m68ki_read_8(state, ea);
1593 uint res = src + dst + XFLAG_AS_1();
1595 FLAG_N = NFLAG_8(res);
1596 FLAG_V = VFLAG_ADD_8(src, dst, res);
1597 FLAG_X = FLAG_C = CFLAG_8(res);
1599 res = MASK_OUT_ABOVE_8(res);
1602 m68ki_write_8(state, ea, res);
1606 M68KMAKE_OP(addx, 8, mm, axy7)
1608 uint src = OPER_A7_PD_8(state);
1609 uint ea = EA_A7_PD_8();
1610 uint dst = m68ki_read_8(state, ea);
1611 uint res = src + dst + XFLAG_AS_1();
1613 FLAG_N = NFLAG_8(res);
1614 FLAG_V = VFLAG_ADD_8(src, dst, res);
1615 FLAG_X = FLAG_C = CFLAG_8(res);
1617 res = MASK_OUT_ABOVE_8(res);
1620 m68ki_write_8(state, ea, res);
1624 M68KMAKE_OP(addx, 8, mm, .)
1626 uint src = OPER_AY_PD_8(state);
1627 uint ea = EA_AX_PD_8();
1628 uint dst = m68ki_read_8(state, ea);
1629 uint res = src + dst + XFLAG_AS_1();
1631 FLAG_N = NFLAG_8(res);
1632 FLAG_V = VFLAG_ADD_8(src, dst, res);
1633 FLAG_X = FLAG_C = CFLAG_8(res);
1635 res = MASK_OUT_ABOVE_8(res);
1638 m68ki_write_8(state, ea, res);
1642 M68KMAKE_OP(addx, 16, mm, .)
1644 uint src = OPER_AY_PD_16(state);
1645 uint ea = EA_AX_PD_16();
1646 uint dst = m68ki_read_16(state, ea);
1647 uint res = src + dst + XFLAG_AS_1();
1649 FLAG_N = NFLAG_16(res);
1650 FLAG_V = VFLAG_ADD_16(src, dst, res);
1651 FLAG_X = FLAG_C = CFLAG_16(res);
1653 res = MASK_OUT_ABOVE_16(res);
1656 m68ki_write_16(state, ea, res);
1660 M68KMAKE_OP(addx, 32, mm, .)
1662 uint src = OPER_AY_PD_32(state);
1663 uint ea = EA_AX_PD_32();
1664 uint dst = m68ki_read_32(state, ea);
1665 uint res = src + dst + XFLAG_AS_1();
1667 FLAG_N = NFLAG_32(res);
1668 FLAG_V = VFLAG_ADD_32(src, dst, res);
1669 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1671 res = MASK_OUT_ABOVE_32(res);
1674 m68ki_write_32(state, ea, res);
1678 M68KMAKE_OP(and, 8, er, d)
1680 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
1682 FLAG_N = NFLAG_8(FLAG_Z);
1683 FLAG_C = CFLAG_CLEAR;
1684 FLAG_V = VFLAG_CLEAR;
1688 M68KMAKE_OP(and, 8, er, .)
1690 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
1692 FLAG_N = NFLAG_8(FLAG_Z);
1693 FLAG_C = CFLAG_CLEAR;
1694 FLAG_V = VFLAG_CLEAR;
1698 M68KMAKE_OP(and, 16, er, d)
1700 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
1702 FLAG_N = NFLAG_16(FLAG_Z);
1703 FLAG_C = CFLAG_CLEAR;
1704 FLAG_V = VFLAG_CLEAR;
1708 M68KMAKE_OP(and, 16, er, .)
1710 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
1712 FLAG_N = NFLAG_16(FLAG_Z);
1713 FLAG_C = CFLAG_CLEAR;
1714 FLAG_V = VFLAG_CLEAR;
1718 M68KMAKE_OP(and, 32, er, d)
1722 FLAG_N = NFLAG_32(FLAG_Z);
1723 FLAG_C = CFLAG_CLEAR;
1724 FLAG_V = VFLAG_CLEAR;
1728 M68KMAKE_OP(and, 32, er, .)
1730 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
1732 FLAG_N = NFLAG_32(FLAG_Z);
1733 FLAG_C = CFLAG_CLEAR;
1734 FLAG_V = VFLAG_CLEAR;
1738 M68KMAKE_OP(and, 8, re, .)
1740 uint ea = M68KMAKE_GET_EA_AY_8;
1741 uint res = DX & m68ki_read_8(state, ea);
1743 FLAG_N = NFLAG_8(res);
1744 FLAG_C = CFLAG_CLEAR;
1745 FLAG_V = VFLAG_CLEAR;
1746 FLAG_Z = MASK_OUT_ABOVE_8(res);
1748 m68ki_write_8(state, ea, FLAG_Z);
1752 M68KMAKE_OP(and, 16, re, .)
1754 uint ea = M68KMAKE_GET_EA_AY_16;
1755 uint res = DX & m68ki_read_16(state, ea);
1757 FLAG_N = NFLAG_16(res);
1758 FLAG_C = CFLAG_CLEAR;
1759 FLAG_V = VFLAG_CLEAR;
1760 FLAG_Z = MASK_OUT_ABOVE_16(res);
1762 m68ki_write_16(state, ea, FLAG_Z);
1766 M68KMAKE_OP(and, 32, re, .)
1768 uint ea = M68KMAKE_GET_EA_AY_32;
1769 uint res = DX & m68ki_read_32(state, ea);
1771 FLAG_N = NFLAG_32(res);
1773 FLAG_C = CFLAG_CLEAR;
1774 FLAG_V = VFLAG_CLEAR;
1776 m68ki_write_32(state, ea, res);
1780 M68KMAKE_OP(andi, 8, ., d)
1782 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8(state) | 0xffffff00));
1784 FLAG_N = NFLAG_8(FLAG_Z);
1785 FLAG_C = CFLAG_CLEAR;
1786 FLAG_V = VFLAG_CLEAR;
1790 M68KMAKE_OP(andi, 8, ., .)
1792 uint src = OPER_I_8(state);
1793 uint ea = M68KMAKE_GET_EA_AY_8;
1794 uint res = src & m68ki_read_8(state, ea);
1796 FLAG_N = NFLAG_8(res);
1798 FLAG_C = CFLAG_CLEAR;
1799 FLAG_V = VFLAG_CLEAR;
1801 m68ki_write_8(state, ea, res);
1805 M68KMAKE_OP(andi, 16, ., d)
1807 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16(state) | 0xffff0000));
1809 FLAG_N = NFLAG_16(FLAG_Z);
1810 FLAG_C = CFLAG_CLEAR;
1811 FLAG_V = VFLAG_CLEAR;
1815 M68KMAKE_OP(andi, 16, ., .)
1817 uint src = OPER_I_16(state);
1818 uint ea = M68KMAKE_GET_EA_AY_16;
1819 uint res = src & m68ki_read_16(state, ea);
1821 FLAG_N = NFLAG_16(res);
1823 FLAG_C = CFLAG_CLEAR;
1824 FLAG_V = VFLAG_CLEAR;
1826 m68ki_write_16(state, ea, res);
1830 M68KMAKE_OP(andi, 32, ., d)
1832 FLAG_Z = DY &= (OPER_I_32(state));
1834 FLAG_N = NFLAG_32(FLAG_Z);
1835 FLAG_C = CFLAG_CLEAR;
1836 FLAG_V = VFLAG_CLEAR;
1840 M68KMAKE_OP(andi, 32, ., .)
1842 uint src = OPER_I_32(state);
1843 uint ea = M68KMAKE_GET_EA_AY_32;
1844 uint res = src & m68ki_read_32(state, ea);
1846 FLAG_N = NFLAG_32(res);
1848 FLAG_C = CFLAG_CLEAR;
1849 FLAG_V = VFLAG_CLEAR;
1851 m68ki_write_32(state, ea, res);
1855 M68KMAKE_OP(andi, 16, toc, .)
1857 m68ki_set_ccr(state, m68ki_get_ccr(state) & OPER_I_8(state));
1861 M68KMAKE_OP(andi, 16, tos, .)
1865 uint src = OPER_I_16(state);
1866 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
1867 m68ki_set_sr(state, m68ki_get_sr() & src);
1870 m68ki_exception_privilege_violation(state);
1874 M68KMAKE_OP(asr, 8, s, .)
1877 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1878 uint src = MASK_OUT_ABOVE_8(*r_dst);
1879 uint res = src >> shift;
1882 USE_CYCLES(shift<<CYC_SHIFT);
1885 res |= m68ki_shift_8_table[shift];
1887 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1889 FLAG_N = NFLAG_8(res);
1891 FLAG_V = VFLAG_CLEAR;
1892 FLAG_X = FLAG_C = src << (9-shift);
1896 M68KMAKE_OP(asr, 16, s, .)
1899 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1900 uint src = MASK_OUT_ABOVE_16(*r_dst);
1901 uint res = src >> shift;
1904 USE_CYCLES(shift<<CYC_SHIFT);
1907 res |= m68ki_shift_16_table[shift];
1909 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1911 FLAG_N = NFLAG_16(res);
1913 FLAG_V = VFLAG_CLEAR;
1914 FLAG_X = FLAG_C = src << (9-shift);
1918 M68KMAKE_OP(asr, 32, s, .)
1921 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1923 uint res = src >> shift;
1926 USE_CYCLES(shift<<CYC_SHIFT);
1929 res |= m68ki_shift_32_table[shift];
1933 FLAG_N = NFLAG_32(res);
1935 FLAG_V = VFLAG_CLEAR;
1936 FLAG_X = FLAG_C = src << (9-shift);
1940 M68KMAKE_OP(asr, 8, r, .)
1943 uint shift = DX & 0x3f;
1944 uint src = MASK_OUT_ABOVE_8(*r_dst);
1945 uint res = src >> shift;
1949 USE_CYCLES(shift<<CYC_SHIFT);
1954 res |= m68ki_shift_8_table[shift];
1956 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1958 FLAG_X = FLAG_C = src << (9-shift);
1959 FLAG_N = NFLAG_8(res);
1961 FLAG_V = VFLAG_CLEAR;
1971 FLAG_Z = ZFLAG_CLEAR;
1972 FLAG_V = VFLAG_CLEAR;
1976 *r_dst &= 0xffffff00;
1977 FLAG_C = CFLAG_CLEAR;
1978 FLAG_X = XFLAG_CLEAR;
1979 FLAG_N = NFLAG_CLEAR;
1981 FLAG_V = VFLAG_CLEAR;
1985 FLAG_C = CFLAG_CLEAR;
1986 FLAG_N = NFLAG_8(src);
1988 FLAG_V = VFLAG_CLEAR;
1992 M68KMAKE_OP(asr, 16, r, .)
1995 uint shift = DX & 0x3f;
1996 uint src = MASK_OUT_ABOVE_16(*r_dst);
1997 uint res = src >> shift;
2001 USE_CYCLES(shift<<CYC_SHIFT);
2006 res |= m68ki_shift_16_table[shift];
2008 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2010 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2011 FLAG_N = NFLAG_16(res);
2013 FLAG_V = VFLAG_CLEAR;
2023 FLAG_Z = ZFLAG_CLEAR;
2024 FLAG_V = VFLAG_CLEAR;
2028 *r_dst &= 0xffff0000;
2029 FLAG_C = CFLAG_CLEAR;
2030 FLAG_X = XFLAG_CLEAR;
2031 FLAG_N = NFLAG_CLEAR;
2033 FLAG_V = VFLAG_CLEAR;
2037 FLAG_C = CFLAG_CLEAR;
2038 FLAG_N = NFLAG_16(src);
2040 FLAG_V = VFLAG_CLEAR;
2044 M68KMAKE_OP(asr, 32, r, .)
2047 uint shift = DX & 0x3f;
2049 uint res = src >> shift;
2053 USE_CYCLES(shift<<CYC_SHIFT);
2058 res |= m68ki_shift_32_table[shift];
2062 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2063 FLAG_N = NFLAG_32(res);
2065 FLAG_V = VFLAG_CLEAR;
2071 *r_dst = 0xffffffff;
2075 FLAG_Z = ZFLAG_CLEAR;
2076 FLAG_V = VFLAG_CLEAR;
2081 FLAG_C = CFLAG_CLEAR;
2082 FLAG_X = XFLAG_CLEAR;
2083 FLAG_N = NFLAG_CLEAR;
2085 FLAG_V = VFLAG_CLEAR;
2089 FLAG_C = CFLAG_CLEAR;
2090 FLAG_N = NFLAG_32(src);
2092 FLAG_V = VFLAG_CLEAR;
2096 M68KMAKE_OP(asr, 16, ., .)
2098 uint ea = M68KMAKE_GET_EA_AY_16;
2099 uint src = m68ki_read_16(state, ea);
2100 uint res = src >> 1;
2105 m68ki_write_16(state, ea, res);
2107 FLAG_N = NFLAG_16(res);
2109 FLAG_V = VFLAG_CLEAR;
2110 FLAG_C = FLAG_X = src << 8;
2114 M68KMAKE_OP(asl, 8, s, .)
2117 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2118 uint src = MASK_OUT_ABOVE_8(*r_dst);
2119 uint res = MASK_OUT_ABOVE_8(src << shift);
2122 USE_CYCLES(shift<<CYC_SHIFT);
2124 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2126 FLAG_X = FLAG_C = src << shift;
2127 FLAG_N = NFLAG_8(res);
2129 src &= m68ki_shift_8_table[shift + 1];
2130 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
2134 M68KMAKE_OP(asl, 16, s, .)
2137 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2138 uint src = MASK_OUT_ABOVE_16(*r_dst);
2139 uint res = MASK_OUT_ABOVE_16(src << shift);
2142 USE_CYCLES(shift<<CYC_SHIFT);
2144 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2146 FLAG_N = NFLAG_16(res);
2148 FLAG_X = FLAG_C = src >> (8-shift);
2149 src &= m68ki_shift_16_table[shift + 1];
2150 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2154 M68KMAKE_OP(asl, 32, s, .)
2157 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2159 uint res = MASK_OUT_ABOVE_32(src << shift);
2162 USE_CYCLES(shift<<CYC_SHIFT);
2166 FLAG_N = NFLAG_32(res);
2168 FLAG_X = FLAG_C = src >> (24-shift);
2169 src &= m68ki_shift_32_table[shift + 1];
2170 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2174 M68KMAKE_OP(asl, 8, r, .)
2177 uint shift = DX & 0x3f;
2178 uint src = MASK_OUT_ABOVE_8(*r_dst);
2179 uint res = MASK_OUT_ABOVE_8(src << shift);
2183 USE_CYCLES(shift<<CYC_SHIFT);
2187 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2188 FLAG_X = FLAG_C = src << shift;
2189 FLAG_N = NFLAG_8(res);
2191 src &= m68ki_shift_8_table[shift + 1];
2192 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
2196 *r_dst &= 0xffffff00;
2197 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
2198 FLAG_N = NFLAG_CLEAR;
2200 FLAG_V = (!(src == 0))<<7;
2204 FLAG_C = CFLAG_CLEAR;
2205 FLAG_N = NFLAG_8(src);
2207 FLAG_V = VFLAG_CLEAR;
2211 M68KMAKE_OP(asl, 16, r, .)
2214 uint shift = DX & 0x3f;
2215 uint src = MASK_OUT_ABOVE_16(*r_dst);
2216 uint res = MASK_OUT_ABOVE_16(src << shift);
2220 USE_CYCLES(shift<<CYC_SHIFT);
2224 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2225 FLAG_X = FLAG_C = (src << shift) >> 8;
2226 FLAG_N = NFLAG_16(res);
2228 src &= m68ki_shift_16_table[shift + 1];
2229 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2233 *r_dst &= 0xffff0000;
2234 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
2235 FLAG_N = NFLAG_CLEAR;
2237 FLAG_V = (!(src == 0))<<7;
2241 FLAG_C = CFLAG_CLEAR;
2242 FLAG_N = NFLAG_16(src);
2244 FLAG_V = VFLAG_CLEAR;
2248 M68KMAKE_OP(asl, 32, r, .)
2251 uint shift = DX & 0x3f;
2253 uint res = MASK_OUT_ABOVE_32(src << shift);
2257 USE_CYCLES(shift<<CYC_SHIFT);
2262 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
2263 FLAG_N = NFLAG_32(res);
2265 src &= m68ki_shift_32_table[shift + 1];
2266 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2271 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
2272 FLAG_N = NFLAG_CLEAR;
2274 FLAG_V = (!(src == 0))<<7;
2278 FLAG_C = CFLAG_CLEAR;
2279 FLAG_N = NFLAG_32(src);
2281 FLAG_V = VFLAG_CLEAR;
2285 M68KMAKE_OP(asl, 16, ., .)
2287 uint ea = M68KMAKE_GET_EA_AY_16;
2288 uint src = m68ki_read_16(state, ea);
2289 uint res = MASK_OUT_ABOVE_16(src << 1);
2291 m68ki_write_16(state, ea, res);
2293 FLAG_N = NFLAG_16(res);
2295 FLAG_X = FLAG_C = src >> 7;
2297 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
2301 M68KMAKE_OP(bcc, 8, ., .)
2305 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2306 m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
2309 USE_CYCLES(CYC_BCC_NOTAKE_B);
2313 M68KMAKE_OP(bcc, 16, ., .)
2317 uint offset = OPER_I_16(state);
2319 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2320 m68ki_branch_16(state, offset);
2324 USE_CYCLES(CYC_BCC_NOTAKE_W);
2328 M68KMAKE_OP(bcc, 32, ., .)
2330 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2334 uint offset = OPER_I_32(state);
2336 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2337 m68ki_branch_32(state, offset);
2347 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2348 m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
2351 USE_CYCLES(CYC_BCC_NOTAKE_B);
2356 M68KMAKE_OP(bchg, 32, r, d)
2359 uint mask = 1 << (DX & 0x1f);
2361 FLAG_Z = *r_dst & mask;
2366 M68KMAKE_OP(bchg, 8, r, .)
2368 uint ea = M68KMAKE_GET_EA_AY_8;
2369 uint src = m68ki_read_8(state, ea);
2370 uint mask = 1 << (DX & 7);
2372 FLAG_Z = src & mask;
2373 m68ki_write_8(state, ea, src ^ mask);
2377 M68KMAKE_OP(bchg, 32, s, d)
2380 uint mask = 1 << (OPER_I_8(state) & 0x1f);
2382 FLAG_Z = *r_dst & mask;
2387 M68KMAKE_OP(bchg, 8, s, .)
2389 uint mask = 1 << (OPER_I_8(state) & 7);
2390 uint ea = M68KMAKE_GET_EA_AY_8;
2391 uint src = m68ki_read_8(state, ea);
2393 FLAG_Z = src & mask;
2394 m68ki_write_8(state, ea, src ^ mask);
2398 M68KMAKE_OP(bclr, 32, r, d)
2401 uint mask = 1 << (DX & 0x1f);
2403 FLAG_Z = *r_dst & mask;
2408 M68KMAKE_OP(bclr, 8, r, .)
2410 uint ea = M68KMAKE_GET_EA_AY_8;
2411 uint src = m68ki_read_8(state, ea);
2412 uint mask = 1 << (DX & 7);
2414 FLAG_Z = src & mask;
2415 m68ki_write_8(state, ea, src & ~mask);
2419 M68KMAKE_OP(bclr, 32, s, d)
2422 uint mask = 1 << (OPER_I_8(state) & 0x1f);
2424 FLAG_Z = *r_dst & mask;
2429 M68KMAKE_OP(bclr, 8, s, .)
2431 uint mask = 1 << (OPER_I_8(state) & 7);
2432 uint ea = M68KMAKE_GET_EA_AY_8;
2433 uint src = m68ki_read_8(state, ea);
2435 FLAG_Z = src & mask;
2436 m68ki_write_8(state, ea, src & ~mask);
2440 M68KMAKE_OP(bfchg, 32, ., d)
2442 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2444 uint word2 = OPER_I_16(state);
2445 uint offset = (word2>>6)&31;
2452 offset = REG_D[offset&7];
2454 width = REG_D[width&7];
2457 width = ((width-1) & 31) + 1;
2459 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2460 mask = ROR_32(mask, offset);
2462 FLAG_N = NFLAG_32(*data<<offset);
2463 FLAG_Z = *data & mask;
2464 FLAG_V = VFLAG_CLEAR;
2465 FLAG_C = CFLAG_CLEAR;
2471 m68ki_exception_illegal(state);
2475 M68KMAKE_OP(bfchg, 32, ., .)
2477 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2479 uint word2 = OPER_I_16(state);
2480 sint offset = (word2>>6)&31;
2487 uint ea = M68KMAKE_GET_EA_AY_8;
2491 offset = MAKE_INT_32(REG_D[offset&7]);
2493 width = REG_D[width&7];
2495 /* Offset is signed so we have to use ugly math =( */
2503 width = ((width-1) & 31) + 1;
2505 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2506 mask_long = mask_base >> offset;
2508 data_long = m68ki_read_32(state, ea);
2509 FLAG_N = NFLAG_32(data_long << offset);
2510 FLAG_Z = data_long & mask_long;
2511 FLAG_V = VFLAG_CLEAR;
2512 FLAG_C = CFLAG_CLEAR;
2514 m68ki_write_32(state, ea, data_long ^ mask_long);
2516 if((width + offset) > 32)
2518 mask_byte = MASK_OUT_ABOVE_8(mask_base) << (8-offset);
2519 data_byte = m68ki_read_8(state, ea+4);
2520 FLAG_Z |= (data_byte & mask_byte);
2521 m68ki_write_8(state, ea+4, data_byte ^ mask_byte);
2525 m68ki_exception_illegal(state);
2529 M68KMAKE_OP(bfclr, 32, ., d)
2531 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2533 uint word2 = OPER_I_16(state);
2534 uint offset = (word2>>6)&31;
2541 offset = REG_D[offset&7];
2543 width = REG_D[width&7];
2547 width = ((width-1) & 31) + 1;
2550 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2551 mask = ROR_32(mask, offset);
2553 FLAG_N = NFLAG_32(*data<<offset);
2554 FLAG_Z = *data & mask;
2555 FLAG_V = VFLAG_CLEAR;
2556 FLAG_C = CFLAG_CLEAR;
2562 m68ki_exception_illegal(state);
2566 M68KMAKE_OP(bfclr, 32, ., .)
2568 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2570 uint word2 = OPER_I_16(state);
2571 sint offset = (word2>>6)&31;
2578 uint ea = M68KMAKE_GET_EA_AY_8;
2582 offset = MAKE_INT_32(REG_D[offset&7]);
2584 width = REG_D[width&7];
2586 /* Offset is signed so we have to use ugly math =( */
2594 width = ((width-1) & 31) + 1;
2596 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2597 mask_long = mask_base >> offset;
2599 data_long = m68ki_read_32(state, ea);
2600 FLAG_N = NFLAG_32(data_long << offset);
2601 FLAG_Z = data_long & mask_long;
2602 FLAG_V = VFLAG_CLEAR;
2603 FLAG_C = CFLAG_CLEAR;
2605 m68ki_write_32(state, ea, data_long & ~mask_long);
2607 if((width + offset) > 32)
2609 mask_byte = MASK_OUT_ABOVE_8(mask_base) << (8-offset);
2610 data_byte = m68ki_read_8(state, ea+4);
2611 FLAG_Z |= (data_byte & mask_byte);
2612 m68ki_write_8(state, ea+4, data_byte & ~mask_byte);
2616 m68ki_exception_illegal(state);
2620 M68KMAKE_OP(bfexts, 32, ., d)
2622 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2624 uint word2 = OPER_I_16(state);
2625 uint offset = (word2>>6)&31;
2631 offset = REG_D[offset&7];
2633 width = REG_D[width&7];
2636 width = ((width-1) & 31) + 1;
2638 data = ROL_32(data, offset);
2639 FLAG_N = NFLAG_32(data);
2640 data = MAKE_INT_32(data) >> (32 - width);
2643 FLAG_V = VFLAG_CLEAR;
2644 FLAG_C = CFLAG_CLEAR;
2646 REG_D[(word2>>12)&7] = data;
2650 m68ki_exception_illegal(state);
2654 M68KMAKE_OP(bfexts, 32, ., .)
2656 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2658 uint word2 = OPER_I_16(state);
2659 sint offset = (word2>>6)&31;
2662 uint ea = M68KMAKE_GET_EA_AY_8;
2666 offset = MAKE_INT_32(REG_D[offset&7]);
2668 width = REG_D[width&7];
2671 /* Offset is signed so we have to use ugly math =( */
2680 width = ((width-1) & 31) + 1;
2682 data = (offset+width) < 8 ? (m68ki_read_8(state, ea) << 24) :
2683 (offset+width) < 16 ? (m68ki_read_16(state, ea) << 16) : m68ki_read_32(state, ea);
2685 data = MASK_OUT_ABOVE_32(data<<offset);
2687 if((offset+width) > 32)
2688 data |= (m68ki_read_8(state, ea+4) << offset) >> 8;
2690 FLAG_N = NFLAG_32(data);
2691 data = MAKE_INT_32(data) >> (32 - width);
2694 FLAG_V = VFLAG_CLEAR;
2695 FLAG_C = CFLAG_CLEAR;
2697 REG_D[(word2 >> 12) & 7] = data;
2701 m68ki_exception_illegal(state);
2705 M68KMAKE_OP(bfextu, 32, ., d)
2707 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2709 uint word2 = OPER_I_16(state);
2710 uint offset = (word2>>6)&31;
2716 offset = REG_D[offset&7];
2718 width = REG_D[width&7];
2721 width = ((width-1) & 31) + 1;
2723 data = ROL_32(data, offset);
2724 FLAG_N = NFLAG_32(data);
2725 data >>= 32 - width;
2728 FLAG_V = VFLAG_CLEAR;
2729 FLAG_C = CFLAG_CLEAR;
2731 REG_D[(word2>>12)&7] = data;
2735 m68ki_exception_illegal(state);
2739 M68KMAKE_OP(bfextu, 32, ., .)
2741 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2743 uint word2 = OPER_I_16(state);
2744 sint offset = (word2>>6)&31;
2747 uint ea = M68KMAKE_GET_EA_AY_8;
2751 offset = MAKE_INT_32(REG_D[offset&7]);
2753 width = REG_D[width&7];
2756 /* Offset is signed so we have to use ugly math =( */
2765 width = ((width-1) & 31) + 1;
2767 data = (offset+width) < 8 ? (m68ki_read_8(state, ea) << 24) :
2768 (offset+width) < 16 ? (m68ki_read_16(state, ea) << 16) : m68ki_read_32(state, ea);
2769 data = MASK_OUT_ABOVE_32(data<<offset);
2771 if((offset+width) > 32)
2772 data |= (m68ki_read_8(state, ea+4) << offset) >> 8;
2774 FLAG_N = NFLAG_32(data);
2775 data >>= (32 - width);
2778 FLAG_V = VFLAG_CLEAR;
2779 FLAG_C = CFLAG_CLEAR;
2781 REG_D[(word2 >> 12) & 7] = data;
2785 m68ki_exception_illegal(state);
2789 M68KMAKE_OP(bfffo, 32, ., d)
2791 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2793 uint word2 = OPER_I_16(state);
2794 uint offset = (word2>>6)&31;
2801 offset = REG_D[offset&7];
2803 width = REG_D[width&7];
2806 width = ((width-1) & 31) + 1;
2808 data = ROL_32(data, offset);
2809 FLAG_N = NFLAG_32(data);
2810 data >>= 32 - width;
2813 FLAG_V = VFLAG_CLEAR;
2814 FLAG_C = CFLAG_CLEAR;
2816 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2819 REG_D[(word2>>12)&7] = offset;
2823 m68ki_exception_illegal(state);
2827 M68KMAKE_OP(bfffo, 32, ., .)
2829 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2831 uint word2 = OPER_I_16(state);
2832 sint offset = (word2>>6)&31;
2837 uint ea = M68KMAKE_GET_EA_AY_8;
2841 offset = MAKE_INT_32(REG_D[offset&7]);
2843 width = REG_D[width&7];
2845 /* Offset is signed so we have to use ugly math =( */
2847 local_offset = offset % 8;
2848 if(local_offset < 0)
2853 width = ((width-1) & 31) + 1;
2855 data = (offset+width) < 16 ? (m68ki_read_16(state, ea) << 16) : m68ki_read_32(state, ea);
2856 data = MASK_OUT_ABOVE_32(data<<local_offset);
2858 if((local_offset+width) > 32)
2859 data |= (m68ki_read_8(state, ea+4) << local_offset) >> 8;
2861 FLAG_N = NFLAG_32(data);
2862 data >>= (32 - width);
2865 FLAG_V = VFLAG_CLEAR;
2866 FLAG_C = CFLAG_CLEAR;
2868 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2871 REG_D[(word2>>12)&7] = offset;
2875 m68ki_exception_illegal(state);
2879 M68KMAKE_OP(bfins, 32, ., d)
2881 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2883 uint word2 = OPER_I_16(state);
2884 uint offset = (word2>>6)&31;
2888 uint64 insert = REG_D[(word2>>12)&7];
2892 offset = REG_D[offset&7];
2894 width = REG_D[width&7];
2898 width = ((width-1) & 31) + 1;
2901 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2902 mask = ROR_32(mask, offset);
2904 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
2905 FLAG_N = NFLAG_32(insert);
2907 insert = ROR_32(insert, offset);
2909 FLAG_V = VFLAG_CLEAR;
2910 FLAG_C = CFLAG_CLEAR;
2917 m68ki_exception_illegal(state);
2921 M68KMAKE_OP(bfins, 32, ., .)
2923 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2925 uint word2 = OPER_I_16(state);
2926 sint offset = (word2>>6)&31;
2928 uint insert_base = REG_D[(word2>>12)&7];
2936 uint ea = M68KMAKE_GET_EA_AY_8;
2940 offset = MAKE_INT_32(REG_D[offset&7]);
2942 width = REG_D[width&7];
2945 /* Offset is signed so we have to use ugly math =( */
2954 width = ((width-1) & 31) + 1;
2956 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2957 mask_long = mask_base >> offset;
2959 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
2960 FLAG_N = NFLAG_32(insert_base);
2961 FLAG_Z = insert_base;
2962 insert_long = insert_base >> offset;
2964 data_long = (offset+width) < 8 ? (m68ki_read_8(state, ea) << 24) :
2965 (offset+width) < 16 ? (m68ki_read_16(state, ea) << 16) : m68ki_read_32(state, ea);
2966 FLAG_V = VFLAG_CLEAR;
2967 FLAG_C = CFLAG_CLEAR;
2969 if((width + offset) < 8) {
2970 m68ki_write_8(state, ea, ((data_long & ~mask_long) | insert_long) >> 24);
2971 } else if((width + offset) < 16) {
2972 m68ki_write_16(state, ea, ((data_long & ~mask_long) | insert_long) >> 16);
2974 m68ki_write_32(state, ea, (data_long & ~mask_long) | insert_long);
2977 if((width + offset) > 32)
2979 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2980 insert_byte = MASK_OUT_ABOVE_8(insert_base);
2981 data_byte = m68ki_read_8(state, ea+4);
2982 FLAG_Z |= (data_byte & mask_byte);
2983 m68ki_write_8(state, ea+4, (data_byte & ~mask_byte) | insert_byte);
2987 m68ki_exception_illegal(state);
2991 M68KMAKE_OP(bfset, 32, ., d)
2993 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2995 uint word2 = OPER_I_16(state);
2996 uint offset = (word2>>6)&31;
3003 offset = REG_D[offset&7];
3005 width = REG_D[width&7];
3009 width = ((width-1) & 31) + 1;
3012 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3013 mask = ROR_32(mask, offset);
3015 FLAG_N = NFLAG_32(*data<<offset);
3016 FLAG_Z = *data & mask;
3017 FLAG_V = VFLAG_CLEAR;
3018 FLAG_C = CFLAG_CLEAR;
3024 m68ki_exception_illegal(state);
3028 M68KMAKE_OP(bfset, 32, ., .)
3030 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3032 uint word2 = OPER_I_16(state);
3033 sint offset = (word2>>6)&31;
3040 uint ea = M68KMAKE_GET_EA_AY_8;
3044 offset = MAKE_INT_32(REG_D[offset&7]);
3046 width = REG_D[width&7];
3048 /* Offset is signed so we have to use ugly math =( */
3056 width = ((width-1) & 31) + 1;
3059 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3060 mask_long = mask_base >> offset;
3062 data_long = m68ki_read_32(state, ea);
3063 FLAG_N = NFLAG_32(data_long << offset);
3064 FLAG_Z = data_long & mask_long;
3065 FLAG_V = VFLAG_CLEAR;
3066 FLAG_C = CFLAG_CLEAR;
3068 m68ki_write_32(state, ea, data_long | mask_long);
3070 if((width + offset) > 32)
3072 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3073 data_byte = m68ki_read_8(state, ea+4);
3074 FLAG_Z |= (data_byte & mask_byte);
3075 m68ki_write_8(state, ea+4, data_byte | mask_byte);
3079 m68ki_exception_illegal(state);
3083 M68KMAKE_OP(bftst, 32, ., d)
3085 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3087 uint word2 = OPER_I_16(state);
3088 uint offset = (word2>>6)&31;
3095 offset = REG_D[offset&7];
3097 width = REG_D[width&7];
3101 width = ((width-1) & 31) + 1;
3104 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3105 mask = ROR_32(mask, offset);
3107 FLAG_N = NFLAG_32(*data<<offset);
3108 FLAG_Z = *data & mask;
3109 FLAG_V = VFLAG_CLEAR;
3110 FLAG_C = CFLAG_CLEAR;
3114 m68ki_exception_illegal(state);
3118 M68KMAKE_OP(bftst, 32, ., .)
3120 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3122 uint word2 = OPER_I_16(state);
3123 sint offset = (word2>>6)&31;
3130 uint ea = M68KMAKE_GET_EA_AY_8;
3133 offset = MAKE_INT_32(REG_D[offset&7]);
3135 width = REG_D[width&7];
3137 /* Offset is signed so we have to use ugly math =( */
3145 width = ((width-1) & 31) + 1;
3148 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3149 mask_long = mask_base >> offset;
3151 data_long = m68ki_read_32(state, ea);
3152 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
3153 FLAG_Z = data_long & mask_long;
3154 FLAG_V = VFLAG_CLEAR;
3155 FLAG_C = CFLAG_CLEAR;
3157 if((width + offset) > 32)
3159 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3160 data_byte = m68ki_read_8(state, ea+4);
3161 FLAG_Z |= (data_byte & mask_byte);
3165 m68ki_exception_illegal(state);
3169 M68KMAKE_OP(bkpt, 0, ., .)
3171 // TODO: review this...
3172 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
3174 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
3176 m68ki_exception_illegal(state);
3180 M68KMAKE_OP(bra, 8, ., .)
3182 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3183 m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
3184 // TODO: review this...
3185 // if(REG_PC == REG_PPC)
3186 // USE_ALL_CYCLES();
3190 M68KMAKE_OP(bra, 16, ., .)
3192 uint offset = OPER_I_16(state);
3194 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3195 m68ki_branch_16(state, offset);
3196 // TODO: review this...
3197 // if(REG_PC == REG_PPC)
3198 // USE_ALL_CYCLES();
3202 M68KMAKE_OP(bra, 32, ., .)
3204 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3206 uint offset = OPER_I_32(state);
3208 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3209 m68ki_branch_32(state, offset);
3210 // TODO: review this...
3211 // if(REG_PC == REG_PPC)
3212 // USE_ALL_CYCLES();
3217 // TODO: review this...
3218 m68ki_exception_illegal(state);
3219 // m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3220 // m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
3221 // if(REG_PC == REG_PPC)
3222 // USE_ALL_CYCLES();
3227 M68KMAKE_OP(bset, 32, r, d)
3230 uint mask = 1 << (DX & 0x1f);
3232 FLAG_Z = *r_dst & mask;
3237 M68KMAKE_OP(bset, 8, r, .)
3239 uint ea = M68KMAKE_GET_EA_AY_8;
3240 uint src = m68ki_read_8(state, ea);
3241 uint mask = 1 << (DX & 7);
3243 FLAG_Z = src & mask;
3244 m68ki_write_8(state, ea, src | mask);
3248 M68KMAKE_OP(bset, 32, s, d)
3251 uint mask = 1 << (OPER_I_8(state) & 0x1f);
3253 FLAG_Z = *r_dst & mask;
3258 M68KMAKE_OP(bset, 8, s, .)
3260 uint mask = 1 << (OPER_I_8(state) & 7);
3261 uint ea = M68KMAKE_GET_EA_AY_8;
3262 uint src = m68ki_read_8(state, ea);
3264 FLAG_Z = src & mask;
3265 m68ki_write_8(state, ea, src | mask);
3269 M68KMAKE_OP(bsr, 8, ., .)
3271 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3272 m68ki_push_32(state, REG_PC);
3273 m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
3277 M68KMAKE_OP(bsr, 16, ., .)
3279 uint offset = OPER_I_16(state);
3280 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3281 m68ki_push_32(state, REG_PC);
3283 m68ki_branch_16(state, offset);
3287 M68KMAKE_OP(bsr, 32, ., .)
3289 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3291 uint offset = OPER_I_32(state);
3292 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3293 m68ki_push_32(state, REG_PC);
3295 m68ki_branch_32(state, offset);
3300 // TODO: review this...
3301 m68ki_exception_illegal(state);
3302 // m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3303 // m68ki_push_32(state, REG_PC);
3304 // m68ki_branch_8(state, MASK_OUT_ABOVE_8(REG_IR));
3309 M68KMAKE_OP(btst, 32, r, d)
3311 FLAG_Z = DY & (1 << (DX & 0x1f));
3315 M68KMAKE_OP(btst, 8, r, .)
3317 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
3321 M68KMAKE_OP(btst, 32, s, d)
3323 FLAG_Z = DY & (1 << (OPER_I_8(state) & 0x1f));
3327 M68KMAKE_OP(btst, 8, s, .)
3329 uint bit = OPER_I_8(state) & 7;
3331 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
3335 M68KMAKE_OP(callm, 32, ., .)
3337 /* note: watch out for pcrelative modes */
3338 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
3340 uint ea = M68KMAKE_GET_EA_AY_32;
3342 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3344 (void)ea; /* just to avoid an 'unused variable' warning */
3345 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
3346 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
3347 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
3350 m68ki_exception_illegal(state);
3354 M68KMAKE_OP(cas, 8, ., .)
3356 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3358 uint word2 = OPER_I_16(state);
3359 uint ea = M68KMAKE_GET_EA_AY_8;
3360 uint dest = m68ki_read_8(state, ea);
3361 uint* compare = ®_D[word2 & 7];
3362 uint res = dest - MASK_OUT_ABOVE_8(*compare);
3364 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3365 FLAG_N = NFLAG_8(res);
3366 FLAG_Z = MASK_OUT_ABOVE_8(res);
3367 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
3368 FLAG_C = CFLAG_8(res);
3371 *compare = MASK_OUT_BELOW_8(*compare) | dest;
3375 m68ki_write_8(state, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
3379 m68ki_exception_illegal(state);
3383 M68KMAKE_OP(cas, 16, ., .)
3385 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3387 uint word2 = OPER_I_16(state);
3388 uint ea = M68KMAKE_GET_EA_AY_16;
3389 uint dest = m68ki_read_16(state, ea);
3390 uint* compare = ®_D[word2 & 7];
3391 uint res = dest - MASK_OUT_ABOVE_16(*compare);
3393 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3394 FLAG_N = NFLAG_16(res);
3395 FLAG_Z = MASK_OUT_ABOVE_16(res);
3396 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
3397 FLAG_C = CFLAG_16(res);
3400 *compare = MASK_OUT_BELOW_16(*compare) | dest;
3404 m68ki_write_16(state, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
3408 m68ki_exception_illegal(state);
3412 M68KMAKE_OP(cas, 32, ., .)
3414 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3416 uint word2 = OPER_I_16(state);
3417 uint ea = M68KMAKE_GET_EA_AY_32;
3418 uint dest = m68ki_read_32(state, ea);
3419 uint* compare = ®_D[word2 & 7];
3420 uint res = dest - *compare;
3422 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3423 FLAG_N = NFLAG_32(res);
3424 FLAG_Z = MASK_OUT_ABOVE_32(res);
3425 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
3426 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
3433 m68ki_write_32(state, ea, REG_D[(word2 >> 6) & 7]);
3437 m68ki_exception_illegal(state);
3441 M68KMAKE_OP(cas2, 16, ., .)
3443 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3445 uint word2 = OPER_I_32(state);
3446 uint* compare1 = ®_D[(word2 >> 16) & 7];
3447 uint ea1 = REG_DA[(word2 >> 28) & 15];
3448 uint dest1 = m68ki_read_16(state, ea1);
3449 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
3450 uint* compare2 = ®_D[word2 & 7];
3451 uint ea2 = REG_DA[(word2 >> 12) & 15];
3452 uint dest2 = m68ki_read_16(state, ea2);
3455 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3456 FLAG_N = NFLAG_16(res1);
3457 FLAG_Z = MASK_OUT_ABOVE_16(res1);
3458 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
3459 FLAG_C = CFLAG_16(res1);
3463 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
3465 FLAG_N = NFLAG_16(res2);
3466 FLAG_Z = MASK_OUT_ABOVE_16(res2);
3467 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
3468 FLAG_C = CFLAG_16(res2);
3473 m68ki_write_16(state, ea1, REG_D[(word2 >> 22) & 7]);
3474 m68ki_write_16(state, ea2, REG_D[(word2 >> 6) & 7]);
3478 *compare1 = BIT_1F(word2) ? (uint)MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
3479 *compare2 = BIT_F(word2) ? (uint)MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
3482 m68ki_exception_illegal(state);
3486 M68KMAKE_OP(cas2, 32, ., .)
3488 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3490 uint word2 = OPER_I_32(state);
3491 uint* compare1 = ®_D[(word2 >> 16) & 7];
3492 uint ea1 = REG_DA[(word2 >> 28) & 15];
3493 uint dest1 = m68ki_read_32(state, ea1);
3494 uint res1 = dest1 - *compare1;
3495 uint* compare2 = ®_D[word2 & 7];
3496 uint ea2 = REG_DA[(word2 >> 12) & 15];
3497 uint dest2 = m68ki_read_32(state, ea2);
3500 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3501 FLAG_N = NFLAG_32(res1);
3502 FLAG_Z = MASK_OUT_ABOVE_32(res1);
3503 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
3504 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
3508 res2 = dest2 - *compare2;
3510 FLAG_N = NFLAG_32(res2);
3511 FLAG_Z = MASK_OUT_ABOVE_32(res2);
3512 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
3513 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
3518 m68ki_write_32(state, ea1, REG_D[(word2 >> 22) & 7]);
3519 m68ki_write_32(state, ea2, REG_D[(word2 >> 6) & 7]);
3527 m68ki_exception_illegal(state);
3531 M68KMAKE_OP(chk, 16, ., d)
3533 sint src = MAKE_INT_16(DX);
3534 sint bound = MAKE_INT_16(DY);
3536 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3537 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3538 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3540 if(src >= 0 && src <= bound)
3544 FLAG_N = (src < 0)<<7;
3545 m68ki_exception_trap(state, EXCEPTION_CHK);
3549 M68KMAKE_OP(chk, 16, ., .)
3551 sint src = MAKE_INT_16(DX);
3552 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3554 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3555 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3556 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3558 if(src >= 0 && src <= bound)
3562 FLAG_N = (src < 0)<<7;
3563 m68ki_exception_trap(state, EXCEPTION_CHK);
3567 M68KMAKE_OP(chk, 32, ., d)
3569 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3571 sint src = MAKE_INT_32(DX);
3572 sint bound = MAKE_INT_32(DY);
3574 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3575 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3576 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3578 if(src >= 0 && src <= bound)
3582 FLAG_N = (src < 0)<<7;
3583 m68ki_exception_trap(state, EXCEPTION_CHK);
3586 m68ki_exception_illegal(state);
3590 M68KMAKE_OP(chk, 32, ., .)
3592 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3594 sint src = MAKE_INT_32(DX);
3595 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
3597 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3598 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3599 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3601 if(src >= 0 && src <= bound)
3605 FLAG_N = (src < 0)<<7;
3606 m68ki_exception_trap(state, EXCEPTION_CHK);
3609 m68ki_exception_illegal(state);
3613 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
3615 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3617 uint word2 = OPER_I_16(state);
3618 sint compare = REG_DA[(word2 >> 12) & 15];
3622 uint ea = EA_PCDI_8();
3623 sint lower_bound = m68ki_read_pcrel_8(state, ea);
3624 sint upper_bound = m68ki_read_pcrel_8(state, ea + 1);
3626 // for signed compare, the arithmetically smaller value is the lower bound
3627 if (lower_bound & 0x80) {
3628 lower_bound = (int32)(int8)lower_bound;
3629 upper_bound = (int32)(int8)upper_bound;
3632 compare = (int32)(int8)compare;
3635 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3636 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3638 if(COND_CS() && BIT_B(word2))
3639 m68ki_exception_trap(state, EXCEPTION_CHK);
3644 m68ki_exception_illegal(state);
3648 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
3650 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3652 uint word2 = OPER_I_16(state);
3653 sint compare = REG_DA[(word2 >> 12) & 15];
3657 uint ea = EA_PCIX_8();
3658 sint lower_bound = m68ki_read_pcrel_8(state, ea);
3659 sint upper_bound = m68ki_read_pcrel_8(state, ea + 1);
3661 if (lower_bound & 0x80) {
3662 lower_bound = (int32)(int8)lower_bound;
3663 upper_bound = (int32)(int8)upper_bound;
3666 compare = (int32)(int8)compare;
3669 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3670 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3672 if(COND_CS() && BIT_B(word2))
3673 m68ki_exception_trap(state, EXCEPTION_CHK);
3677 m68ki_exception_illegal(state);
3681 M68KMAKE_OP(chk2cmp2, 8, ., .)
3683 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3685 uint word2 = OPER_I_16(state);
3686 sint compare = REG_DA[(word2 >> 12) & 15];
3690 uint ea = M68KMAKE_GET_EA_AY_8;
3691 sint lower_bound = (int8)m68ki_read_8(state, ea);
3692 sint upper_bound = (int8)m68ki_read_8(state, ea + 1);
3694 // for signed compare, the arithmetically smaller value is the lower bound
3695 if (lower_bound & 0x80) {
3696 lower_bound = (int32)(int8)lower_bound;
3697 upper_bound = (int32)(int8)upper_bound;
3700 compare = (int32)(int8)compare;
3703 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3704 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3706 if(COND_CS() && BIT_B(word2))
3707 m68ki_exception_trap(state, EXCEPTION_CHK);
3710 m68ki_exception_illegal(state);
3714 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
3716 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3718 uint word2 = OPER_I_16(state);
3719 sint compare = REG_DA[(word2 >> 12) & 15];
3723 uint ea = EA_PCDI_16();
3724 sint lower_bound = (int16)m68ki_read_pcrel_16(state, ea);
3725 sint upper_bound = (int16)m68ki_read_pcrel_16(state, ea + 2);
3727 // for signed compare, the arithmetically smaller value is the lower bound
3728 if (lower_bound & 0x8000) {
3729 lower_bound = (int32)(int16)lower_bound;
3730 upper_bound = (int32)(int16)upper_bound;
3733 compare = (int32)(int16)compare;
3736 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3737 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3739 if(COND_CS() && BIT_B(word2))
3740 m68ki_exception_trap(state, EXCEPTION_CHK);
3743 m68ki_exception_illegal(state);
3747 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
3749 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3751 uint word2 = OPER_I_16(state);
3752 sint compare = REG_DA[(word2 >> 12) & 15];
3756 uint ea = EA_PCIX_16();
3757 sint lower_bound = (int16)m68ki_read_pcrel_16(state, ea);
3758 sint upper_bound = (int16)m68ki_read_pcrel_16(state, ea + 2);
3760 // for signed compare, the arithmetically smaller value is the lower bound
3761 if (lower_bound & 0x8000) {
3762 lower_bound = (int32)(int16)lower_bound;
3763 upper_bound = (int32)(int16)upper_bound;
3766 compare = (int32)(int16)compare;
3769 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3770 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3772 if(COND_CS() && BIT_B(word2))
3773 m68ki_exception_trap(state, EXCEPTION_CHK);
3776 m68ki_exception_illegal(state);
3780 M68KMAKE_OP(chk2cmp2, 16, ., .)
3782 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3784 uint word2 = OPER_I_16(state);
3785 sint compare = REG_DA[(word2 >> 12) & 15];
3789 uint ea = M68KMAKE_GET_EA_AY_16;
3790 sint lower_bound = (int16)m68ki_read_16(state, ea);
3791 sint upper_bound = (int16)m68ki_read_16(state, ea + 2);
3793 // for signed compare, the arithmetically smaller value is the lower bound
3794 if (lower_bound & 0x8000) {
3795 lower_bound = (int32)(int16)lower_bound;
3796 upper_bound = (int32)(int16)upper_bound;
3799 compare = (int32)(int16)compare;
3802 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3803 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3805 if(COND_CS() && BIT_B(word2))
3806 m68ki_exception_trap(state, EXCEPTION_CHK);
3809 m68ki_exception_illegal(state);
3813 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
3815 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3817 uint32 word2 = OPER_I_16(state);
3818 sint64 compare = REG_DA[(word2 >> 12) & 15];
3819 uint32 ea = EA_PCDI_32();
3820 sint64 lower_bound = m68ki_read_pcrel_32(state, ea);
3821 sint64 upper_bound = m68ki_read_pcrel_32(state, ea + 4);
3823 // for signed compare, the arithmetically smaller value is the lower bound
3824 if (lower_bound & 0x80000000) {
3825 lower_bound = (int64)(int32)lower_bound;
3826 upper_bound = (int64)(int32)upper_bound;
3827 compare = (int64)(int32)compare;
3830 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3831 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3833 if(COND_CS() && BIT_B(word2))
3834 m68ki_exception_trap(state, EXCEPTION_CHK);
3837 m68ki_exception_illegal(state);
3841 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
3843 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3845 uint32 word2 = OPER_I_16(state);
3846 sint64 compare = REG_DA[(word2 >> 12) & 15];
3847 uint32 ea = EA_PCIX_32();
3848 sint64 lower_bound = m68ki_read_32(state, ea);
3849 sint64 upper_bound = m68ki_read_32(state, ea + 4);
3851 // for signed compare, the arithmetically smaller value is the lower bound
3852 if (lower_bound & 0x80000000) {
3853 lower_bound = (int64)(int32)lower_bound;
3854 upper_bound = (int64)(int32)upper_bound;
3855 compare = (int64)(int32)compare;
3858 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3859 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3861 if(COND_CS() && BIT_B(word2))
3862 m68ki_exception_trap(state, EXCEPTION_CHK);
3865 m68ki_exception_illegal(state);
3869 M68KMAKE_OP(chk2cmp2, 32, ., .)
3871 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3873 uint32 word2 = OPER_I_16(state);
3874 sint64 compare = REG_DA[(word2 >> 12) & 15];
3875 uint32 ea = M68KMAKE_GET_EA_AY_32;
3876 sint64 lower_bound = m68ki_read_32(state, ea);
3877 sint64 upper_bound = m68ki_read_32(state, ea + 4);
3879 // for signed compare, the arithmetically smaller value is the lower bound
3880 if (lower_bound & 0x80000000) {
3881 lower_bound = (int64)(int32)lower_bound;
3882 upper_bound = (int64)(int32)upper_bound;
3883 compare = (int64)(int32)compare;
3886 FLAG_C = (compare >= lower_bound && compare <= upper_bound) ? CFLAG_CLEAR : CFLAG_SET;
3887 FLAG_Z = ((upper_bound == compare) || (lower_bound == compare)) ? 0 : 1;
3889 if(COND_CS() && BIT_B(word2))
3890 m68ki_exception_trap(state, EXCEPTION_CHK);
3893 m68ki_exception_illegal(state);
3897 M68KMAKE_OP(clr, 8, ., d)
3901 FLAG_N = NFLAG_CLEAR;
3902 FLAG_V = VFLAG_CLEAR;
3903 FLAG_C = CFLAG_CLEAR;
3908 M68KMAKE_OP(clr, 8, ., .)
3910 uint32 ea = M68KMAKE_GET_EA_AY_8;
3912 if(CPU_TYPE_IS_000(CPU_TYPE))
3913 m68ki_read_8(state, ea); /* the 68000 does a dummy read, the value is discarded */
3914 m68ki_write_8(state, ea, 0);
3916 FLAG_N = NFLAG_CLEAR;
3917 FLAG_V = VFLAG_CLEAR;
3918 FLAG_C = CFLAG_CLEAR;
3923 M68KMAKE_OP(clr, 16, ., d)
3927 FLAG_N = NFLAG_CLEAR;
3928 FLAG_V = VFLAG_CLEAR;
3929 FLAG_C = CFLAG_CLEAR;
3934 M68KMAKE_OP(clr, 16, ., .)
3936 uint32 ea = M68KMAKE_GET_EA_AY_16;
3938 if(CPU_TYPE_IS_000(CPU_TYPE))
3939 m68ki_read_16(state, ea); /* the 68000 does a dummy read, the value is discarded */
3940 m68ki_write_16(state, ea, 0);
3942 FLAG_N = NFLAG_CLEAR;
3943 FLAG_V = VFLAG_CLEAR;
3944 FLAG_C = CFLAG_CLEAR;
3949 M68KMAKE_OP(clr, 32, ., d)
3953 FLAG_N = NFLAG_CLEAR;
3954 FLAG_V = VFLAG_CLEAR;
3955 FLAG_C = CFLAG_CLEAR;
3960 M68KMAKE_OP(clr, 32, ., .)
3962 uint32 ea = M68KMAKE_GET_EA_AY_32;
3964 if(CPU_TYPE_IS_000(CPU_TYPE))
3965 m68ki_read_32(state, ea); /* the 68000 does a dummy read, the value is discarded */
3966 m68ki_write_32(state, ea, 0);
3968 FLAG_N = NFLAG_CLEAR;
3969 FLAG_V = VFLAG_CLEAR;
3970 FLAG_C = CFLAG_CLEAR;
3975 M68KMAKE_OP(cmp, 8, ., d)
3977 uint src = MASK_OUT_ABOVE_8(DY);
3978 uint dst = MASK_OUT_ABOVE_8(DX);
3979 uint res = dst - src;
3981 FLAG_N = NFLAG_8(res);
3982 FLAG_Z = MASK_OUT_ABOVE_8(res);
3983 FLAG_V = VFLAG_SUB_8(src, dst, res);
3984 FLAG_C = CFLAG_8(res);
3988 M68KMAKE_OP(cmp, 8, ., .)
3990 uint src = M68KMAKE_GET_OPER_AY_8;
3991 uint dst = MASK_OUT_ABOVE_8(DX);
3992 uint res = dst - src;
3994 FLAG_N = NFLAG_8(res);
3995 FLAG_Z = MASK_OUT_ABOVE_8(res);
3996 FLAG_V = VFLAG_SUB_8(src, dst, res);
3997 FLAG_C = CFLAG_8(res);
4001 M68KMAKE_OP(cmp, 16, ., d)
4003 uint src = MASK_OUT_ABOVE_16(DY);
4004 uint dst = MASK_OUT_ABOVE_16(DX);
4005 uint res = dst - src;
4007 FLAG_N = NFLAG_16(res);
4008 FLAG_Z = MASK_OUT_ABOVE_16(res);
4009 FLAG_V = VFLAG_SUB_16(src, dst, res);
4010 FLAG_C = CFLAG_16(res);
4014 M68KMAKE_OP(cmp, 16, ., a)
4016 uint src = MASK_OUT_ABOVE_16(AY);
4017 uint dst = MASK_OUT_ABOVE_16(DX);
4018 uint res = dst - src;
4020 FLAG_N = NFLAG_16(res);
4021 FLAG_Z = MASK_OUT_ABOVE_16(res);
4022 FLAG_V = VFLAG_SUB_16(src, dst, res);
4023 FLAG_C = CFLAG_16(res);
4027 M68KMAKE_OP(cmp, 16, ., .)
4029 uint src = M68KMAKE_GET_OPER_AY_16;
4030 uint dst = MASK_OUT_ABOVE_16(DX);
4031 uint res = dst - src;
4033 FLAG_N = NFLAG_16(res);
4034 FLAG_Z = MASK_OUT_ABOVE_16(res);
4035 FLAG_V = VFLAG_SUB_16(src, dst, res);
4036 FLAG_C = CFLAG_16(res);
4040 M68KMAKE_OP(cmp, 32, ., d)
4044 uint res = dst - src;
4046 FLAG_N = NFLAG_32(res);
4047 FLAG_Z = MASK_OUT_ABOVE_32(res);
4048 FLAG_V = VFLAG_SUB_32(src, dst, res);
4049 FLAG_C = CFLAG_SUB_32(src, dst, res);
4053 M68KMAKE_OP(cmp, 32, ., a)
4057 uint res = dst - src;
4059 FLAG_N = NFLAG_32(res);
4060 FLAG_Z = MASK_OUT_ABOVE_32(res);
4061 FLAG_V = VFLAG_SUB_32(src, dst, res);
4062 FLAG_C = CFLAG_SUB_32(src, dst, res);
4066 M68KMAKE_OP(cmp, 32, ., .)
4068 uint src = M68KMAKE_GET_OPER_AY_32;
4070 uint res = dst - src;
4072 FLAG_N = NFLAG_32(res);
4073 FLAG_Z = MASK_OUT_ABOVE_32(res);
4074 FLAG_V = VFLAG_SUB_32(src, dst, res);
4075 FLAG_C = CFLAG_SUB_32(src, dst, res);
4079 M68KMAKE_OP(cmpa, 16, ., d)
4081 uint src = MAKE_INT_16(DY);
4083 uint res = dst - src;
4085 FLAG_N = NFLAG_32(res);
4086 FLAG_Z = MASK_OUT_ABOVE_32(res);
4087 FLAG_V = VFLAG_SUB_32(src, dst, res);
4088 FLAG_C = CFLAG_SUB_32(src, dst, res);
4092 M68KMAKE_OP(cmpa, 16, ., a)
4094 uint src = MAKE_INT_16(AY);
4096 uint res = dst - src;
4098 FLAG_N = NFLAG_32(res);
4099 FLAG_Z = MASK_OUT_ABOVE_32(res);
4100 FLAG_V = VFLAG_SUB_32(src, dst, res);
4101 FLAG_C = CFLAG_SUB_32(src, dst, res);
4105 M68KMAKE_OP(cmpa, 16, ., .)
4107 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4109 uint res = dst - src;
4111 FLAG_N = NFLAG_32(res);
4112 FLAG_Z = MASK_OUT_ABOVE_32(res);
4113 FLAG_V = VFLAG_SUB_32(src, dst, res);
4114 FLAG_C = CFLAG_SUB_32(src, dst, res);
4118 M68KMAKE_OP(cmpa, 32, ., d)
4122 uint res = dst - src;
4124 FLAG_N = NFLAG_32(res);
4125 FLAG_Z = MASK_OUT_ABOVE_32(res);
4126 FLAG_V = VFLAG_SUB_32(src, dst, res);
4127 FLAG_C = CFLAG_SUB_32(src, dst, res);
4131 M68KMAKE_OP(cmpa, 32, ., a)
4135 uint res = dst - src;
4137 FLAG_N = NFLAG_32(res);
4138 FLAG_Z = MASK_OUT_ABOVE_32(res);
4139 FLAG_V = VFLAG_SUB_32(src, dst, res);
4140 FLAG_C = CFLAG_SUB_32(src, dst, res);
4144 M68KMAKE_OP(cmpa, 32, ., .)
4146 uint src = M68KMAKE_GET_OPER_AY_32;
4148 uint res = dst - src;
4150 FLAG_N = NFLAG_32(res);
4151 FLAG_Z = MASK_OUT_ABOVE_32(res);
4152 FLAG_V = VFLAG_SUB_32(src, dst, res);
4153 FLAG_C = CFLAG_SUB_32(src, dst, res);
4157 M68KMAKE_OP(cmpi, 8, ., d)
4159 uint src = OPER_I_8(state);
4160 uint dst = MASK_OUT_ABOVE_8(DY);
4161 uint res = dst - src;
4163 FLAG_N = NFLAG_8(res);
4164 FLAG_Z = MASK_OUT_ABOVE_8(res);
4165 FLAG_V = VFLAG_SUB_8(src, dst, res);
4166 FLAG_C = CFLAG_8(res);
4170 M68KMAKE_OP(cmpi, 8, ., .)
4172 uint src = OPER_I_8(state);
4173 uint dst = M68KMAKE_GET_OPER_AY_8;
4174 uint res = dst - src;
4176 FLAG_N = NFLAG_8(res);
4177 FLAG_Z = MASK_OUT_ABOVE_8(res);
4178 FLAG_V = VFLAG_SUB_8(src, dst, res);
4179 FLAG_C = CFLAG_8(res);
4183 M68KMAKE_OP(cmpi, 8, ., pcdi)
4185 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4187 uint src = OPER_I_8(state);
4188 uint dst = OPER_PCDI_8(state);
4189 uint res = dst - src;
4191 FLAG_N = NFLAG_8(res);
4192 FLAG_Z = MASK_OUT_ABOVE_8(res);
4193 FLAG_V = VFLAG_SUB_8(src, dst, res);
4194 FLAG_C = CFLAG_8(res);
4197 m68ki_exception_illegal(state);
4201 M68KMAKE_OP(cmpi, 8, ., pcix)
4203 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4205 uint src = OPER_I_8(state);
4206 uint dst = OPER_PCIX_8(state);
4207 uint res = dst - src;
4209 FLAG_N = NFLAG_8(res);
4210 FLAG_Z = MASK_OUT_ABOVE_8(res);
4211 FLAG_V = VFLAG_SUB_8(src, dst, res);
4212 FLAG_C = CFLAG_8(res);
4215 m68ki_exception_illegal(state);
4219 M68KMAKE_OP(cmpi, 16, ., d)
4221 uint src = OPER_I_16(state);
4222 uint dst = MASK_OUT_ABOVE_16(DY);
4223 uint res = dst - src;
4225 FLAG_N = NFLAG_16(res);
4226 FLAG_Z = MASK_OUT_ABOVE_16(res);
4227 FLAG_V = VFLAG_SUB_16(src, dst, res);
4228 FLAG_C = CFLAG_16(res);
4232 M68KMAKE_OP(cmpi, 16, ., .)
4234 uint src = OPER_I_16(state);
4235 uint dst = M68KMAKE_GET_OPER_AY_16;
4236 uint res = dst - src;
4238 FLAG_N = NFLAG_16(res);
4239 FLAG_Z = MASK_OUT_ABOVE_16(res);
4240 FLAG_V = VFLAG_SUB_16(src, dst, res);
4241 FLAG_C = CFLAG_16(res);
4245 M68KMAKE_OP(cmpi, 16, ., pcdi)
4247 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4249 uint src = OPER_I_16(state);
4250 uint dst = OPER_PCDI_16(state);
4251 uint res = dst - src;
4253 FLAG_N = NFLAG_16(res);
4254 FLAG_Z = MASK_OUT_ABOVE_16(res);
4255 FLAG_V = VFLAG_SUB_16(src, dst, res);
4256 FLAG_C = CFLAG_16(res);
4259 m68ki_exception_illegal(state);
4263 M68KMAKE_OP(cmpi, 16, ., pcix)
4265 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4267 uint src = OPER_I_16(state);
4268 uint dst = OPER_PCIX_16(state);
4269 uint res = dst - src;
4271 FLAG_N = NFLAG_16(res);
4272 FLAG_Z = MASK_OUT_ABOVE_16(res);
4273 FLAG_V = VFLAG_SUB_16(src, dst, res);
4274 FLAG_C = CFLAG_16(res);
4277 m68ki_exception_illegal(state);
4281 M68KMAKE_OP(cmpi, 32, ., d)
4283 uint src = OPER_I_32(state);
4285 uint res = dst - src;
4287 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
4288 FLAG_N = NFLAG_32(res);
4289 FLAG_Z = MASK_OUT_ABOVE_32(res);
4290 FLAG_V = VFLAG_SUB_32(src, dst, res);
4291 FLAG_C = CFLAG_SUB_32(src, dst, res);
4295 M68KMAKE_OP(cmpi, 32, ., .)
4297 uint src = OPER_I_32(state);
4298 uint dst = M68KMAKE_GET_OPER_AY_32;
4299 uint res = dst - src;
4301 FLAG_N = NFLAG_32(res);
4302 FLAG_Z = MASK_OUT_ABOVE_32(res);
4303 FLAG_V = VFLAG_SUB_32(src, dst, res);
4304 FLAG_C = CFLAG_SUB_32(src, dst, res);
4308 M68KMAKE_OP(cmpi, 32, ., pcdi)
4310 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4312 uint src = OPER_I_32(state);
4313 uint dst = OPER_PCDI_32(state);
4314 uint res = dst - src;
4316 FLAG_N = NFLAG_32(res);
4317 FLAG_Z = MASK_OUT_ABOVE_32(res);
4318 FLAG_V = VFLAG_SUB_32(src, dst, res);
4319 FLAG_C = CFLAG_SUB_32(src, dst, res);
4322 m68ki_exception_illegal(state);
4326 M68KMAKE_OP(cmpi, 32, ., pcix)
4328 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4330 uint src = OPER_I_32(state);
4331 uint dst = OPER_PCIX_32(state);
4332 uint res = dst - src;
4334 FLAG_N = NFLAG_32(res);
4335 FLAG_Z = MASK_OUT_ABOVE_32(res);
4336 FLAG_V = VFLAG_SUB_32(src, dst, res);
4337 FLAG_C = CFLAG_SUB_32(src, dst, res);
4340 m68ki_exception_illegal(state);
4344 M68KMAKE_OP(cmpm, 8, ., ax7)
4346 uint src = OPER_AY_PI_8(state);
4347 uint dst = OPER_A7_PI_8(state);
4348 uint res = dst - src;
4350 FLAG_N = NFLAG_8(res);
4351 FLAG_Z = MASK_OUT_ABOVE_8(res);
4352 FLAG_V = VFLAG_SUB_8(src, dst, res);
4353 FLAG_C = CFLAG_8(res);
4357 M68KMAKE_OP(cmpm, 8, ., ay7)
4359 uint src = OPER_A7_PI_8(state);
4360 uint dst = OPER_AX_PI_8(state);
4361 uint res = dst - src;
4363 FLAG_N = NFLAG_8(res);
4364 FLAG_Z = MASK_OUT_ABOVE_8(res);
4365 FLAG_V = VFLAG_SUB_8(src, dst, res);
4366 FLAG_C = CFLAG_8(res);
4370 M68KMAKE_OP(cmpm, 8, ., axy7)
4372 uint src = OPER_A7_PI_8(state);
4373 uint dst = OPER_A7_PI_8(state);
4374 uint res = dst - src;
4376 FLAG_N = NFLAG_8(res);
4377 FLAG_Z = MASK_OUT_ABOVE_8(res);
4378 FLAG_V = VFLAG_SUB_8(src, dst, res);
4379 FLAG_C = CFLAG_8(res);
4383 M68KMAKE_OP(cmpm, 8, ., .)
4385 uint src = OPER_AY_PI_8(state);
4386 uint dst = OPER_AX_PI_8(state);
4387 uint res = dst - src;
4389 FLAG_N = NFLAG_8(res);
4390 FLAG_Z = MASK_OUT_ABOVE_8(res);
4391 FLAG_V = VFLAG_SUB_8(src, dst, res);
4392 FLAG_C = CFLAG_8(res);
4396 M68KMAKE_OP(cmpm, 16, ., .)
4398 uint src = OPER_AY_PI_16(state);
4399 uint dst = OPER_AX_PI_16(state);
4400 uint res = dst - src;
4402 FLAG_N = NFLAG_16(res);
4403 FLAG_Z = MASK_OUT_ABOVE_16(res);
4404 FLAG_V = VFLAG_SUB_16(src, dst, res);
4405 FLAG_C = CFLAG_16(res);
4409 M68KMAKE_OP(cmpm, 32, ., .)
4411 uint src = OPER_AY_PI_32(state);
4412 uint dst = OPER_AX_PI_32(state);
4413 uint res = dst - src;
4415 FLAG_N = NFLAG_32(res);
4416 FLAG_Z = MASK_OUT_ABOVE_32(res);
4417 FLAG_V = VFLAG_SUB_32(src, dst, res);
4418 FLAG_C = CFLAG_SUB_32(src, dst, res);
4422 M68KMAKE_OP(cpbcc, 32, ., .)
4424 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4426 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4427 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4428 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4431 m68ki_exception_1111(state);
4435 M68KMAKE_OP(cpdbcc, 32, ., .)
4437 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4439 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4440 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4441 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4444 m68ki_exception_1111(state);
4448 M68KMAKE_OP(cpgen, 32, ., .)
4450 // TODO: what's the condition?
4451 // if(HAS_FPU || HAS_PMMU)
4452 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4454 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4455 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4456 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4459 m68ki_exception_1111(state);
4463 M68KMAKE_OP(cpscc, 32, ., .)
4465 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4467 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4468 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4469 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4472 m68ki_exception_1111(state);
4476 M68KMAKE_OP(cptrapcc, 32, ., .)
4478 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4480 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4481 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4482 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
4483 // JFF: unsupported, but at least if the trap doesn't occur, app should still work, so at least PC increase is correct
4487 m68ki_exception_1111(state);
4490 M68KMAKE_OP(ftrapcc,32, ., .)
4494 m68881_ftrap(state);
4496 m68ki_exception_1111(state);
4500 M68KMAKE_OP(dbt, 16, ., .)
4506 M68KMAKE_OP(dbf, 16, ., .)
4509 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4511 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4514 uint offset = OPER_I_16(state);
4516 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4517 m68ki_branch_16(state, offset);
4518 USE_CYCLES(CYC_DBCC_F_NOEXP);
4522 USE_CYCLES(CYC_DBCC_F_EXP);
4526 M68KMAKE_OP(dbcc, 16, ., .)
4531 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4533 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4536 uint offset = OPER_I_16(state);
4538 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4539 m68ki_branch_16(state, offset);
4540 USE_CYCLES(CYC_DBCC_F_NOEXP);
4544 USE_CYCLES(CYC_DBCC_F_EXP);
4551 M68KMAKE_OP(divs, 16, ., d)
4554 sint src = MAKE_INT_16(DY);
4560 FLAG_C = CFLAG_CLEAR;
4561 if((uint32)*r_dst == 0x80000000 && src == -1)
4564 FLAG_N = NFLAG_CLEAR;
4565 FLAG_V = VFLAG_CLEAR;
4570 quotient = MAKE_INT_32(*r_dst) / src;
4571 remainder = MAKE_INT_32(*r_dst) % src;
4573 if(quotient == MAKE_INT_16(quotient))
4576 FLAG_N = NFLAG_16(quotient);
4577 FLAG_V = VFLAG_CLEAR;
4578 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4584 m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
4588 M68KMAKE_OP(divs, 16, ., .)
4591 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4597 FLAG_C = CFLAG_CLEAR;
4598 if((uint32)*r_dst == 0x80000000 && src == -1)
4601 FLAG_N = NFLAG_CLEAR;
4602 FLAG_V = VFLAG_CLEAR;
4607 quotient = MAKE_INT_32(*r_dst) / src;
4608 remainder = MAKE_INT_32(*r_dst) % src;
4610 if(quotient == MAKE_INT_16(quotient))
4613 FLAG_N = NFLAG_16(quotient);
4614 FLAG_V = VFLAG_CLEAR;
4615 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4621 m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
4625 M68KMAKE_OP(divu, 16, ., d)
4628 uint src = MASK_OUT_ABOVE_16(DY);
4632 FLAG_C = CFLAG_CLEAR;
4633 uint quotient = *r_dst / src;
4634 uint remainder = *r_dst % src;
4636 if(quotient < 0x10000)
4639 FLAG_N = NFLAG_16(quotient);
4640 FLAG_V = VFLAG_CLEAR;
4641 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4647 m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
4651 M68KMAKE_OP(divu, 16, ., .)
4654 uint src = M68KMAKE_GET_OPER_AY_16;
4658 FLAG_C = CFLAG_CLEAR;
4659 uint quotient = *r_dst / src;
4660 uint remainder = *r_dst % src;
4662 if(quotient < 0x10000)
4665 FLAG_N = NFLAG_16(quotient);
4666 FLAG_V = VFLAG_CLEAR;
4667 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4673 m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
4677 M68KMAKE_OP(divl, 32, ., d)
4681 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4683 uint word2 = OPER_I_16(state);
4684 uint64 divisor = DY;
4685 uint64 dividend = 0;
4686 uint64 quotient = 0;
4687 uint64 remainder = 0;
4691 if(BIT_A(word2)) /* 64 bit */
4693 dividend = REG_D[word2 & 7];
4695 dividend |= REG_D[(word2 >> 12) & 7];
4697 if(BIT_B(word2)) /* signed */
4699 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4700 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4701 if((sint64)quotient != (sint64)((sint32)quotient))
4709 quotient = dividend / divisor;
4710 if(quotient > 0xffffffff)
4715 remainder = dividend % divisor;
4720 dividend = REG_D[(word2 >> 12) & 7];
4721 if(BIT_B(word2)) /* signed */
4723 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4724 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4728 quotient = dividend / divisor;
4729 remainder = dividend % divisor;
4733 REG_D[word2 & 7] = remainder;
4734 REG_D[(word2 >> 12) & 7] = quotient;
4736 FLAG_N = NFLAG_32(quotient);
4738 FLAG_V = VFLAG_CLEAR;
4739 FLAG_C = CFLAG_CLEAR;
4742 m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
4745 m68ki_exception_illegal(state);
4749 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4751 uint word2 = OPER_I_16(state);
4753 uint dividend_hi = REG_D[word2 & 7];
4754 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4757 uint dividend_neg = 0;
4758 uint divisor_neg = 0;
4764 /* quad / long : long quotient, long remainder */
4767 if(BIT_B(word2)) /* signed */
4769 /* special case in signed divide */
4770 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4772 REG_D[word2 & 7] = 0;
4773 REG_D[(word2 >> 12) & 7] = 0x80000000;
4776 FLAG_Z = ZFLAG_CLEAR;
4777 FLAG_V = VFLAG_CLEAR;
4778 FLAG_C = CFLAG_CLEAR;
4781 if(GET_MSB_32(dividend_hi))
4784 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4785 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4787 if(GET_MSB_32(divisor))
4790 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4795 /* if the upper long is greater than the divisor, we're overflowing. */
4796 if(dividend_hi >= divisor)
4802 for(i = 31; i >= 0; i--)
4805 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4806 if(remainder >= divisor)
4808 remainder -= divisor;
4812 for(i = 31; i >= 0; i--)
4815 overflow = GET_MSB_32(remainder);
4816 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4817 if(remainder >= divisor || overflow)
4819 remainder -= divisor;
4824 if(BIT_B(word2)) /* signed */
4826 if(quotient > 0x7fffffff)
4833 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4834 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4837 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4840 REG_D[word2 & 7] = remainder;
4841 REG_D[(word2 >> 12) & 7] = quotient;
4843 FLAG_N = NFLAG_32(quotient);
4845 FLAG_V = VFLAG_CLEAR;
4846 FLAG_C = CFLAG_CLEAR;
4850 /* long / long: long quotient, maybe long remainder */
4851 if(BIT_B(word2)) /* signed */
4853 /* Special case in divide */
4854 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4857 FLAG_Z = ZFLAG_CLEAR;
4858 FLAG_V = VFLAG_CLEAR;
4859 FLAG_C = CFLAG_CLEAR;
4860 REG_D[(word2 >> 12) & 7] = 0x80000000;
4861 REG_D[word2 & 7] = 0;
4864 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4865 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4869 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4870 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4873 FLAG_N = NFLAG_32(quotient);
4875 FLAG_V = VFLAG_CLEAR;
4876 FLAG_C = CFLAG_CLEAR;
4879 m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
4882 m68ki_exception_illegal(state);
4888 M68KMAKE_OP(divl, 32, ., .)
4892 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4894 uint word2 = OPER_I_16(state);
4895 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
4896 uint64 dividend = 0;
4897 uint64 quotient = 0;
4898 uint64 remainder = 0;
4902 if(BIT_A(word2)) /* 64 bit */
4904 dividend = REG_D[word2 & 7];
4906 dividend |= REG_D[(word2 >> 12) & 7];
4908 if(BIT_B(word2)) /* signed */
4910 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4911 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4912 if((sint64)quotient != (sint64)((sint32)quotient))
4920 quotient = dividend / divisor;
4921 if(quotient > 0xffffffff)
4926 remainder = dividend % divisor;
4931 dividend = REG_D[(word2 >> 12) & 7];
4932 if(BIT_B(word2)) /* signed */
4934 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4935 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4939 quotient = dividend / divisor;
4940 remainder = dividend % divisor;
4944 REG_D[word2 & 7] = remainder;
4945 REG_D[(word2 >> 12) & 7] = quotient;
4947 FLAG_N = NFLAG_32(quotient);
4949 FLAG_V = VFLAG_CLEAR;
4950 FLAG_C = CFLAG_CLEAR;
4953 m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
4956 m68ki_exception_illegal(state);
4960 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4962 uint word2 = OPER_I_16(state);
4963 uint divisor = M68KMAKE_GET_OPER_AY_32;
4964 uint dividend_hi = REG_D[word2 & 7];
4965 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4968 uint dividend_neg = 0;
4969 uint divisor_neg = 0;
4975 /* quad / long : long quotient, long remainder */
4978 if(BIT_B(word2)) /* signed */
4980 /* special case in signed divide */
4981 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4983 REG_D[word2 & 7] = 0;
4984 REG_D[(word2 >> 12) & 7] = 0x80000000;
4987 FLAG_Z = ZFLAG_CLEAR;
4988 FLAG_V = VFLAG_CLEAR;
4989 FLAG_C = CFLAG_CLEAR;
4992 if(GET_MSB_32(dividend_hi))
4995 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4996 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4998 if(GET_MSB_32(divisor))
5001 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
5006 /* if the upper long is greater than the divisor, we're overflowing. */
5007 if(dividend_hi >= divisor)
5013 for(i = 31; i >= 0; i--)
5016 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
5017 if(remainder >= divisor)
5019 remainder -= divisor;
5023 for(i = 31; i >= 0; i--)
5026 overflow = GET_MSB_32(remainder);
5027 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
5028 if(remainder >= divisor || overflow)
5030 remainder -= divisor;
5035 if(BIT_B(word2)) /* signed */
5037 if(quotient > 0x7fffffff)
5044 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
5045 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
5048 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
5051 REG_D[word2 & 7] = remainder;
5052 REG_D[(word2 >> 12) & 7] = quotient;
5054 FLAG_N = NFLAG_32(quotient);
5056 FLAG_V = VFLAG_CLEAR;
5057 FLAG_C = CFLAG_CLEAR;
5061 /* long / long: long quotient, maybe long remainder */
5062 if(BIT_B(word2)) /* signed */
5064 /* Special case in divide */
5065 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
5068 FLAG_Z = ZFLAG_CLEAR;
5069 FLAG_V = VFLAG_CLEAR;
5070 FLAG_C = CFLAG_CLEAR;
5071 REG_D[(word2 >> 12) & 7] = 0x80000000;
5072 REG_D[word2 & 7] = 0;
5075 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
5076 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
5080 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
5081 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
5084 FLAG_N = NFLAG_32(quotient);
5086 FLAG_V = VFLAG_CLEAR;
5087 FLAG_C = CFLAG_CLEAR;
5090 m68ki_exception_trap(state, EXCEPTION_ZERO_DIVIDE);
5093 m68ki_exception_illegal(state);
5099 M68KMAKE_OP(eor, 8, ., d)
5101 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
5103 FLAG_N = NFLAG_8(res);
5105 FLAG_C = CFLAG_CLEAR;
5106 FLAG_V = VFLAG_CLEAR;
5110 M68KMAKE_OP(eor, 8, ., .)
5112 uint ea = M68KMAKE_GET_EA_AY_8;
5113 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(state, ea));
5115 m68ki_write_8(state, ea, res);
5117 FLAG_N = NFLAG_8(res);
5119 FLAG_C = CFLAG_CLEAR;
5120 FLAG_V = VFLAG_CLEAR;
5124 M68KMAKE_OP(eor, 16, ., d)
5126 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
5128 FLAG_N = NFLAG_16(res);
5130 FLAG_C = CFLAG_CLEAR;
5131 FLAG_V = VFLAG_CLEAR;
5135 M68KMAKE_OP(eor, 16, ., .)
5137 uint ea = M68KMAKE_GET_EA_AY_16;
5138 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(state, ea));
5140 m68ki_write_16(state, ea, res);
5142 FLAG_N = NFLAG_16(res);
5144 FLAG_C = CFLAG_CLEAR;
5145 FLAG_V = VFLAG_CLEAR;
5149 M68KMAKE_OP(eor, 32, ., d)
5151 uint res = DY ^= DX;
5153 FLAG_N = NFLAG_32(res);
5155 FLAG_C = CFLAG_CLEAR;
5156 FLAG_V = VFLAG_CLEAR;
5160 M68KMAKE_OP(eor, 32, ., .)
5162 uint ea = M68KMAKE_GET_EA_AY_32;
5163 uint res = DX ^ m68ki_read_32(state, ea);
5165 m68ki_write_32(state, ea, res);
5167 FLAG_N = NFLAG_32(res);
5169 FLAG_C = CFLAG_CLEAR;
5170 FLAG_V = VFLAG_CLEAR;
5174 M68KMAKE_OP(eori, 8, ., d)
5176 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8(state));
5178 FLAG_N = NFLAG_8(res);
5180 FLAG_C = CFLAG_CLEAR;
5181 FLAG_V = VFLAG_CLEAR;
5185 M68KMAKE_OP(eori, 8, ., .)
5187 uint src = OPER_I_8(state);
5188 uint ea = M68KMAKE_GET_EA_AY_8;
5189 uint res = src ^ m68ki_read_8(state, ea);
5191 m68ki_write_8(state, ea, res);
5193 FLAG_N = NFLAG_8(res);
5195 FLAG_C = CFLAG_CLEAR;
5196 FLAG_V = VFLAG_CLEAR;
5200 M68KMAKE_OP(eori, 16, ., d)
5202 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16(state));
5204 FLAG_N = NFLAG_16(res);
5206 FLAG_C = CFLAG_CLEAR;
5207 FLAG_V = VFLAG_CLEAR;
5211 M68KMAKE_OP(eori, 16, ., .)
5213 uint src = OPER_I_16(state);
5214 uint ea = M68KMAKE_GET_EA_AY_16;
5215 uint res = src ^ m68ki_read_16(state, ea);
5217 m68ki_write_16(state, ea, res);
5219 FLAG_N = NFLAG_16(res);
5221 FLAG_C = CFLAG_CLEAR;
5222 FLAG_V = VFLAG_CLEAR;
5226 M68KMAKE_OP(eori, 32, ., d)
5228 uint res = DY ^= OPER_I_32(state);
5230 FLAG_N = NFLAG_32(res);
5232 FLAG_C = CFLAG_CLEAR;
5233 FLAG_V = VFLAG_CLEAR;
5237 M68KMAKE_OP(eori, 32, ., .)
5239 uint src = OPER_I_32(state);
5240 uint ea = M68KMAKE_GET_EA_AY_32;
5241 uint res = src ^ m68ki_read_32(state, ea);
5243 m68ki_write_32(state, ea, res);
5245 FLAG_N = NFLAG_32(res);
5247 FLAG_C = CFLAG_CLEAR;
5248 FLAG_V = VFLAG_CLEAR;
5252 M68KMAKE_OP(eori, 16, toc, .)
5254 m68ki_set_ccr(state, m68ki_get_ccr(state) ^ OPER_I_8(state));
5258 M68KMAKE_OP(eori, 16, tos, .)
5262 uint src = OPER_I_16(state);
5263 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5264 m68ki_set_sr(state, m68ki_get_sr() ^ src);
5267 m68ki_exception_privilege_violation(state);
5271 M68KMAKE_OP(exg, 32, dd, .)
5281 M68KMAKE_OP(exg, 32, aa, .)
5291 M68KMAKE_OP(exg, 32, da, .)
5301 M68KMAKE_OP(ext, 16, ., .)
5305 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
5307 FLAG_N = NFLAG_16(*r_dst);
5308 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
5309 FLAG_V = VFLAG_CLEAR;
5310 FLAG_C = CFLAG_CLEAR;
5314 M68KMAKE_OP(ext, 32, ., .)
5318 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
5320 FLAG_N = NFLAG_32(*r_dst);
5322 FLAG_V = VFLAG_CLEAR;
5323 FLAG_C = CFLAG_CLEAR;
5327 M68KMAKE_OP(extb, 32, ., .)
5329 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5333 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
5335 FLAG_N = NFLAG_32(*r_dst);
5337 FLAG_V = VFLAG_CLEAR;
5338 FLAG_C = CFLAG_CLEAR;
5341 m68ki_exception_illegal(state);
5345 M68KMAKE_OP(illegal, 0, ., .)
5347 m68ki_exception_illegal(state);
5350 M68KMAKE_OP(jmp, 32, ., .)
5352 m68ki_jump(state, M68KMAKE_GET_EA_AY_32);
5353 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5357 M68KMAKE_OP(jsr, 32, ., .)
5359 uint ea = M68KMAKE_GET_EA_AY_32;
5360 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5361 m68ki_push_32(state, REG_PC);
5362 m68ki_jump(state, ea);
5366 M68KMAKE_OP(lea, 32, ., .)
5368 AX = M68KMAKE_GET_EA_AY_32;
5372 M68KMAKE_OP(link, 16, ., a7)
5375 m68ki_write_32(state, REG_A[7], REG_A[7]);
5376 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state)));
5380 M68KMAKE_OP(link, 16, ., .)
5384 m68ki_push_32(state, *r_dst);
5386 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state)));
5390 M68KMAKE_OP(link, 32, ., a7)
5392 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5395 m68ki_write_32(state, REG_A[7], REG_A[7]);
5396 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(state));
5399 m68ki_exception_illegal(state);
5403 M68KMAKE_OP(link, 32, ., .)
5405 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5409 m68ki_push_32(state, *r_dst);
5411 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(state));
5414 m68ki_exception_illegal(state);
5418 M68KMAKE_OP(lsr, 8, s, .)
5421 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5422 uint src = MASK_OUT_ABOVE_8(*r_dst);
5423 uint res = src >> shift;
5426 USE_CYCLES(shift<<CYC_SHIFT);
5428 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5430 FLAG_N = NFLAG_CLEAR;
5432 FLAG_X = FLAG_C = src << (9-shift);
5433 FLAG_V = VFLAG_CLEAR;
5437 M68KMAKE_OP(lsr, 16, s, .)
5440 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5441 uint src = MASK_OUT_ABOVE_16(*r_dst);
5442 uint res = src >> shift;
5445 USE_CYCLES(shift<<CYC_SHIFT);
5447 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5449 FLAG_N = NFLAG_CLEAR;
5451 FLAG_X = FLAG_C = src << (9-shift);
5452 FLAG_V = VFLAG_CLEAR;
5456 M68KMAKE_OP(lsr, 32, s, .)
5459 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5461 uint res = src >> shift;
5464 USE_CYCLES(shift<<CYC_SHIFT);
5468 FLAG_N = NFLAG_CLEAR;
5470 FLAG_X = FLAG_C = src << (9-shift);
5471 FLAG_V = VFLAG_CLEAR;
5475 M68KMAKE_OP(lsr, 8, r, .)
5478 uint shift = DX & 0x3f;
5479 uint src = MASK_OUT_ABOVE_8(*r_dst);
5480 uint res = src >> shift;
5484 USE_CYCLES(shift<<CYC_SHIFT);
5488 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5489 FLAG_X = FLAG_C = src << (9-shift);
5490 FLAG_N = NFLAG_CLEAR;
5492 FLAG_V = VFLAG_CLEAR;
5496 *r_dst &= 0xffffff00;
5497 FLAG_X = XFLAG_CLEAR;
5498 FLAG_C = CFLAG_CLEAR;
5499 FLAG_N = NFLAG_CLEAR;
5501 FLAG_V = VFLAG_CLEAR;
5505 FLAG_C = CFLAG_CLEAR;
5506 FLAG_N = NFLAG_8(src);
5508 FLAG_V = VFLAG_CLEAR;
5512 M68KMAKE_OP(lsr, 16, r, .)
5515 uint shift = DX & 0x3f;
5516 uint src = MASK_OUT_ABOVE_16(*r_dst);
5517 uint res = src >> shift;
5521 USE_CYCLES(shift<<CYC_SHIFT);
5525 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5526 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5527 FLAG_N = NFLAG_CLEAR;
5529 FLAG_V = VFLAG_CLEAR;
5533 *r_dst &= 0xffff0000;
5534 FLAG_X = XFLAG_CLEAR;
5535 FLAG_C = CFLAG_CLEAR;
5536 FLAG_N = NFLAG_CLEAR;
5538 FLAG_V = VFLAG_CLEAR;
5542 FLAG_C = CFLAG_CLEAR;
5543 FLAG_N = NFLAG_16(src);
5545 FLAG_V = VFLAG_CLEAR;
5549 M68KMAKE_OP(lsr, 32, r, .)
5552 uint shift = DX & 0x3f;
5554 uint res = src >> shift;
5558 USE_CYCLES(shift<<CYC_SHIFT);
5563 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5564 FLAG_N = NFLAG_CLEAR;
5566 FLAG_V = VFLAG_CLEAR;
5571 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
5572 FLAG_N = NFLAG_CLEAR;
5574 FLAG_V = VFLAG_CLEAR;
5578 FLAG_C = CFLAG_CLEAR;
5579 FLAG_N = NFLAG_32(src);
5581 FLAG_V = VFLAG_CLEAR;
5585 M68KMAKE_OP(lsr, 16, ., .)
5587 uint ea = M68KMAKE_GET_EA_AY_16;
5588 uint src = m68ki_read_16(state, ea);
5589 uint res = src >> 1;
5591 m68ki_write_16(state, ea, res);
5593 FLAG_N = NFLAG_CLEAR;
5595 FLAG_C = FLAG_X = src << 8;
5596 FLAG_V = VFLAG_CLEAR;
5600 M68KMAKE_OP(lsl, 8, s, .)
5603 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5604 uint src = MASK_OUT_ABOVE_8(*r_dst);
5605 uint res = MASK_OUT_ABOVE_8(src << shift);
5608 USE_CYCLES(shift<<CYC_SHIFT);
5610 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5612 FLAG_N = NFLAG_8(res);
5614 FLAG_X = FLAG_C = src << shift;
5615 FLAG_V = VFLAG_CLEAR;
5619 M68KMAKE_OP(lsl, 16, s, .)
5622 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5623 uint src = MASK_OUT_ABOVE_16(*r_dst);
5624 uint res = MASK_OUT_ABOVE_16(src << shift);
5627 USE_CYCLES(shift<<CYC_SHIFT);
5629 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5631 FLAG_N = NFLAG_16(res);
5633 FLAG_X = FLAG_C = src >> (8-shift);
5634 FLAG_V = VFLAG_CLEAR;
5638 M68KMAKE_OP(lsl, 32, s, .)
5641 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5643 uint res = MASK_OUT_ABOVE_32(src << shift);
5646 USE_CYCLES(shift<<CYC_SHIFT);
5650 FLAG_N = NFLAG_32(res);
5652 FLAG_X = FLAG_C = src >> (24-shift);
5653 FLAG_V = VFLAG_CLEAR;
5657 M68KMAKE_OP(lsl, 8, r, .)
5660 uint shift = DX & 0x3f;
5661 uint src = MASK_OUT_ABOVE_8(*r_dst);
5662 uint res = MASK_OUT_ABOVE_8(src << shift);
5666 USE_CYCLES(shift<<CYC_SHIFT);
5670 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5671 FLAG_X = FLAG_C = src << shift;
5672 FLAG_N = NFLAG_8(res);
5674 FLAG_V = VFLAG_CLEAR;
5678 *r_dst &= 0xffffff00;
5679 FLAG_X = XFLAG_CLEAR;
5680 FLAG_C = CFLAG_CLEAR;
5681 FLAG_N = NFLAG_CLEAR;
5683 FLAG_V = VFLAG_CLEAR;
5687 FLAG_C = CFLAG_CLEAR;
5688 FLAG_N = NFLAG_8(src);
5690 FLAG_V = VFLAG_CLEAR;
5694 M68KMAKE_OP(lsl, 16, r, .)
5697 uint shift = DX & 0x3f;
5698 uint src = MASK_OUT_ABOVE_16(*r_dst);
5699 uint res = MASK_OUT_ABOVE_16(src << shift);
5703 USE_CYCLES(shift<<CYC_SHIFT);
5707 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5708 FLAG_X = FLAG_C = (src << shift) >> 8;
5709 FLAG_N = NFLAG_16(res);
5711 FLAG_V = VFLAG_CLEAR;
5715 *r_dst &= 0xffff0000;
5716 FLAG_X = XFLAG_CLEAR;
5717 FLAG_C = CFLAG_CLEAR;
5718 FLAG_N = NFLAG_CLEAR;
5720 FLAG_V = VFLAG_CLEAR;
5724 FLAG_C = CFLAG_CLEAR;
5725 FLAG_N = NFLAG_16(src);
5727 FLAG_V = VFLAG_CLEAR;
5731 M68KMAKE_OP(lsl, 32, r, .)
5734 uint shift = DX & 0x3f;
5736 uint res = MASK_OUT_ABOVE_32(src << shift);
5740 USE_CYCLES(shift<<CYC_SHIFT);
5745 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
5746 FLAG_N = NFLAG_32(res);
5748 FLAG_V = VFLAG_CLEAR;
5753 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
5754 FLAG_N = NFLAG_CLEAR;
5756 FLAG_V = VFLAG_CLEAR;
5760 FLAG_C = CFLAG_CLEAR;
5761 FLAG_N = NFLAG_32(src);
5763 FLAG_V = VFLAG_CLEAR;
5767 M68KMAKE_OP(lsl, 16, ., .)
5769 uint ea = M68KMAKE_GET_EA_AY_16;
5770 uint src = m68ki_read_16(state, ea);
5771 uint res = MASK_OUT_ABOVE_16(src << 1);
5773 m68ki_write_16(state, ea, res);
5775 FLAG_N = NFLAG_16(res);
5777 FLAG_X = FLAG_C = src >> 7;
5778 FLAG_V = VFLAG_CLEAR;
5782 M68KMAKE_OP(move, 8, d, d)
5784 uint res = MASK_OUT_ABOVE_8(DY);
5787 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5789 FLAG_N = NFLAG_8(res);
5791 FLAG_V = VFLAG_CLEAR;
5792 FLAG_C = CFLAG_CLEAR;
5796 M68KMAKE_OP(move, 8, d, .)
5798 uint res = M68KMAKE_GET_OPER_AY_8;
5801 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5803 FLAG_N = NFLAG_8(res);
5805 FLAG_V = VFLAG_CLEAR;
5806 FLAG_C = CFLAG_CLEAR;
5810 M68KMAKE_OP(move, 8, ai, d)
5812 uint res = MASK_OUT_ABOVE_8(DY);
5813 uint ea = EA_AX_AI_8();
5815 m68ki_write_8(state, ea, res);
5817 FLAG_N = NFLAG_8(res);
5819 FLAG_V = VFLAG_CLEAR;
5820 FLAG_C = CFLAG_CLEAR;
5824 M68KMAKE_OP(move, 8, ai, .)
5826 uint res = M68KMAKE_GET_OPER_AY_8;
5827 uint ea = EA_AX_AI_8();
5829 m68ki_write_8(state, ea, res);
5831 FLAG_N = NFLAG_8(res);
5833 FLAG_V = VFLAG_CLEAR;
5834 FLAG_C = CFLAG_CLEAR;
5838 M68KMAKE_OP(move, 8, pi7, d)
5840 uint res = MASK_OUT_ABOVE_8(DY);
5841 uint ea = EA_A7_PI_8();
5843 m68ki_write_8(state, ea, res);
5845 FLAG_N = NFLAG_8(res);
5847 FLAG_V = VFLAG_CLEAR;
5848 FLAG_C = CFLAG_CLEAR;
5852 M68KMAKE_OP(move, 8, pi, d)
5854 uint res = MASK_OUT_ABOVE_8(DY);
5855 uint ea = EA_AX_PI_8();
5857 m68ki_write_8(state, ea, res);
5859 FLAG_N = NFLAG_8(res);
5861 FLAG_V = VFLAG_CLEAR;
5862 FLAG_C = CFLAG_CLEAR;
5866 M68KMAKE_OP(move, 8, pi7, .)
5868 uint res = M68KMAKE_GET_OPER_AY_8;
5869 uint ea = EA_A7_PI_8();
5871 m68ki_write_8(state, ea, res);
5873 FLAG_N = NFLAG_8(res);
5875 FLAG_V = VFLAG_CLEAR;
5876 FLAG_C = CFLAG_CLEAR;
5880 M68KMAKE_OP(move, 8, pi, .)
5882 uint res = M68KMAKE_GET_OPER_AY_8;
5883 uint ea = EA_AX_PI_8();
5885 m68ki_write_8(state, ea, res);
5887 FLAG_N = NFLAG_8(res);
5889 FLAG_V = VFLAG_CLEAR;
5890 FLAG_C = CFLAG_CLEAR;
5894 M68KMAKE_OP(move, 8, pd7, d)
5896 uint res = MASK_OUT_ABOVE_8(DY);
5897 uint ea = EA_A7_PD_8();
5899 m68ki_write_8(state, ea, res);
5901 FLAG_N = NFLAG_8(res);
5903 FLAG_V = VFLAG_CLEAR;
5904 FLAG_C = CFLAG_CLEAR;
5908 M68KMAKE_OP(move, 8, pd, d)
5910 uint res = MASK_OUT_ABOVE_8(DY);
5911 uint ea = EA_AX_PD_8();
5913 m68ki_write_8(state, ea, res);
5915 FLAG_N = NFLAG_8(res);
5917 FLAG_V = VFLAG_CLEAR;
5918 FLAG_C = CFLAG_CLEAR;
5922 M68KMAKE_OP(move, 8, pd7, .)
5924 uint res = M68KMAKE_GET_OPER_AY_8;
5925 uint ea = EA_A7_PD_8();
5927 m68ki_write_8(state, ea, res);
5929 FLAG_N = NFLAG_8(res);
5931 FLAG_V = VFLAG_CLEAR;
5932 FLAG_C = CFLAG_CLEAR;
5936 M68KMAKE_OP(move, 8, pd, .)
5938 uint res = M68KMAKE_GET_OPER_AY_8;
5939 uint ea = EA_AX_PD_8();
5941 m68ki_write_8(state, ea, res);
5943 FLAG_N = NFLAG_8(res);
5945 FLAG_V = VFLAG_CLEAR;
5946 FLAG_C = CFLAG_CLEAR;
5950 M68KMAKE_OP(move, 8, di, d)
5952 uint res = MASK_OUT_ABOVE_8(DY);
5953 uint ea = EA_AX_DI_8();
5955 m68ki_write_8(state, ea, res);
5957 FLAG_N = NFLAG_8(res);
5959 FLAG_V = VFLAG_CLEAR;
5960 FLAG_C = CFLAG_CLEAR;
5964 M68KMAKE_OP(move, 8, di, .)
5966 uint res = M68KMAKE_GET_OPER_AY_8;
5967 uint ea = EA_AX_DI_8();
5969 m68ki_write_8(state, ea, res);
5971 FLAG_N = NFLAG_8(res);
5973 FLAG_V = VFLAG_CLEAR;
5974 FLAG_C = CFLAG_CLEAR;
5978 M68KMAKE_OP(move, 8, ix, d)
5980 uint res = MASK_OUT_ABOVE_8(DY);
5981 uint ea = EA_AX_IX_8();
5983 m68ki_write_8(state, ea, res);
5985 FLAG_N = NFLAG_8(res);
5987 FLAG_V = VFLAG_CLEAR;
5988 FLAG_C = CFLAG_CLEAR;
5992 M68KMAKE_OP(move, 8, ix, .)
5994 uint res = M68KMAKE_GET_OPER_AY_8;
5995 uint ea = EA_AX_IX_8();
5997 m68ki_write_8(state, ea, res);
5999 FLAG_N = NFLAG_8(res);
6001 FLAG_V = VFLAG_CLEAR;
6002 FLAG_C = CFLAG_CLEAR;
6006 M68KMAKE_OP(move, 8, aw, d)
6008 uint res = MASK_OUT_ABOVE_8(DY);
6009 uint ea = EA_AW_8();
6011 m68ki_write_8(state, ea, res);
6013 FLAG_N = NFLAG_8(res);
6015 FLAG_V = VFLAG_CLEAR;
6016 FLAG_C = CFLAG_CLEAR;
6020 M68KMAKE_OP(move, 8, aw, .)
6022 uint res = M68KMAKE_GET_OPER_AY_8;
6023 uint ea = EA_AW_8();
6025 m68ki_write_8(state, ea, res);
6027 FLAG_N = NFLAG_8(res);
6029 FLAG_V = VFLAG_CLEAR;
6030 FLAG_C = CFLAG_CLEAR;
6034 M68KMAKE_OP(move, 8, al, d)
6036 uint res = MASK_OUT_ABOVE_8(DY);
6037 uint ea = EA_AL_8();
6039 m68ki_write_8(state, ea, res);
6041 FLAG_N = NFLAG_8(res);
6043 FLAG_V = VFLAG_CLEAR;
6044 FLAG_C = CFLAG_CLEAR;
6048 M68KMAKE_OP(move, 8, al, .)
6050 uint res = M68KMAKE_GET_OPER_AY_8;
6051 uint ea = EA_AL_8();
6053 m68ki_write_8(state, ea, res);
6055 FLAG_N = NFLAG_8(res);
6057 FLAG_V = VFLAG_CLEAR;
6058 FLAG_C = CFLAG_CLEAR;
6062 M68KMAKE_OP(move, 16, d, d)
6064 uint res = MASK_OUT_ABOVE_16(DY);
6067 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
6069 FLAG_N = NFLAG_16(res);
6071 FLAG_V = VFLAG_CLEAR;
6072 FLAG_C = CFLAG_CLEAR;
6076 M68KMAKE_OP(move, 16, d, a)
6078 uint res = MASK_OUT_ABOVE_16(AY);
6081 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
6083 FLAG_N = NFLAG_16(res);
6085 FLAG_V = VFLAG_CLEAR;
6086 FLAG_C = CFLAG_CLEAR;
6090 M68KMAKE_OP(move, 16, d, .)
6092 uint res = M68KMAKE_GET_OPER_AY_16;
6095 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
6097 FLAG_N = NFLAG_16(res);
6099 FLAG_V = VFLAG_CLEAR;
6100 FLAG_C = CFLAG_CLEAR;
6104 M68KMAKE_OP(move, 16, ai, d)
6106 uint res = MASK_OUT_ABOVE_16(DY);
6107 uint ea = EA_AX_AI_16();
6109 m68ki_write_16(state, ea, res);
6111 FLAG_N = NFLAG_16(res);
6113 FLAG_V = VFLAG_CLEAR;
6114 FLAG_C = CFLAG_CLEAR;
6118 M68KMAKE_OP(move, 16, ai, a)
6120 uint res = MASK_OUT_ABOVE_16(AY);
6121 uint ea = EA_AX_AI_16();
6123 m68ki_write_16(state, ea, res);
6125 FLAG_N = NFLAG_16(res);
6127 FLAG_V = VFLAG_CLEAR;
6128 FLAG_C = CFLAG_CLEAR;
6132 M68KMAKE_OP(move, 16, ai, .)
6134 uint res = M68KMAKE_GET_OPER_AY_16;
6135 uint ea = EA_AX_AI_16();
6137 m68ki_write_16(state, ea, res);
6139 FLAG_N = NFLAG_16(res);
6141 FLAG_V = VFLAG_CLEAR;
6142 FLAG_C = CFLAG_CLEAR;
6146 M68KMAKE_OP(move, 16, pi, d)
6148 uint res = MASK_OUT_ABOVE_16(DY);
6149 uint ea = EA_AX_PI_16();
6151 m68ki_write_16(state, ea, res);
6153 FLAG_N = NFLAG_16(res);
6155 FLAG_V = VFLAG_CLEAR;
6156 FLAG_C = CFLAG_CLEAR;
6160 M68KMAKE_OP(move, 16, pi, a)
6162 uint res = MASK_OUT_ABOVE_16(AY);
6163 uint ea = EA_AX_PI_16();
6165 m68ki_write_16(state, ea, res);
6167 FLAG_N = NFLAG_16(res);
6169 FLAG_V = VFLAG_CLEAR;
6170 FLAG_C = CFLAG_CLEAR;
6174 M68KMAKE_OP(move, 16, pi, .)
6176 uint res = M68KMAKE_GET_OPER_AY_16;
6177 uint ea = EA_AX_PI_16();
6179 m68ki_write_16(state, ea, res);
6181 FLAG_N = NFLAG_16(res);
6183 FLAG_V = VFLAG_CLEAR;
6184 FLAG_C = CFLAG_CLEAR;
6188 M68KMAKE_OP(move, 16, pd, d)
6190 uint res = MASK_OUT_ABOVE_16(DY);
6191 uint ea = EA_AX_PD_16();
6193 m68ki_write_16(state, ea, res);
6195 FLAG_N = NFLAG_16(res);
6197 FLAG_V = VFLAG_CLEAR;
6198 FLAG_C = CFLAG_CLEAR;
6202 M68KMAKE_OP(move, 16, pd, a)
6204 uint res = MASK_OUT_ABOVE_16(AY);
6205 uint ea = EA_AX_PD_16();
6207 m68ki_write_16(state, ea, res);
6209 FLAG_N = NFLAG_16(res);
6211 FLAG_V = VFLAG_CLEAR;
6212 FLAG_C = CFLAG_CLEAR;
6216 M68KMAKE_OP(move, 16, pd, .)
6218 uint res = M68KMAKE_GET_OPER_AY_16;
6219 uint ea = EA_AX_PD_16();
6221 m68ki_write_16(state, ea, res);
6223 FLAG_N = NFLAG_16(res);
6225 FLAG_V = VFLAG_CLEAR;
6226 FLAG_C = CFLAG_CLEAR;
6230 M68KMAKE_OP(move, 16, di, d)
6232 uint res = MASK_OUT_ABOVE_16(DY);
6233 uint ea = EA_AX_DI_16();
6235 m68ki_write_16(state, ea, res);
6237 FLAG_N = NFLAG_16(res);
6239 FLAG_V = VFLAG_CLEAR;
6240 FLAG_C = CFLAG_CLEAR;
6244 M68KMAKE_OP(move, 16, di, a)
6246 uint res = MASK_OUT_ABOVE_16(AY);
6247 uint ea = EA_AX_DI_16();
6249 m68ki_write_16(state, ea, res);
6251 FLAG_N = NFLAG_16(res);
6253 FLAG_V = VFLAG_CLEAR;
6254 FLAG_C = CFLAG_CLEAR;
6258 M68KMAKE_OP(move, 16, di, .)
6260 uint res = M68KMAKE_GET_OPER_AY_16;
6261 uint ea = EA_AX_DI_16();
6263 m68ki_write_16(state, ea, res);
6265 FLAG_N = NFLAG_16(res);
6267 FLAG_V = VFLAG_CLEAR;
6268 FLAG_C = CFLAG_CLEAR;
6272 M68KMAKE_OP(move, 16, ix, d)
6274 uint res = MASK_OUT_ABOVE_16(DY);
6275 uint ea = EA_AX_IX_16();
6277 m68ki_write_16(state, ea, res);
6279 FLAG_N = NFLAG_16(res);
6281 FLAG_V = VFLAG_CLEAR;
6282 FLAG_C = CFLAG_CLEAR;
6286 M68KMAKE_OP(move, 16, ix, a)
6288 uint res = MASK_OUT_ABOVE_16(AY);
6289 uint ea = EA_AX_IX_16();
6291 m68ki_write_16(state, ea, res);
6293 FLAG_N = NFLAG_16(res);
6295 FLAG_V = VFLAG_CLEAR;
6296 FLAG_C = CFLAG_CLEAR;
6300 M68KMAKE_OP(move, 16, ix, .)
6302 uint res = M68KMAKE_GET_OPER_AY_16;
6303 uint ea = EA_AX_IX_16();
6305 m68ki_write_16(state, ea, res);
6307 FLAG_N = NFLAG_16(res);
6309 FLAG_V = VFLAG_CLEAR;
6310 FLAG_C = CFLAG_CLEAR;
6314 M68KMAKE_OP(move, 16, aw, d)
6316 uint res = MASK_OUT_ABOVE_16(DY);
6317 uint ea = EA_AW_16();
6319 m68ki_write_16(state, ea, res);
6321 FLAG_N = NFLAG_16(res);
6323 FLAG_V = VFLAG_CLEAR;
6324 FLAG_C = CFLAG_CLEAR;
6328 M68KMAKE_OP(move, 16, aw, a)
6330 uint res = MASK_OUT_ABOVE_16(AY);
6331 uint ea = EA_AW_16();
6333 m68ki_write_16(state, ea, res);
6335 FLAG_N = NFLAG_16(res);
6337 FLAG_V = VFLAG_CLEAR;
6338 FLAG_C = CFLAG_CLEAR;
6342 M68KMAKE_OP(move, 16, aw, .)
6344 uint res = M68KMAKE_GET_OPER_AY_16;
6345 uint ea = EA_AW_16();
6347 m68ki_write_16(state, ea, res);
6349 FLAG_N = NFLAG_16(res);
6351 FLAG_V = VFLAG_CLEAR;
6352 FLAG_C = CFLAG_CLEAR;
6356 M68KMAKE_OP(move, 16, al, d)
6358 uint res = MASK_OUT_ABOVE_16(DY);
6359 uint ea = EA_AL_16();
6361 m68ki_write_16(state, ea, res);
6363 FLAG_N = NFLAG_16(res);
6365 FLAG_V = VFLAG_CLEAR;
6366 FLAG_C = CFLAG_CLEAR;
6370 M68KMAKE_OP(move, 16, al, a)
6372 uint res = MASK_OUT_ABOVE_16(AY);
6373 uint ea = EA_AL_16();
6375 m68ki_write_16(state, ea, res);
6377 FLAG_N = NFLAG_16(res);
6379 FLAG_V = VFLAG_CLEAR;
6380 FLAG_C = CFLAG_CLEAR;
6384 M68KMAKE_OP(move, 16, al, .)
6386 uint res = M68KMAKE_GET_OPER_AY_16;
6387 uint ea = EA_AL_16();
6389 m68ki_write_16(state, ea, res);
6391 FLAG_N = NFLAG_16(res);
6393 FLAG_V = VFLAG_CLEAR;
6394 FLAG_C = CFLAG_CLEAR;
6398 M68KMAKE_OP(move, 32, d, d)
6405 FLAG_N = NFLAG_32(res);
6407 FLAG_V = VFLAG_CLEAR;
6408 FLAG_C = CFLAG_CLEAR;
6412 M68KMAKE_OP(move, 32, d, a)
6419 FLAG_N = NFLAG_32(res);
6421 FLAG_V = VFLAG_CLEAR;
6422 FLAG_C = CFLAG_CLEAR;
6426 M68KMAKE_OP(move, 32, d, .)
6428 uint res = M68KMAKE_GET_OPER_AY_32;
6433 FLAG_N = NFLAG_32(res);
6435 FLAG_V = VFLAG_CLEAR;
6436 FLAG_C = CFLAG_CLEAR;
6440 M68KMAKE_OP(move, 32, ai, d)
6443 uint ea = EA_AX_AI_32();
6445 m68ki_write_32(state, ea, res);
6447 FLAG_N = NFLAG_32(res);
6449 FLAG_V = VFLAG_CLEAR;
6450 FLAG_C = CFLAG_CLEAR;
6454 M68KMAKE_OP(move, 32, ai, a)
6457 uint ea = EA_AX_AI_32();
6459 m68ki_write_32(state, ea, res);
6461 FLAG_N = NFLAG_32(res);
6463 FLAG_V = VFLAG_CLEAR;
6464 FLAG_C = CFLAG_CLEAR;
6468 M68KMAKE_OP(move, 32, ai, .)
6470 uint res = M68KMAKE_GET_OPER_AY_32;
6471 uint ea = EA_AX_AI_32();
6473 m68ki_write_32(state, ea, res);
6475 FLAG_N = NFLAG_32(res);
6477 FLAG_V = VFLAG_CLEAR;
6478 FLAG_C = CFLAG_CLEAR;
6482 M68KMAKE_OP(move, 32, pi, d)
6485 uint ea = EA_AX_PI_32();
6487 m68ki_write_32(state, ea, res);
6489 FLAG_N = NFLAG_32(res);
6491 FLAG_V = VFLAG_CLEAR;
6492 FLAG_C = CFLAG_CLEAR;
6496 M68KMAKE_OP(move, 32, pi, a)
6499 uint ea = EA_AX_PI_32();
6501 m68ki_write_32(state, ea, res);
6503 FLAG_N = NFLAG_32(res);
6505 FLAG_V = VFLAG_CLEAR;
6506 FLAG_C = CFLAG_CLEAR;
6510 M68KMAKE_OP(move, 32, pi, .)
6512 uint res = M68KMAKE_GET_OPER_AY_32;
6513 uint ea = EA_AX_PI_32();
6515 m68ki_write_32(state, ea, res);
6517 FLAG_N = NFLAG_32(res);
6519 FLAG_V = VFLAG_CLEAR;
6520 FLAG_C = CFLAG_CLEAR;
6524 M68KMAKE_OP(move, 32, pd, d)
6527 uint ea = EA_AX_PD_32();
6529 m68ki_write_16(state, ea+2, res & 0xFFFF );
6530 m68ki_write_16(state, ea, (res >> 16) & 0xFFFF );
6532 FLAG_N = NFLAG_32(res);
6534 FLAG_V = VFLAG_CLEAR;
6535 FLAG_C = CFLAG_CLEAR;
6539 M68KMAKE_OP(move, 32, pd, a)
6542 uint ea = EA_AX_PD_32();
6544 m68ki_write_16(state, ea+2, res & 0xFFFF );
6545 m68ki_write_16(state, ea, (res >> 16) & 0xFFFF );
6547 FLAG_N = NFLAG_32(res);
6549 FLAG_V = VFLAG_CLEAR;
6550 FLAG_C = CFLAG_CLEAR;
6554 M68KMAKE_OP(move, 32, pd, .)
6556 uint res = M68KMAKE_GET_OPER_AY_32;
6557 uint ea = EA_AX_PD_32();
6559 m68ki_write_16(state, ea+2, res & 0xFFFF );
6560 m68ki_write_16(state, ea, (res >> 16) & 0xFFFF );
6562 FLAG_N = NFLAG_32(res);
6564 FLAG_V = VFLAG_CLEAR;
6565 FLAG_C = CFLAG_CLEAR;
6569 M68KMAKE_OP(move, 32, di, d)
6572 uint ea = EA_AX_DI_32();
6574 m68ki_write_32(state, ea, res);
6576 FLAG_N = NFLAG_32(res);
6578 FLAG_V = VFLAG_CLEAR;
6579 FLAG_C = CFLAG_CLEAR;
6583 M68KMAKE_OP(move, 32, di, a)
6586 uint ea = EA_AX_DI_32();
6588 m68ki_write_32(state, ea, res);
6590 FLAG_N = NFLAG_32(res);
6592 FLAG_V = VFLAG_CLEAR;
6593 FLAG_C = CFLAG_CLEAR;
6597 M68KMAKE_OP(move, 32, di, .)
6599 uint res = M68KMAKE_GET_OPER_AY_32;
6600 uint ea = EA_AX_DI_32();
6602 m68ki_write_32(state, ea, res);
6604 FLAG_N = NFLAG_32(res);
6606 FLAG_V = VFLAG_CLEAR;
6607 FLAG_C = CFLAG_CLEAR;
6611 M68KMAKE_OP(move, 32, ix, d)
6614 uint ea = EA_AX_IX_32();
6616 m68ki_write_32(state, ea, res);
6618 FLAG_N = NFLAG_32(res);
6620 FLAG_V = VFLAG_CLEAR;
6621 FLAG_C = CFLAG_CLEAR;
6625 M68KMAKE_OP(move, 32, ix, a)
6628 uint ea = EA_AX_IX_32();
6630 m68ki_write_32(state, ea, res);
6632 FLAG_N = NFLAG_32(res);
6634 FLAG_V = VFLAG_CLEAR;
6635 FLAG_C = CFLAG_CLEAR;
6639 M68KMAKE_OP(move, 32, ix, .)
6641 uint res = M68KMAKE_GET_OPER_AY_32;
6642 uint ea = EA_AX_IX_32();
6644 m68ki_write_32(state, ea, res);
6646 FLAG_N = NFLAG_32(res);
6648 FLAG_V = VFLAG_CLEAR;
6649 FLAG_C = CFLAG_CLEAR;
6653 M68KMAKE_OP(move, 32, aw, d)
6656 uint ea = EA_AW_32();
6658 m68ki_write_32(state, ea, res);
6660 FLAG_N = NFLAG_32(res);
6662 FLAG_V = VFLAG_CLEAR;
6663 FLAG_C = CFLAG_CLEAR;
6667 M68KMAKE_OP(move, 32, aw, a)
6670 uint ea = EA_AW_32();
6672 m68ki_write_32(state, ea, res);
6674 FLAG_N = NFLAG_32(res);
6676 FLAG_V = VFLAG_CLEAR;
6677 FLAG_C = CFLAG_CLEAR;
6681 M68KMAKE_OP(move, 32, aw, .)
6683 uint res = M68KMAKE_GET_OPER_AY_32;
6684 uint ea = EA_AW_32();
6686 m68ki_write_32(state, ea, res);
6688 FLAG_N = NFLAG_32(res);
6690 FLAG_V = VFLAG_CLEAR;
6691 FLAG_C = CFLAG_CLEAR;
6695 M68KMAKE_OP(move, 32, al, d)
6698 uint ea = EA_AL_32();
6700 m68ki_write_32(state, ea, res);
6702 FLAG_N = NFLAG_32(res);
6704 FLAG_V = VFLAG_CLEAR;
6705 FLAG_C = CFLAG_CLEAR;
6709 M68KMAKE_OP(move, 32, al, a)
6712 uint ea = EA_AL_32();
6714 m68ki_write_32(state, ea, res);
6716 FLAG_N = NFLAG_32(res);
6718 FLAG_V = VFLAG_CLEAR;
6719 FLAG_C = CFLAG_CLEAR;
6723 M68KMAKE_OP(move, 32, al, .)
6725 uint res = M68KMAKE_GET_OPER_AY_32;
6726 uint ea = EA_AL_32();
6728 m68ki_write_32(state, ea, res);
6730 FLAG_N = NFLAG_32(res);
6732 FLAG_V = VFLAG_CLEAR;
6733 FLAG_C = CFLAG_CLEAR;
6737 M68KMAKE_OP(movea, 16, ., d)
6739 AX = MAKE_INT_16(DY);
6743 M68KMAKE_OP(movea, 16, ., a)
6745 AX = MAKE_INT_16(AY);
6749 M68KMAKE_OP(movea, 16, ., .)
6751 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
6755 M68KMAKE_OP(movea, 32, ., d)
6761 M68KMAKE_OP(movea, 32, ., a)
6767 M68KMAKE_OP(movea, 32, ., .)
6769 AX = M68KMAKE_GET_OPER_AY_32;
6773 M68KMAKE_OP(move, 16, frc, d)
6775 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6777 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr(state);
6780 m68ki_exception_illegal(state);
6784 M68KMAKE_OP(move, 16, frc, .)
6786 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6788 m68ki_write_16(state, M68KMAKE_GET_EA_AY_16, m68ki_get_ccr(state));
6791 m68ki_exception_illegal(state);
6795 M68KMAKE_OP(move, 16, toc, d)
6797 m68ki_set_ccr(state, DY);
6801 M68KMAKE_OP(move, 16, toc, .)
6803 m68ki_set_ccr(state, M68KMAKE_GET_OPER_AY_16);
6807 M68KMAKE_OP(move, 16, frs, d)
6809 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6811 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
6814 m68ki_exception_privilege_violation(state);
6818 M68KMAKE_OP(move, 16, frs, .)
6820 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6822 uint ea = M68KMAKE_GET_EA_AY_16;
6823 m68ki_write_16(state, ea, m68ki_get_sr());
6826 m68ki_exception_privilege_violation(state);
6830 M68KMAKE_OP(move, 16, tos, d)
6834 m68ki_set_sr(state, DY);
6837 m68ki_exception_privilege_violation(state);
6841 M68KMAKE_OP(move, 16, tos, .)
6845 uint new_sr = M68KMAKE_GET_OPER_AY_16;
6846 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6847 m68ki_set_sr(state, new_sr);
6850 m68ki_exception_privilege_violation(state);
6854 M68KMAKE_OP(move, 32, fru, .)
6861 m68ki_exception_privilege_violation(state);
6865 M68KMAKE_OP(move, 32, tou, .)
6869 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6873 m68ki_exception_privilege_violation(state);
6877 M68KMAKE_OP(movec, 32, cr, .)
6879 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6883 uint word2 = OPER_I_16(state);
6885 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6886 switch (word2 & 0xfff)
6888 case 0x000: /* SFC */
6889 REG_DA[(word2 >> 12) & 15] = REG_SFC;
6891 case 0x001: /* DFC */
6892 REG_DA[(word2 >> 12) & 15] = REG_DFC;
6894 case 0x002: /* CACR */
6895 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6897 REG_DA[(word2 >> 12) & 15] = REG_CACR;
6901 case 0x800: /* USP */
6902 REG_DA[(word2 >> 12) & 15] = REG_USP;
6904 case 0x801: /* VBR */
6905 REG_DA[(word2 >> 12) & 15] = REG_VBR;
6907 case 0x802: /* CAAR */
6908 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6910 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
6913 m68ki_exception_illegal(state);
6915 case 0x803: /* MSP */
6916 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6918 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
6921 m68ki_exception_illegal(state);
6923 case 0x804: /* ISP */
6924 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6926 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
6929 m68ki_exception_illegal(state);
6931 case 0x003: /* TC */
6932 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6934 REG_DA[(word2 >> 12) & 15] = state->mmu_tc;
6937 m68ki_exception_illegal(state);
6939 case 0x004: /* ITT0 */
6940 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6942 REG_DA[(word2 >> 12) & 15] = state->mmu_itt0;
6945 m68ki_exception_illegal(state);
6947 case 0x005: /* ITT1 */
6948 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6950 REG_DA[(word2 >> 12) & 15] = state->mmu_itt1;
6953 m68ki_exception_illegal(state);
6955 case 0x006: /* DTT0 */
6956 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6958 REG_DA[(word2 >> 12) & 15] = state->mmu_dtt0;
6961 m68ki_exception_illegal(state);
6963 case 0x007: /* DTT1 */
6964 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6966 REG_DA[(word2 >> 12) & 15] = state->mmu_dtt1;
6969 m68ki_exception_illegal(state);
6971 case 0x805: /* MMUSR */
6972 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6974 REG_DA[(word2 >> 12) & 15] = state->mmu_sr_040;
6977 m68ki_exception_illegal(state);
6979 case 0x806: /* URP */
6980 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6982 REG_DA[(word2 >> 12) & 15] = state->mmu_urp_aptr;
6985 m68ki_exception_illegal(state);
6987 case 0x807: /* SRP */
6988 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6990 REG_DA[(word2 >> 12) & 15] = state->mmu_srp_aptr;
6993 m68ki_exception_illegal(state);
6996 m68ki_exception_illegal(state);
7000 m68ki_exception_privilege_violation(state);
7003 m68ki_exception_illegal(state);
7007 M68KMAKE_OP(movec, 32, rc, .)
7009 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7013 uint word2 = OPER_I_16(state);
7015 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7016 switch (word2 & 0xfff)
7018 case 0x000: /* SFC */
7019 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
7021 case 0x001: /* DFC */
7022 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
7024 case 0x002: /* CACR */
7025 /* Only EC020 and later have CACR */
7026 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7028 /* 68030 can write all bits except 5-7, 040 can write all */
7029 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7031 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0xfffffffe; // Old I cache bit not working on 040
7033 else if (CPU_TYPE_IS_030_PLUS(CPU_TYPE))
7035 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0xff1f;
7039 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
7042 if (REG_CACR & (M68K_CACR_CI | M68K_CACR_CEI)) {
7043 m68ki_ic_clear(state);
7047 m68ki_exception_illegal(state);
7049 case 0x800: /* USP */
7050 REG_USP = REG_DA[(word2 >> 12) & 15];
7052 case 0x801: /* VBR */
7053 REG_VBR = REG_DA[(word2 >> 12) & 15];
7055 case 0x802: /* CAAR */
7056 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7058 REG_CAAR = REG_DA[(word2 >> 12) & 15];
7061 m68ki_exception_illegal(state);
7063 case 0x803: /* MSP */
7064 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7066 /* we are in supervisor mode so just check for M flag */
7069 REG_MSP = REG_DA[(word2 >> 12) & 15];
7072 REG_SP = REG_DA[(word2 >> 12) & 15];
7075 m68ki_exception_illegal(state);
7077 case 0x804: /* ISP */
7078 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7082 REG_SP = REG_DA[(word2 >> 12) & 15];
7085 REG_ISP = REG_DA[(word2 >> 12) & 15];
7088 m68ki_exception_illegal(state);
7090 case 0x003: /* TC */
7091 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7093 state->mmu_tc = REG_DA[(word2 >> 12) & 15];
7095 if (state->mmu_tc & 0x8000)
7097 state->pmmu_enabled = 1;
7101 state->pmmu_enabled = 0;
7105 m68ki_exception_illegal(state);
7107 case 0x004: /* ITT0 */
7108 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7110 state->mmu_itt0 = REG_DA[(word2 >> 12) & 15];
7113 m68ki_exception_illegal(state);
7115 case 0x005: /* ITT1 */
7116 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7118 state->mmu_itt1 = REG_DA[(word2 >> 12) & 15];
7121 m68ki_exception_illegal(state);
7123 case 0x006: /* DTT0 */
7124 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7126 state->mmu_dtt0 = REG_DA[(word2 >> 12) & 15];
7129 m68ki_exception_illegal(state);
7131 case 0x007: /* DTT1 */
7132 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7134 state->mmu_dtt1 = REG_DA[(word2 >> 12) & 15];
7137 m68ki_exception_illegal(state);
7139 case 0x805: /* MMUSR */
7140 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7142 state->mmu_sr_040 = REG_DA[(word2 >> 12) & 15];
7145 m68ki_exception_illegal(state);
7147 case 0x806: /* URP */
7148 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7150 state->mmu_urp_aptr = REG_DA[(word2 >> 12) & 15];
7153 m68ki_exception_illegal(state);
7155 case 0x807: /* SRP */
7156 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7158 state->mmu_srp_aptr = REG_DA[(word2 >> 12) & 15];
7161 m68ki_exception_illegal(state);
7164 m68ki_exception_illegal(state);
7168 m68ki_exception_privilege_violation(state);
7171 m68ki_exception_illegal(state);
7175 M68KMAKE_OP(movem, 16, re, pd)
7178 uint register_list = OPER_I_16(state);
7183 if(register_list & (1 << i))
7186 m68ki_write_16(state, ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
7191 USE_CYCLES(count<<CYC_MOVEM_W);
7195 M68KMAKE_OP(movem, 16, re, .)
7198 uint register_list = OPER_I_16(state);
7199 uint ea = M68KMAKE_GET_EA_AY_16;
7203 if(register_list & (1 << i))
7205 m68ki_write_16(state, ea, MASK_OUT_ABOVE_16(REG_DA[i]));
7210 USE_CYCLES(count<<CYC_MOVEM_W);
7214 M68KMAKE_OP(movem, 32, re, pd)
7217 uint register_list = OPER_I_16(state);
7222 if(register_list & (1 << i))
7225 m68ki_write_16(state, ea+2, REG_DA[15-i] & 0xFFFF );
7226 m68ki_write_16(state, ea, (REG_DA[15-i] >> 16) & 0xFFFF );
7231 USE_CYCLES(count<<CYC_MOVEM_L);
7235 M68KMAKE_OP(movem, 32, re, .)
7238 uint register_list = OPER_I_16(state);
7239 uint ea = M68KMAKE_GET_EA_AY_32;
7243 if(register_list & (1 << i))
7245 m68ki_write_32(state, ea, REG_DA[i]);
7250 USE_CYCLES(count<<CYC_MOVEM_L);
7254 M68KMAKE_OP(movem, 16, er, pi)
7257 uint register_list = OPER_I_16(state);
7262 if(register_list & (1 << i))
7264 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(state, ea)));
7270 USE_CYCLES(count<<CYC_MOVEM_W);
7274 M68KMAKE_OP(movem, 16, er, pcdi)
7277 uint register_list = OPER_I_16(state);
7278 uint ea = EA_PCDI_16();
7282 if(register_list & (1 << i))
7284 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(state, ea)));
7289 USE_CYCLES(count<<CYC_MOVEM_W);
7293 M68KMAKE_OP(movem, 16, er, pcix)
7296 uint register_list = OPER_I_16(state);
7297 uint ea = EA_PCIX_16();
7301 if(register_list & (1 << i))
7303 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(state, ea)));
7308 USE_CYCLES(count<<CYC_MOVEM_W);
7312 M68KMAKE_OP(movem, 16, er, .)
7315 uint register_list = OPER_I_16(state);
7316 uint ea = M68KMAKE_GET_EA_AY_16;
7320 if(register_list & (1 << i))
7322 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(state, ea)));
7327 USE_CYCLES(count<<CYC_MOVEM_W);
7331 M68KMAKE_OP(movem, 32, er, pi)
7334 uint register_list = OPER_I_16(state);
7339 if(register_list & (1 << i))
7341 REG_DA[i] = m68ki_read_32(state, ea);
7347 USE_CYCLES(count<<CYC_MOVEM_L);
7351 M68KMAKE_OP(movem, 32, er, pcdi)
7354 uint register_list = OPER_I_16(state);
7355 uint ea = EA_PCDI_32();
7359 if(register_list & (1 << i))
7361 REG_DA[i] = m68ki_read_pcrel_32(state, ea);
7366 USE_CYCLES(count<<CYC_MOVEM_L);
7370 M68KMAKE_OP(movem, 32, er, pcix)
7373 uint register_list = OPER_I_16(state);
7374 uint ea = EA_PCIX_32();
7378 if(register_list & (1 << i))
7380 REG_DA[i] = m68ki_read_pcrel_32(state, ea);
7385 USE_CYCLES(count<<CYC_MOVEM_L);
7389 M68KMAKE_OP(movem, 32, er, .)
7392 uint register_list = OPER_I_16(state);
7393 uint ea = M68KMAKE_GET_EA_AY_32;
7397 if(register_list & (1 << i))
7399 REG_DA[i] = m68ki_read_32(state, ea);
7404 USE_CYCLES(count<<CYC_MOVEM_L);
7408 M68KMAKE_OP(movep, 16, re, .)
7410 uint ea = EA_AY_DI_16();
7413 m68ki_write_8(state, ea, MASK_OUT_ABOVE_8(src >> 8));
7414 m68ki_write_8(state, ea += 2, MASK_OUT_ABOVE_8(src));
7418 M68KMAKE_OP(movep, 32, re, .)
7420 uint ea = EA_AY_DI_32();
7423 m68ki_write_8(state, ea, MASK_OUT_ABOVE_8(src >> 24));
7424 m68ki_write_8(state, ea += 2, MASK_OUT_ABOVE_8(src >> 16));
7425 m68ki_write_8(state, ea += 2, MASK_OUT_ABOVE_8(src >> 8));
7426 m68ki_write_8(state, ea += 2, MASK_OUT_ABOVE_8(src));
7430 M68KMAKE_OP(movep, 16, er, .)
7432 uint ea = EA_AY_DI_16();
7435 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(state, ea) << 8) + m68ki_read_8(state, ea + 2));
7439 M68KMAKE_OP(movep, 32, er, .)
7441 uint ea = EA_AY_DI_32();
7443 DX = (m68ki_read_8(state, ea) << 24) + (m68ki_read_8(state, ea + 2) << 16)
7444 + (m68ki_read_8(state, ea + 4) << 8) + m68ki_read_8(state, ea + 6);
7448 M68KMAKE_OP(moves, 8, ., .)
7450 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7454 uint word2 = OPER_I_16(state);
7455 uint ea = M68KMAKE_GET_EA_AY_8;
7457 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7458 if(BIT_B(word2)) /* Register to memory */
7460 m68ki_write_8_fc(state, ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
7463 if(BIT_F(word2)) /* Memory to address register */
7465 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(state, ea, REG_SFC));
7466 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7470 /* Memory to data register */
7471 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(state, ea, REG_SFC);
7472 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7476 m68ki_exception_privilege_violation(state);
7479 m68ki_exception_illegal(state);
7483 M68KMAKE_OP(moves, 16, ., .)
7485 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7489 uint word2 = OPER_I_16(state);
7490 uint ea = M68KMAKE_GET_EA_AY_16;
7492 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7493 if(BIT_B(word2)) /* Register to memory */
7495 m68ki_write_16_fc(state, ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
7498 if(BIT_F(word2)) /* Memory to address register */
7500 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(state, ea, REG_SFC));
7501 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7505 /* Memory to data register */
7506 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(state, ea, REG_SFC);
7507 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7511 m68ki_exception_privilege_violation(state);
7514 m68ki_exception_illegal(state);
7518 M68KMAKE_OP(moves, 32, ., .)
7520 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7524 uint word2 = OPER_I_16(state);
7525 uint ea = M68KMAKE_GET_EA_AY_32;
7527 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7528 if(BIT_B(word2)) /* Register to memory */
7530 m68ki_write_32_fc(state, ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
7531 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7535 /* Memory to register */
7536 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(state, ea, REG_SFC);
7537 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7541 m68ki_exception_privilege_violation(state);
7544 m68ki_exception_illegal(state);
7548 M68KMAKE_OP(moveq, 32, ., .)
7550 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
7552 FLAG_N = NFLAG_32(res);
7554 FLAG_V = VFLAG_CLEAR;
7555 FLAG_C = CFLAG_CLEAR;
7559 M68KMAKE_OP(move16, 32, ., .)
7561 uint16 w2 = OPER_I_16(state);
7562 int ax = REG_IR & 7;
7563 int ay = (w2 >> 12) & 7;
7565 m68ki_write_32(state, REG_A[ay], m68ki_read_32(state, REG_A[ax]));
7566 m68ki_write_32(state, REG_A[ay]+4, m68ki_read_32(state, REG_A[ax]+4));
7567 m68ki_write_32(state, REG_A[ay]+8, m68ki_read_32(state, REG_A[ax]+8));
7568 m68ki_write_32(state, REG_A[ay]+12, m68ki_read_32(state, REG_A[ax]+12));
7575 M68KMAKE_OP(muls, 16, ., d)
7578 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7583 FLAG_N = NFLAG_32(res);
7584 FLAG_V = VFLAG_CLEAR;
7585 FLAG_C = CFLAG_CLEAR;
7589 M68KMAKE_OP(muls, 16, ., .)
7592 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7597 FLAG_N = NFLAG_32(res);
7598 FLAG_V = VFLAG_CLEAR;
7599 FLAG_C = CFLAG_CLEAR;
7603 M68KMAKE_OP(mulu, 16, ., d)
7606 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
7611 FLAG_N = NFLAG_32(res);
7612 FLAG_V = VFLAG_CLEAR;
7613 FLAG_C = CFLAG_CLEAR;
7617 M68KMAKE_OP(mulu, 16, ., .)
7620 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
7625 FLAG_N = NFLAG_32(res);
7626 FLAG_V = VFLAG_CLEAR;
7627 FLAG_C = CFLAG_CLEAR;
7631 M68KMAKE_OP(mull, 32, ., d)
7635 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7637 uint word2 = OPER_I_16(state);
7639 uint64 dst = REG_D[(word2 >> 12) & 7];
7642 FLAG_C = CFLAG_CLEAR;
7644 if(BIT_B(word2)) /* signed */
7646 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7649 FLAG_Z = MASK_OUT_ABOVE_32(res);
7650 FLAG_N = NFLAG_32(res);
7651 FLAG_V = ((sint64)res != (sint32)res)<<7;
7652 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7655 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7656 FLAG_N = NFLAG_64(res);
7657 FLAG_V = VFLAG_CLEAR;
7658 REG_D[word2 & 7] = (res >> 32);
7659 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7666 FLAG_Z = MASK_OUT_ABOVE_32(res);
7667 FLAG_N = NFLAG_32(res);
7668 FLAG_V = (res > 0xffffffff)<<7;
7669 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7672 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7673 FLAG_N = NFLAG_64(res);
7674 FLAG_V = VFLAG_CLEAR;
7675 REG_D[word2 & 7] = (res >> 32);
7676 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7679 m68ki_exception_illegal(state);
7683 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7685 uint word2 = OPER_I_16(state);
7687 uint dst = REG_D[(word2 >> 12) & 7];
7688 uint neg = GET_MSB_32(src ^ dst);
7700 FLAG_C = CFLAG_CLEAR;
7702 if(BIT_B(word2)) /* signed */
7705 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7707 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7710 src1 = MASK_OUT_ABOVE_16(src);
7712 dst1 = MASK_OUT_ABOVE_16(dst);
7721 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7722 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7724 if(BIT_B(word2) && neg)
7726 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7727 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7732 REG_D[word2 & 7] = hi;
7733 REG_D[(word2 >> 12) & 7] = lo;
7734 FLAG_N = NFLAG_32(hi);
7736 FLAG_V = VFLAG_CLEAR;
7740 REG_D[(word2 >> 12) & 7] = lo;
7741 FLAG_N = NFLAG_32(lo);
7744 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7746 FLAG_V = (hi != 0) << 7;
7749 m68ki_exception_illegal(state);
7755 M68KMAKE_OP(mull, 32, ., .)
7759 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7761 uint word2 = OPER_I_16(state);
7762 uint64 src = M68KMAKE_GET_OPER_AY_32;
7763 uint64 dst = REG_D[(word2 >> 12) & 7];
7766 FLAG_C = CFLAG_CLEAR;
7768 if(BIT_B(word2)) /* signed */
7770 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7773 FLAG_Z = MASK_OUT_ABOVE_32(res);
7774 FLAG_N = NFLAG_32(res);
7775 FLAG_V = ((sint64)res != (sint32)res)<<7;
7776 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7779 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7780 FLAG_N = NFLAG_64(res);
7781 FLAG_V = VFLAG_CLEAR;
7782 REG_D[word2 & 7] = (res >> 32);
7783 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7790 FLAG_Z = MASK_OUT_ABOVE_32(res);
7791 FLAG_N = NFLAG_32(res);
7792 FLAG_V = (res > 0xffffffff)<<7;
7793 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7796 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7797 FLAG_N = NFLAG_64(res);
7798 FLAG_V = VFLAG_CLEAR;
7799 REG_D[word2 & 7] = (res >> 32);
7800 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7803 m68ki_exception_illegal(state);
7807 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7809 uint word2 = OPER_I_16(state);
7810 uint src = M68KMAKE_GET_OPER_AY_32;
7811 uint dst = REG_D[(word2 >> 12) & 7];
7812 uint neg = GET_MSB_32(src ^ dst);
7824 FLAG_C = CFLAG_CLEAR;
7826 if(BIT_B(word2)) /* signed */
7829 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7831 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7834 src1 = MASK_OUT_ABOVE_16(src);
7836 dst1 = MASK_OUT_ABOVE_16(dst);
7845 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7846 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7848 if(BIT_B(word2) && neg)
7850 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7851 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7856 REG_D[word2 & 7] = hi;
7857 REG_D[(word2 >> 12) & 7] = lo;
7858 FLAG_N = NFLAG_32(hi);
7860 FLAG_V = VFLAG_CLEAR;
7864 REG_D[(word2 >> 12) & 7] = lo;
7865 FLAG_N = NFLAG_32(lo);
7868 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7870 FLAG_V = (hi != 0) << 7;
7873 m68ki_exception_illegal(state);
7879 M68KMAKE_OP(nbcd, 8, ., d)
7882 uint dst = MASK_OUT_ABOVE_8(*r_dst);
7883 uint res = - dst - XFLAG_AS_1();
7887 FLAG_V = res; /* Undefined V behavior */
7889 if(((res|dst) & 0x0f) == 0)
7890 res = (res & 0xf0) + 6;
7892 res = MASK_OUT_ABOVE_8(res + 0x9a);
7894 FLAG_V &= ~res; /* Undefined V behavior part II */
7896 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7904 FLAG_V = VFLAG_CLEAR;
7905 FLAG_C = CFLAG_CLEAR;
7906 FLAG_X = XFLAG_CLEAR;
7908 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7912 M68KMAKE_OP(nbcd, 8, ., .)
7914 uint ea = M68KMAKE_GET_EA_AY_8;
7915 uint dst = m68ki_read_8(state, ea);
7916 uint res = - dst - XFLAG_AS_1();
7920 FLAG_V = res; /* Undefined V behavior */
7922 if(((res|dst) & 0x0f) == 0)
7923 res = (res & 0xf0) + 6;
7925 res = MASK_OUT_ABOVE_8(res + 0x9a);
7927 FLAG_V &= ~res; /* Undefined V behavior part II */
7929 m68ki_write_8(state, ea, MASK_OUT_ABOVE_8(res));
7937 FLAG_V = VFLAG_CLEAR;
7938 FLAG_C = CFLAG_CLEAR;
7939 FLAG_X = XFLAG_CLEAR;
7941 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7945 M68KMAKE_OP(neg, 8, ., d)
7948 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
7950 FLAG_N = NFLAG_8(res);
7951 FLAG_C = FLAG_X = CFLAG_8(res);
7952 FLAG_V = *r_dst & res;
7953 FLAG_Z = MASK_OUT_ABOVE_8(res);
7955 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
7959 M68KMAKE_OP(neg, 8, ., .)
7961 uint ea = M68KMAKE_GET_EA_AY_8;
7962 uint src = m68ki_read_8(state, ea);
7965 FLAG_N = NFLAG_8(res);
7966 FLAG_C = FLAG_X = CFLAG_8(res);
7968 FLAG_Z = MASK_OUT_ABOVE_8(res);
7970 m68ki_write_8(state, ea, FLAG_Z);
7974 M68KMAKE_OP(neg, 16, ., d)
7977 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
7979 FLAG_N = NFLAG_16(res);
7980 FLAG_C = FLAG_X = CFLAG_16(res);
7981 FLAG_V = (*r_dst & res)>>8;
7982 FLAG_Z = MASK_OUT_ABOVE_16(res);
7984 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
7988 M68KMAKE_OP(neg, 16, ., .)
7990 uint ea = M68KMAKE_GET_EA_AY_16;
7991 uint src = m68ki_read_16(state, ea);
7994 FLAG_N = NFLAG_16(res);
7995 FLAG_C = FLAG_X = CFLAG_16(res);
7996 FLAG_V = (src & res)>>8;
7997 FLAG_Z = MASK_OUT_ABOVE_16(res);
7999 m68ki_write_16(state, ea, FLAG_Z);
8003 M68KMAKE_OP(neg, 32, ., d)
8006 uint res = 0 - *r_dst;
8008 FLAG_N = NFLAG_32(res);
8009 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
8010 FLAG_V = (*r_dst & res)>>24;
8011 FLAG_Z = MASK_OUT_ABOVE_32(res);
8017 M68KMAKE_OP(neg, 32, ., .)
8019 uint ea = M68KMAKE_GET_EA_AY_32;
8020 uint src = m68ki_read_32(state, ea);
8023 FLAG_N = NFLAG_32(res);
8024 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
8025 FLAG_V = (src & res)>>24;
8026 FLAG_Z = MASK_OUT_ABOVE_32(res);
8028 m68ki_write_32(state, ea, FLAG_Z);
8032 M68KMAKE_OP(negx, 8, ., d)
8035 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
8037 FLAG_N = NFLAG_8(res);
8038 FLAG_X = FLAG_C = CFLAG_8(res);
8039 FLAG_V = *r_dst & res;
8041 res = MASK_OUT_ABOVE_8(res);
8044 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8048 M68KMAKE_OP(negx, 8, ., .)
8050 uint ea = M68KMAKE_GET_EA_AY_8;
8051 uint src = m68ki_read_8(state, ea);
8052 uint res = 0 - src - XFLAG_AS_1();
8054 FLAG_N = NFLAG_8(res);
8055 FLAG_X = FLAG_C = CFLAG_8(res);
8058 res = MASK_OUT_ABOVE_8(res);
8061 m68ki_write_8(state, ea, res);
8065 M68KMAKE_OP(negx, 16, ., d)
8068 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
8070 FLAG_N = NFLAG_16(res);
8071 FLAG_X = FLAG_C = CFLAG_16(res);
8072 FLAG_V = (*r_dst & res)>>8;
8074 res = MASK_OUT_ABOVE_16(res);
8077 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8081 M68KMAKE_OP(negx, 16, ., .)
8083 uint ea = M68KMAKE_GET_EA_AY_16;
8084 uint src = m68ki_read_16(state, ea);
8085 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
8087 FLAG_N = NFLAG_16(res);
8088 FLAG_X = FLAG_C = CFLAG_16(res);
8089 FLAG_V = (src & res)>>8;
8091 res = MASK_OUT_ABOVE_16(res);
8094 m68ki_write_16(state, ea, res);
8098 M68KMAKE_OP(negx, 32, ., d)
8101 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
8103 FLAG_N = NFLAG_32(res);
8104 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
8105 FLAG_V = (*r_dst & res)>>24;
8107 res = MASK_OUT_ABOVE_32(res);
8114 M68KMAKE_OP(negx, 32, ., .)
8116 uint ea = M68KMAKE_GET_EA_AY_32;
8117 uint src = m68ki_read_32(state, ea);
8118 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
8120 FLAG_N = NFLAG_32(res);
8121 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
8122 FLAG_V = (src & res)>>24;
8124 res = MASK_OUT_ABOVE_32(res);
8127 m68ki_write_32(state, ea, res);
8131 M68KMAKE_OP(nop, 0, ., .)
8133 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8137 M68KMAKE_OP(not, 8, ., d)
8140 uint res = MASK_OUT_ABOVE_8(~*r_dst);
8142 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8144 FLAG_N = NFLAG_8(res);
8146 FLAG_C = CFLAG_CLEAR;
8147 FLAG_V = VFLAG_CLEAR;
8151 M68KMAKE_OP(not, 8, ., .)
8153 uint ea = M68KMAKE_GET_EA_AY_8;
8154 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(state, ea));
8156 m68ki_write_8(state, ea, res);
8158 FLAG_N = NFLAG_8(res);
8160 FLAG_C = CFLAG_CLEAR;
8161 FLAG_V = VFLAG_CLEAR;
8165 M68KMAKE_OP(not, 16, ., d)
8168 uint res = MASK_OUT_ABOVE_16(~*r_dst);
8170 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8172 FLAG_N = NFLAG_16(res);
8174 FLAG_C = CFLAG_CLEAR;
8175 FLAG_V = VFLAG_CLEAR;
8179 M68KMAKE_OP(not, 16, ., .)
8181 uint ea = M68KMAKE_GET_EA_AY_16;
8182 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(state, ea));
8184 m68ki_write_16(state, ea, res);
8186 FLAG_N = NFLAG_16(res);
8188 FLAG_C = CFLAG_CLEAR;
8189 FLAG_V = VFLAG_CLEAR;
8193 M68KMAKE_OP(not, 32, ., d)
8196 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
8198 FLAG_N = NFLAG_32(res);
8200 FLAG_C = CFLAG_CLEAR;
8201 FLAG_V = VFLAG_CLEAR;
8205 M68KMAKE_OP(not, 32, ., .)
8207 uint ea = M68KMAKE_GET_EA_AY_32;
8208 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(state, ea));
8210 m68ki_write_32(state, ea, res);
8212 FLAG_N = NFLAG_32(res);
8214 FLAG_C = CFLAG_CLEAR;
8215 FLAG_V = VFLAG_CLEAR;
8219 M68KMAKE_OP(or, 8, er, d)
8221 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
8223 FLAG_N = NFLAG_8(res);
8225 FLAG_C = CFLAG_CLEAR;
8226 FLAG_V = VFLAG_CLEAR;
8230 M68KMAKE_OP(or, 8, er, .)
8232 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
8234 FLAG_N = NFLAG_8(res);
8236 FLAG_C = CFLAG_CLEAR;
8237 FLAG_V = VFLAG_CLEAR;
8241 M68KMAKE_OP(or, 16, er, d)
8243 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
8245 FLAG_N = NFLAG_16(res);
8247 FLAG_C = CFLAG_CLEAR;
8248 FLAG_V = VFLAG_CLEAR;
8252 M68KMAKE_OP(or, 16, er, .)
8254 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
8256 FLAG_N = NFLAG_16(res);
8258 FLAG_C = CFLAG_CLEAR;
8259 FLAG_V = VFLAG_CLEAR;
8263 M68KMAKE_OP(or, 32, er, d)
8265 uint res = DX |= DY;
8267 FLAG_N = NFLAG_32(res);
8269 FLAG_C = CFLAG_CLEAR;
8270 FLAG_V = VFLAG_CLEAR;
8274 M68KMAKE_OP(or, 32, er, .)
8276 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
8278 FLAG_N = NFLAG_32(res);
8280 FLAG_C = CFLAG_CLEAR;
8281 FLAG_V = VFLAG_CLEAR;
8285 M68KMAKE_OP(or, 8, re, .)
8287 uint ea = M68KMAKE_GET_EA_AY_8;
8288 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(state, ea));
8290 m68ki_write_8(state, ea, res);
8292 FLAG_N = NFLAG_8(res);
8294 FLAG_C = CFLAG_CLEAR;
8295 FLAG_V = VFLAG_CLEAR;
8299 M68KMAKE_OP(or, 16, re, .)
8301 uint ea = M68KMAKE_GET_EA_AY_16;
8302 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(state, ea));
8304 m68ki_write_16(state, ea, res);
8306 FLAG_N = NFLAG_16(res);
8308 FLAG_C = CFLAG_CLEAR;
8309 FLAG_V = VFLAG_CLEAR;
8313 M68KMAKE_OP(or, 32, re, .)
8315 uint ea = M68KMAKE_GET_EA_AY_32;
8316 uint res = DX | m68ki_read_32(state, ea);
8318 m68ki_write_32(state, ea, res);
8320 FLAG_N = NFLAG_32(res);
8322 FLAG_C = CFLAG_CLEAR;
8323 FLAG_V = VFLAG_CLEAR;
8327 M68KMAKE_OP(ori, 8, ., d)
8329 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8(state)));
8331 FLAG_N = NFLAG_8(res);
8333 FLAG_C = CFLAG_CLEAR;
8334 FLAG_V = VFLAG_CLEAR;
8338 M68KMAKE_OP(ori, 8, ., .)
8340 uint src = OPER_I_8(state);
8341 uint ea = M68KMAKE_GET_EA_AY_8;
8342 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(state, ea));
8344 m68ki_write_8(state, ea, res);
8346 FLAG_N = NFLAG_8(res);
8348 FLAG_C = CFLAG_CLEAR;
8349 FLAG_V = VFLAG_CLEAR;
8353 M68KMAKE_OP(ori, 16, ., d)
8355 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16(state));
8357 FLAG_N = NFLAG_16(res);
8359 FLAG_C = CFLAG_CLEAR;
8360 FLAG_V = VFLAG_CLEAR;
8364 M68KMAKE_OP(ori, 16, ., .)
8366 uint src = OPER_I_16(state);
8367 uint ea = M68KMAKE_GET_EA_AY_16;
8368 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(state, ea));
8370 m68ki_write_16(state, ea, res);
8372 FLAG_N = NFLAG_16(res);
8374 FLAG_C = CFLAG_CLEAR;
8375 FLAG_V = VFLAG_CLEAR;
8379 M68KMAKE_OP(ori, 32, ., d)
8381 uint res = DY |= OPER_I_32(state);
8383 FLAG_N = NFLAG_32(res);
8385 FLAG_C = CFLAG_CLEAR;
8386 FLAG_V = VFLAG_CLEAR;
8390 M68KMAKE_OP(ori, 32, ., .)
8392 uint src = OPER_I_32(state);
8393 uint ea = M68KMAKE_GET_EA_AY_32;
8394 uint res = src | m68ki_read_32(state, ea);
8396 m68ki_write_32(state, ea, res);
8398 FLAG_N = NFLAG_32(res);
8400 FLAG_C = CFLAG_CLEAR;
8401 FLAG_V = VFLAG_CLEAR;
8405 M68KMAKE_OP(ori, 16, toc, .)
8407 m68ki_set_ccr(state, m68ki_get_ccr(state) | OPER_I_8(state));
8411 M68KMAKE_OP(ori, 16, tos, .)
8415 uint src = OPER_I_16(state);
8416 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8417 m68ki_set_sr(state, m68ki_get_sr() | src);
8420 m68ki_exception_privilege_violation(state);
8424 M68KMAKE_OP(pack, 16, rr, .)
8426 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8428 /* Note: DX and DY are reversed in Motorola's docs */
8429 uint src = DY + OPER_I_16(state);
8432 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
8435 m68ki_exception_illegal(state);
8439 M68KMAKE_OP(pack, 16, mm, ax7)
8441 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8443 /* Note: AX and AY are reversed in Motorola's docs */
8444 uint ea_src = EA_AY_PD_8();
8445 uint src = m68ki_read_8(state, ea_src);
8446 ea_src = EA_AY_PD_8();
8447 src = ((src << 8) | m68ki_read_8(state, ea_src)) + OPER_I_16(state);
8449 m68ki_write_8(state, EA_A7_PD_8(), ((src >> 8) & 0x000f) | ((src<<4) & 0x00f0));
8452 m68ki_exception_illegal(state);
8456 M68KMAKE_OP(pack, 16, mm, ay7)
8458 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8460 /* Note: AX and AY are reversed in Motorola's docs */
8461 uint ea_src = EA_A7_PD_8();
8462 uint src = m68ki_read_8(state, ea_src);
8463 ea_src = EA_A7_PD_8();
8464 src = (src | (m68ki_read_8(state, ea_src) << 8)) + OPER_I_16(state);
8466 m68ki_write_8(state, EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8469 m68ki_exception_illegal(state);
8473 M68KMAKE_OP(pack, 16, mm, axy7)
8475 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8477 uint ea_src = EA_A7_PD_8();
8478 uint src = m68ki_read_8(state, ea_src);
8479 ea_src = EA_A7_PD_8();
8480 src = (src | (m68ki_read_8(state, ea_src) << 8)) + OPER_I_16(state);
8482 m68ki_write_8(state, EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8485 m68ki_exception_illegal(state);
8489 M68KMAKE_OP(pack, 16, mm, .)
8491 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8493 /* Note: AX and AY are reversed in Motorola's docs */
8494 uint ea_src = EA_AY_PD_8();
8495 uint src = m68ki_read_8(state, ea_src);
8496 ea_src = EA_AY_PD_8();
8497 src = (src | (m68ki_read_8(state, ea_src) << 8)) + OPER_I_16(state);
8499 m68ki_write_8(state, EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8502 m68ki_exception_illegal(state);
8506 M68KMAKE_OP(pea, 32, ., .)
8508 uint ea = M68KMAKE_GET_EA_AY_32;
8510 m68ki_push_32(state, ea);
8513 M68KMAKE_OP(pflusha, 32, ., .)
8517 fprintf(stderr,"68040: unhandled PFLUSHA (ir=%04x)\n", REG_IR);
8520 m68ki_exception_1111(state);
8523 M68KMAKE_OP(pflushan, 32, ., .)
8527 fprintf(stderr,"68040: unhandled PFLUSHAN (ir=%04x)\n", REG_IR);
8530 m68ki_exception_1111(state);
8533 M68KMAKE_OP(pmmu, 32, ., .)
8535 if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU))
8537 m68851_mmu_ops(state);
8541 m68ki_exception_1111(state);
8545 M68KMAKE_OP(reset, 0, ., .)
8549 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
8550 USE_CYCLES(CYC_RESET);
8553 m68ki_exception_privilege_violation(state);
8557 M68KMAKE_OP(ror, 8, s, .)
8560 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8561 uint shift = orig_shift & 7;
8562 uint src = MASK_OUT_ABOVE_8(*r_dst);
8563 uint res = ROR_8(src, shift);
8566 USE_CYCLES(orig_shift<<CYC_SHIFT);
8568 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8570 FLAG_N = NFLAG_8(res);
8572 FLAG_C = src << (9-orig_shift);
8573 FLAG_V = VFLAG_CLEAR;
8577 M68KMAKE_OP(ror, 16, s, .)
8580 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8581 uint src = MASK_OUT_ABOVE_16(*r_dst);
8582 uint res = ROR_16(src, shift);
8585 USE_CYCLES(shift<<CYC_SHIFT);
8587 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8589 FLAG_N = NFLAG_16(res);
8591 FLAG_C = src << (9-shift);
8592 FLAG_V = VFLAG_CLEAR;
8596 M68KMAKE_OP(ror, 32, s, .)
8599 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8600 uint64 src = *r_dst;
8601 uint res = ROR_32(src, shift);
8604 USE_CYCLES(shift<<CYC_SHIFT);
8608 FLAG_N = NFLAG_32(res);
8610 FLAG_C = src << (9-shift);
8611 FLAG_V = VFLAG_CLEAR;
8615 M68KMAKE_OP(ror, 8, r, .)
8618 uint orig_shift = DX & 0x3f;
8619 uint shift = orig_shift & 7;
8620 uint src = MASK_OUT_ABOVE_8(*r_dst);
8621 uint res = ROR_8(src, shift);
8625 USE_CYCLES(orig_shift<<CYC_SHIFT);
8627 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8628 FLAG_C = src << (8-((shift-1)&7));
8629 FLAG_N = NFLAG_8(res);
8631 FLAG_V = VFLAG_CLEAR;
8635 FLAG_C = CFLAG_CLEAR;
8636 FLAG_N = NFLAG_8(src);
8638 FLAG_V = VFLAG_CLEAR;
8642 M68KMAKE_OP(ror, 16, r, .)
8645 uint orig_shift = DX & 0x3f;
8646 uint shift = orig_shift & 15;
8647 uint src = MASK_OUT_ABOVE_16(*r_dst);
8648 uint res = ROR_16(src, shift);
8652 USE_CYCLES(orig_shift<<CYC_SHIFT);
8654 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8655 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
8656 FLAG_N = NFLAG_16(res);
8658 FLAG_V = VFLAG_CLEAR;
8662 FLAG_C = CFLAG_CLEAR;
8663 FLAG_N = NFLAG_16(src);
8665 FLAG_V = VFLAG_CLEAR;
8669 M68KMAKE_OP(ror, 32, r, .)
8672 uint orig_shift = DX & 0x3f;
8673 uint shift = orig_shift & 31;
8674 uint64 src = *r_dst;
8675 uint res = ROR_32(src, shift);
8679 USE_CYCLES(orig_shift<<CYC_SHIFT);
8682 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
8683 FLAG_N = NFLAG_32(res);
8685 FLAG_V = VFLAG_CLEAR;
8689 FLAG_C = CFLAG_CLEAR;
8690 FLAG_N = NFLAG_32(src);
8692 FLAG_V = VFLAG_CLEAR;
8696 M68KMAKE_OP(ror, 16, ., .)
8698 uint ea = M68KMAKE_GET_EA_AY_16;
8699 uint src = m68ki_read_16(state, ea);
8700 uint res = ROR_16(src, 1);
8702 m68ki_write_16(state, ea, res);
8704 FLAG_N = NFLAG_16(res);
8707 FLAG_V = VFLAG_CLEAR;
8711 M68KMAKE_OP(rol, 8, s, .)
8714 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8715 uint shift = orig_shift & 7;
8716 uint src = MASK_OUT_ABOVE_8(*r_dst);
8717 uint res = ROL_8(src, shift);
8720 USE_CYCLES(orig_shift<<CYC_SHIFT);
8722 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8724 FLAG_N = NFLAG_8(res);
8726 FLAG_C = src << orig_shift;
8727 FLAG_V = VFLAG_CLEAR;
8731 M68KMAKE_OP(rol, 16, s, .)
8734 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8735 uint src = MASK_OUT_ABOVE_16(*r_dst);
8736 uint res = ROL_16(src, shift);
8739 USE_CYCLES(shift<<CYC_SHIFT);
8741 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8743 FLAG_N = NFLAG_16(res);
8745 FLAG_C = src >> (8-shift);
8746 FLAG_V = VFLAG_CLEAR;
8750 M68KMAKE_OP(rol, 32, s, .)
8753 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8754 uint64 src = *r_dst;
8755 uint res = ROL_32(src, shift);
8758 USE_CYCLES(shift<<CYC_SHIFT);
8762 FLAG_N = NFLAG_32(res);
8764 FLAG_C = src >> (24-shift);
8765 FLAG_V = VFLAG_CLEAR;
8769 M68KMAKE_OP(rol, 8, r, .)
8772 uint orig_shift = DX & 0x3f;
8773 uint shift = orig_shift & 7;
8774 uint src = MASK_OUT_ABOVE_8(*r_dst);
8775 uint res = ROL_8(src, shift);
8779 USE_CYCLES(orig_shift<<CYC_SHIFT);
8783 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8784 FLAG_C = src << shift;
8785 FLAG_N = NFLAG_8(res);
8787 FLAG_V = VFLAG_CLEAR;
8790 FLAG_C = (src & 1)<<8;
8791 FLAG_N = NFLAG_8(src);
8793 FLAG_V = VFLAG_CLEAR;
8797 FLAG_C = CFLAG_CLEAR;
8798 FLAG_N = NFLAG_8(src);
8800 FLAG_V = VFLAG_CLEAR;
8804 M68KMAKE_OP(rol, 16, r, .)
8807 uint orig_shift = DX & 0x3f;
8808 uint shift = orig_shift & 15;
8809 uint src = MASK_OUT_ABOVE_16(*r_dst);
8810 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
8814 USE_CYCLES(orig_shift<<CYC_SHIFT);
8818 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8819 FLAG_C = (src << shift) >> 8;
8820 FLAG_N = NFLAG_16(res);
8822 FLAG_V = VFLAG_CLEAR;
8825 FLAG_C = (src & 1)<<8;
8826 FLAG_N = NFLAG_16(src);
8828 FLAG_V = VFLAG_CLEAR;
8832 FLAG_C = CFLAG_CLEAR;
8833 FLAG_N = NFLAG_16(src);
8835 FLAG_V = VFLAG_CLEAR;
8839 M68KMAKE_OP(rol, 32, r, .)
8842 uint orig_shift = DX & 0x3f;
8843 uint shift = orig_shift & 31;
8844 uint64 src = *r_dst;
8845 uint res = ROL_32(src, shift);
8849 USE_CYCLES(orig_shift<<CYC_SHIFT);
8853 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
8854 FLAG_N = NFLAG_32(res);
8856 FLAG_V = VFLAG_CLEAR;
8860 FLAG_C = CFLAG_CLEAR;
8861 FLAG_N = NFLAG_32(src);
8863 FLAG_V = VFLAG_CLEAR;
8867 M68KMAKE_OP(rol, 16, ., .)
8869 uint ea = M68KMAKE_GET_EA_AY_16;
8870 uint src = m68ki_read_16(state, ea);
8871 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
8873 m68ki_write_16(state, ea, res);
8875 FLAG_N = NFLAG_16(res);
8878 FLAG_V = VFLAG_CLEAR;
8882 M68KMAKE_OP(roxr, 8, s, .)
8885 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8886 uint src = MASK_OUT_ABOVE_8(*r_dst);
8887 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8890 USE_CYCLES(shift<<CYC_SHIFT);
8892 FLAG_C = FLAG_X = res;
8893 res = MASK_OUT_ABOVE_8(res);
8895 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8897 FLAG_N = NFLAG_8(res);
8899 FLAG_V = VFLAG_CLEAR;
8903 M68KMAKE_OP(roxr, 16, s, .)
8906 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8907 uint src = MASK_OUT_ABOVE_16(*r_dst);
8908 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8911 USE_CYCLES(shift<<CYC_SHIFT);
8913 FLAG_C = FLAG_X = res >> 8;
8914 res = MASK_OUT_ABOVE_16(res);
8916 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8918 FLAG_N = NFLAG_16(res);
8920 FLAG_V = VFLAG_CLEAR;
8924 M68KMAKE_OP(roxr, 32, s, .)
8929 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8930 uint64 src = *r_dst;
8931 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8934 USE_CYCLES(shift<<CYC_SHIFT);
8936 res = ROR_33_64(res, shift);
8938 FLAG_C = FLAG_X = res >> 24;
8939 res = MASK_OUT_ABOVE_32(res);
8943 FLAG_N = NFLAG_32(res);
8945 FLAG_V = VFLAG_CLEAR;
8950 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8952 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8953 uint new_x_flag = src & (1 << (shift - 1));
8956 USE_CYCLES(shift<<CYC_SHIFT);
8960 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
8961 FLAG_N = NFLAG_32(res);
8963 FLAG_V = VFLAG_CLEAR;
8969 M68KMAKE_OP(roxr, 8, r, .)
8972 uint orig_shift = DX & 0x3f;
8976 uint shift = orig_shift % 9;
8977 uint src = MASK_OUT_ABOVE_8(*r_dst);
8978 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8980 USE_CYCLES(orig_shift<<CYC_SHIFT);
8982 FLAG_C = FLAG_X = res;
8983 res = MASK_OUT_ABOVE_8(res);
8985 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8986 FLAG_N = NFLAG_8(res);
8988 FLAG_V = VFLAG_CLEAR;
8993 FLAG_N = NFLAG_8(*r_dst);
8994 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
8995 FLAG_V = VFLAG_CLEAR;
8999 M68KMAKE_OP(roxr, 16, r, .)
9002 uint orig_shift = DX & 0x3f;
9006 uint shift = orig_shift % 17;
9007 uint src = MASK_OUT_ABOVE_16(*r_dst);
9008 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
9010 USE_CYCLES(orig_shift<<CYC_SHIFT);
9012 FLAG_C = FLAG_X = res >> 8;
9013 res = MASK_OUT_ABOVE_16(res);
9015 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9016 FLAG_N = NFLAG_16(res);
9018 FLAG_V = VFLAG_CLEAR;
9023 FLAG_N = NFLAG_16(*r_dst);
9024 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
9025 FLAG_V = VFLAG_CLEAR;
9029 M68KMAKE_OP(roxr, 32, r, .)
9034 uint orig_shift = DX & 0x3f;
9038 uint shift = orig_shift % 33;
9039 uint64 src = *r_dst;
9040 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9042 res = ROR_33_64(res, shift);
9044 USE_CYCLES(orig_shift<<CYC_SHIFT);
9046 FLAG_C = FLAG_X = res >> 24;
9047 res = MASK_OUT_ABOVE_32(res);
9050 FLAG_N = NFLAG_32(res);
9052 FLAG_V = VFLAG_CLEAR;
9057 FLAG_N = NFLAG_32(*r_dst);
9059 FLAG_V = VFLAG_CLEAR;
9064 uint orig_shift = DX & 0x3f;
9065 uint shift = orig_shift % 33;
9067 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
9068 uint new_x_flag = src & (1 << (shift - 1));
9071 USE_CYCLES(orig_shift<<CYC_SHIFT);
9076 FLAG_X = (new_x_flag != 0)<<8;
9081 FLAG_N = NFLAG_32(res);
9083 FLAG_V = VFLAG_CLEAR;
9089 M68KMAKE_OP(roxr, 16, ., .)
9091 uint ea = M68KMAKE_GET_EA_AY_16;
9092 uint src = m68ki_read_16(state, ea);
9093 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
9095 FLAG_C = FLAG_X = res >> 8;
9096 res = MASK_OUT_ABOVE_16(res);
9098 m68ki_write_16(state, ea, res);
9100 FLAG_N = NFLAG_16(res);
9102 FLAG_V = VFLAG_CLEAR;
9106 M68KMAKE_OP(roxl, 8, s, .)
9109 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9110 uint src = MASK_OUT_ABOVE_8(*r_dst);
9111 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9114 USE_CYCLES(shift<<CYC_SHIFT);
9116 FLAG_C = FLAG_X = res;
9117 res = MASK_OUT_ABOVE_8(res);
9119 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9121 FLAG_N = NFLAG_8(res);
9123 FLAG_V = VFLAG_CLEAR;
9127 M68KMAKE_OP(roxl, 16, s, .)
9130 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9131 uint src = MASK_OUT_ABOVE_16(*r_dst);
9132 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9135 USE_CYCLES(shift<<CYC_SHIFT);
9137 FLAG_C = FLAG_X = res >> 8;
9138 res = MASK_OUT_ABOVE_16(res);
9140 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9142 FLAG_N = NFLAG_16(res);
9144 FLAG_V = VFLAG_CLEAR;
9148 M68KMAKE_OP(roxl, 32, s, .)
9153 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9154 uint64 src = *r_dst;
9155 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9158 USE_CYCLES(shift<<CYC_SHIFT);
9160 res = ROL_33_64(res, shift);
9162 FLAG_C = FLAG_X = res >> 24;
9163 res = MASK_OUT_ABOVE_32(res);
9167 FLAG_N = NFLAG_32(res);
9169 FLAG_V = VFLAG_CLEAR;
9174 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9176 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9177 uint new_x_flag = src & (1 << (32 - shift));
9180 USE_CYCLES(shift<<CYC_SHIFT);
9184 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
9185 FLAG_N = NFLAG_32(res);
9187 FLAG_V = VFLAG_CLEAR;
9193 M68KMAKE_OP(roxl, 8, r, .)
9196 uint orig_shift = DX & 0x3f;
9201 uint shift = orig_shift % 9;
9202 uint src = MASK_OUT_ABOVE_8(*r_dst);
9203 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9205 USE_CYCLES(orig_shift<<CYC_SHIFT);
9207 FLAG_C = FLAG_X = res;
9208 res = MASK_OUT_ABOVE_8(res);
9210 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9211 FLAG_N = NFLAG_8(res);
9213 FLAG_V = VFLAG_CLEAR;
9218 FLAG_N = NFLAG_8(*r_dst);
9219 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
9220 FLAG_V = VFLAG_CLEAR;
9224 M68KMAKE_OP(roxl, 16, r, .)
9227 uint orig_shift = DX & 0x3f;
9231 uint shift = orig_shift % 17;
9232 uint src = MASK_OUT_ABOVE_16(*r_dst);
9233 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9235 USE_CYCLES(orig_shift<<CYC_SHIFT);
9237 FLAG_C = FLAG_X = res >> 8;
9238 res = MASK_OUT_ABOVE_16(res);
9240 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9241 FLAG_N = NFLAG_16(res);
9243 FLAG_V = VFLAG_CLEAR;
9248 FLAG_N = NFLAG_16(*r_dst);
9249 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
9250 FLAG_V = VFLAG_CLEAR;
9254 M68KMAKE_OP(roxl, 32, r, .)
9259 uint orig_shift = DX & 0x3f;
9263 uint shift = orig_shift % 33;
9264 uint64 src = *r_dst;
9265 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9267 res = ROL_33_64(res, shift);
9269 USE_CYCLES(orig_shift<<CYC_SHIFT);
9271 FLAG_C = FLAG_X = res >> 24;
9272 res = MASK_OUT_ABOVE_32(res);
9275 FLAG_N = NFLAG_32(res);
9277 FLAG_V = VFLAG_CLEAR;
9282 FLAG_N = NFLAG_32(*r_dst);
9284 FLAG_V = VFLAG_CLEAR;
9289 uint orig_shift = DX & 0x3f;
9290 uint shift = orig_shift % 33;
9292 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9293 uint new_x_flag = src & (1 << (32 - shift));
9296 USE_CYCLES(orig_shift<<CYC_SHIFT);
9301 FLAG_X = (new_x_flag != 0)<<8;
9306 FLAG_N = NFLAG_32(res);
9308 FLAG_V = VFLAG_CLEAR;
9314 M68KMAKE_OP(roxl, 16, ., .)
9316 uint ea = M68KMAKE_GET_EA_AY_16;
9317 uint src = m68ki_read_16(state, ea);
9318 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
9320 FLAG_C = FLAG_X = res >> 8;
9321 res = MASK_OUT_ABOVE_16(res);
9323 m68ki_write_16(state, ea, res);
9325 FLAG_N = NFLAG_16(res);
9327 FLAG_V = VFLAG_CLEAR;
9331 M68KMAKE_OP(rtd, 32, ., .)
9333 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
9335 uint new_pc = m68ki_pull_32(state);
9337 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9338 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state)));
9339 m68ki_jump(state, new_pc);
9342 m68ki_exception_illegal(state);
9346 M68KMAKE_OP(rte, 32, ., .)
9354 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
9355 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9357 if(CPU_TYPE_IS_000(CPU_TYPE))
9359 new_sr = m68ki_pull_16(state);
9360 new_pc = m68ki_pull_32(state);
9361 m68ki_jump(state, new_pc);
9362 m68ki_set_sr(state, new_sr);
9364 CPU_INSTR_MODE = INSTRUCTION_YES;
9365 CPU_RUN_MODE = RUN_MODE_NORMAL;
9370 if(CPU_TYPE_IS_010(CPU_TYPE))
9372 format_word = m68ki_read_16(state, REG_A[7]+6) >> 12;
9373 if(format_word == 0)
9375 new_sr = m68ki_pull_16(state);
9376 new_pc = m68ki_pull_32(state);
9377 m68ki_fake_pull_16(state); /* format word */
9378 m68ki_jump(state, new_pc);
9379 m68ki_set_sr(state, new_sr);
9380 CPU_INSTR_MODE = INSTRUCTION_YES;
9381 CPU_RUN_MODE = RUN_MODE_NORMAL;
9383 } else if (format_word == 8) {
9384 /* Format 8 stack frame -- 68010 only. 29 word bus/address error */
9385 new_sr = m68ki_pull_16(state);
9386 new_pc = m68ki_pull_32(state);
9387 m68ki_fake_pull_16(state); /* format word */
9388 m68ki_jump(state, new_pc);
9389 m68ki_set_sr(state, new_sr);
9390 CPU_INSTR_MODE = INSTRUCTION_YES;
9391 CPU_RUN_MODE = RUN_MODE_NORMAL;
9392 m68ki_fake_pull_16(state); /* special status */
9393 m68ki_fake_pull_32(state); /* fault address */
9394 m68ki_fake_pull_32(state); /* reserved and data output buffer */
9395 m68ki_fake_pull_32(state); /* reserved and data input buffer */
9396 m68ki_fake_pull_32(state); /* reserved and instruction input buffer */
9397 m68ki_fake_pull_32(state); /* 8 dwords of CPU specific undocumented data */
9398 m68ki_fake_pull_32(state);
9399 m68ki_fake_pull_32(state);
9400 m68ki_fake_pull_32(state);
9401 m68ki_fake_pull_32(state);
9402 m68ki_fake_pull_32(state);
9403 m68ki_fake_pull_32(state);
9404 m68ki_fake_pull_32(state);
9407 CPU_INSTR_MODE = INSTRUCTION_YES;
9408 CPU_RUN_MODE = RUN_MODE_NORMAL;
9409 /* Not handling other exception types (9) */
9410 m68ki_exception_format_error(state);
9414 /* Otherwise it's 020 */
9416 format_word = m68ki_read_16(state, REG_A[7]+6) >> 12;
9419 case 0: /* Normal */
9420 new_sr = m68ki_pull_16(state);
9421 new_pc = m68ki_pull_32(state);
9422 m68ki_fake_pull_16(state); /* format word */
9423 m68ki_jump(state, new_pc);
9424 m68ki_set_sr(state, new_sr);
9425 CPU_INSTR_MODE = INSTRUCTION_YES;
9426 CPU_RUN_MODE = RUN_MODE_NORMAL;
9428 case 1: /* Throwaway */
9429 new_sr = m68ki_pull_16(state);
9430 m68ki_fake_pull_32(state); /* program counter */
9431 m68ki_fake_pull_16(state); /* format word */
9432 m68ki_set_sr_noint(state, new_sr);
9435 new_sr = m68ki_pull_16(state);
9436 new_pc = m68ki_pull_32(state);
9437 m68ki_fake_pull_16(state); /* format word */
9438 m68ki_fake_pull_32(state); /* address */
9439 m68ki_jump(state, new_pc);
9440 m68ki_set_sr(state, new_sr);
9441 CPU_INSTR_MODE = INSTRUCTION_YES;
9442 CPU_RUN_MODE = RUN_MODE_NORMAL;
9444 case 7: /* 68040 access error */
9445 new_sr = m68ki_pull_16(state);
9446 new_pc = m68ki_pull_32(state);
9447 m68ki_fake_pull_16(state); /* $06: format word */
9448 m68ki_fake_pull_32(state); /* $08: effective address */
9449 m68ki_fake_pull_16(state); /* $0c: special status word */
9450 m68ki_fake_pull_16(state); /* $0e: wb3s */
9451 m68ki_fake_pull_16(state); /* $10: wb2s */
9452 m68ki_fake_pull_16(state); /* $12: wb1s */
9453 m68ki_fake_pull_32(state); /* $14: data fault address */
9454 m68ki_fake_pull_32(state); /* $18: wb3a */
9455 m68ki_fake_pull_32(state); /* $1c: wb3d */
9456 m68ki_fake_pull_32(state); /* $20: wb2a */
9457 m68ki_fake_pull_32(state); /* $24: wb2d */
9458 m68ki_fake_pull_32(state); /* $28: wb1a */
9459 m68ki_fake_pull_32(state); /* $2c: wb1d/pd0 */
9460 m68ki_fake_pull_32(state); /* $30: pd1 */
9461 m68ki_fake_pull_32(state); /* $34: pd2 */
9462 m68ki_fake_pull_32(state); /* $38: pd3 */
9463 m68ki_jump(state, new_pc);
9464 m68ki_set_sr(state, new_sr);
9465 CPU_INSTR_MODE = INSTRUCTION_YES;
9466 CPU_RUN_MODE = RUN_MODE_NORMAL;
9469 case 0x0a: /* Bus Error at instruction boundary */
9470 new_sr = m68ki_pull_16(state);
9471 new_pc = m68ki_pull_32(state);
9472 m68ki_fake_pull_16(state); /* $06: format word */
9473 m68ki_fake_pull_16(state); /* $08: internal register */
9474 m68ki_fake_pull_16(state); /* $0a: special status word */
9475 m68ki_fake_pull_16(state); /* $0c: instruction pipe stage c */
9476 m68ki_fake_pull_16(state); /* $0e: instruction pipe stage b */
9477 m68ki_fake_pull_32(state); /* $10: data fault address */
9478 m68ki_fake_pull_32(state); /* $14: internal registers */
9479 m68ki_fake_pull_32(state); /* $18: data output buffer */
9480 m68ki_fake_pull_32(state); /* $1c: internal registers */
9482 m68ki_jump(state, new_pc);
9483 m68ki_set_sr(state, new_sr);
9484 CPU_INSTR_MODE = INSTRUCTION_YES;
9485 CPU_RUN_MODE = RUN_MODE_NORMAL;
9488 case 0x0b: /* Bus Error - Instruction Execution in Progress */
9489 new_sr = m68ki_pull_16(state);
9490 new_pc = m68ki_pull_32(state);
9491 m68ki_fake_pull_16(state); /* $06: format word */
9492 m68ki_fake_pull_16(state); /* $08: internal register */
9493 m68ki_fake_pull_16(state); /* $0a: special status word */
9494 m68ki_fake_pull_16(state); /* $0c: instruction pipe stage c */
9495 m68ki_fake_pull_16(state); /* $0e: instruction pipe stage b */
9496 m68ki_fake_pull_32(state); /* $10: data fault address */
9497 m68ki_fake_pull_32(state); /* $14: internal registers */
9498 m68ki_fake_pull_32(state); /* $18: data output buffer */
9499 m68ki_fake_pull_32(state); /* $1c: internal registers */
9500 m68ki_fake_pull_32(state); /* $20: */
9501 m68ki_fake_pull_32(state); /* $24: stage B address */
9502 m68ki_fake_pull_32(state); /* $28: */
9503 m68ki_fake_pull_32(state); /* $2c: data input buffer */
9504 m68ki_fake_pull_32(state); /* $30: */
9505 m68ki_fake_pull_16(state); /* $34: */
9506 m68ki_fake_pull_16(state); /* $36: version #, internal information */
9507 m68ki_fake_pull_32(state); /* $38: */
9508 m68ki_fake_pull_32(state); /* $3c: */
9509 m68ki_fake_pull_32(state); /* $40: */
9510 m68ki_fake_pull_32(state); /* $44: */
9511 m68ki_fake_pull_32(state); /* $48: */
9512 m68ki_fake_pull_32(state); /* $4c: */
9513 m68ki_fake_pull_32(state); /* $50: */
9514 m68ki_fake_pull_32(state); /* $54: */
9515 m68ki_fake_pull_32(state); /* $58: */
9517 m68ki_jump(state, new_pc);
9518 m68ki_set_sr(state, new_sr);
9519 CPU_INSTR_MODE = INSTRUCTION_YES;
9520 CPU_RUN_MODE = RUN_MODE_NORMAL;
9523 /* Not handling long or short bus fault */
9524 CPU_INSTR_MODE = INSTRUCTION_YES;
9525 CPU_RUN_MODE = RUN_MODE_NORMAL;
9526 m68ki_exception_format_error(state);
9529 m68ki_exception_privilege_violation(state);
9533 M68KMAKE_OP(rtm, 32, ., .)
9535 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
9537 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9538 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
9539 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
9540 m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
9543 m68ki_exception_illegal(state);
9547 M68KMAKE_OP(rtr, 32, ., .)
9549 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9550 m68ki_set_ccr(state, m68ki_pull_16(state));
9551 m68ki_jump(state, m68ki_pull_32(state));
9555 M68KMAKE_OP(rts, 32, ., .)
9557 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9558 m68ki_jump(state, m68ki_pull_32(state));
9562 M68KMAKE_OP(sbcd, 8, rr, .)
9567 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9572 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9573 FLAG_V = res; /* Undefined V behavior */
9576 FLAG_X = FLAG_C = CFLAG_SET;
9577 } else if(res < corf)
9578 FLAG_X = FLAG_C = CFLAG_SET;
9580 FLAG_N = FLAG_X = FLAG_C = 0;
9582 res = MASK_OUT_ABOVE_8(res - corf);
9584 FLAG_V &= ~res; /* Undefined V behavior part II */
9585 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9588 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9592 M68KMAKE_OP(sbcd, 8, mm, ax7)
9594 uint src = OPER_AY_PD_8(state);
9595 uint ea = EA_A7_PD_8();
9596 uint dst = m68ki_read_8(state, ea);
9597 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9602 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9603 FLAG_V = res; /* Undefined V behavior */
9606 FLAG_X = FLAG_C = CFLAG_SET;
9607 } else if(res < corf)
9608 FLAG_X = FLAG_C = CFLAG_SET;
9610 FLAG_N = FLAG_X = FLAG_C = 0;
9612 res = MASK_OUT_ABOVE_8(res - corf);
9614 FLAG_V &= ~res; /* Undefined V behavior part II */
9615 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9618 m68ki_write_8(state, ea, res);
9622 M68KMAKE_OP(sbcd, 8, mm, ay7)
9624 uint src = OPER_A7_PD_8(state);
9625 uint ea = EA_AX_PD_8();
9626 uint dst = m68ki_read_8(state, ea);
9627 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9632 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9633 FLAG_V = res; /* Undefined V behavior */
9636 FLAG_X = FLAG_C = CFLAG_SET;
9637 } else if(res < corf)
9638 FLAG_X = FLAG_C = CFLAG_SET;
9640 FLAG_N = FLAG_X = FLAG_C = 0;
9642 res = MASK_OUT_ABOVE_8(res - corf);
9644 FLAG_V &= ~res; /* Undefined V behavior part II */
9645 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9648 m68ki_write_8(state, ea, res);
9652 M68KMAKE_OP(sbcd, 8, mm, axy7)
9654 uint src = OPER_A7_PD_8(state);
9655 uint ea = EA_A7_PD_8();
9656 uint dst = m68ki_read_8(state, ea);
9657 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9662 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9663 FLAG_V = res; /* Undefined V behavior */
9666 FLAG_X = FLAG_C = CFLAG_SET;
9667 } else if(res < corf)
9668 FLAG_X = FLAG_C = CFLAG_SET;
9670 FLAG_N = FLAG_X = FLAG_C = 0;
9672 res = MASK_OUT_ABOVE_8(res - corf);
9674 FLAG_V &= ~res; /* Undefined V behavior part II */
9675 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9678 m68ki_write_8(state, ea, res);
9682 M68KMAKE_OP(sbcd, 8, mm, .)
9684 uint src = OPER_AY_PD_8(state);
9685 uint ea = EA_AX_PD_8();
9686 uint dst = m68ki_read_8(state, ea);
9687 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9692 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9693 FLAG_V = res; /* Undefined V behavior */
9696 FLAG_X = FLAG_C = CFLAG_SET;
9697 } else if(res < corf)
9698 FLAG_X = FLAG_C = CFLAG_SET;
9700 FLAG_N = FLAG_X = FLAG_C = 0;
9702 res = MASK_OUT_ABOVE_8(res - corf);
9704 FLAG_V &= ~res; /* Undefined V behavior part II */
9705 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9708 m68ki_write_8(state, ea, res);
9712 M68KMAKE_OP(st, 8, ., d)
9718 M68KMAKE_OP(st, 8, ., .)
9720 m68ki_write_8(state, M68KMAKE_GET_EA_AY_8, 0xff);
9724 M68KMAKE_OP(sf, 8, ., d)
9730 M68KMAKE_OP(sf, 8, ., .)
9732 m68ki_write_8(state, M68KMAKE_GET_EA_AY_8, 0);
9736 M68KMAKE_OP(scc, 8, ., d)
9741 USE_CYCLES(CYC_SCC_R_TRUE);
9748 M68KMAKE_OP(scc, 8, ., .)
9750 m68ki_write_8(state, M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
9754 M68KMAKE_OP(stop, 0, ., .)
9758 uint new_sr = OPER_I_16(state);
9759 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9760 CPU_STOPPED |= STOP_LEVEL_STOP;
9761 m68ki_set_sr(state, new_sr);
9762 if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR])
9763 m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR];
9768 m68ki_exception_privilege_violation(state);
9772 M68KMAKE_OP(sub, 8, er, d)
9775 uint src = MASK_OUT_ABOVE_8(DY);
9776 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9777 uint res = dst - src;
9779 FLAG_N = NFLAG_8(res);
9780 FLAG_X = FLAG_C = CFLAG_8(res);
9781 FLAG_V = VFLAG_SUB_8(src, dst, res);
9782 FLAG_Z = MASK_OUT_ABOVE_8(res);
9784 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9788 M68KMAKE_OP(sub, 8, er, .)
9791 uint src = M68KMAKE_GET_OPER_AY_8;
9792 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9793 uint res = dst - src;
9795 FLAG_N = NFLAG_8(res);
9796 FLAG_X = FLAG_C = CFLAG_8(res);
9797 FLAG_V = VFLAG_SUB_8(src, dst, res);
9798 FLAG_Z = MASK_OUT_ABOVE_8(res);
9800 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9804 M68KMAKE_OP(sub, 16, er, d)
9807 uint src = MASK_OUT_ABOVE_16(DY);
9808 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9809 uint res = dst - src;
9811 FLAG_N = NFLAG_16(res);
9812 FLAG_X = FLAG_C = CFLAG_16(res);
9813 FLAG_V = VFLAG_SUB_16(src, dst, res);
9814 FLAG_Z = MASK_OUT_ABOVE_16(res);
9816 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9820 M68KMAKE_OP(sub, 16, er, a)
9823 uint src = MASK_OUT_ABOVE_16(AY);
9824 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9825 uint res = dst - src;
9827 FLAG_N = NFLAG_16(res);
9828 FLAG_X = FLAG_C = CFLAG_16(res);
9829 FLAG_V = VFLAG_SUB_16(src, dst, res);
9830 FLAG_Z = MASK_OUT_ABOVE_16(res);
9832 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9836 M68KMAKE_OP(sub, 16, er, .)
9839 uint src = M68KMAKE_GET_OPER_AY_16;
9840 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9841 uint res = dst - src;
9843 FLAG_N = NFLAG_16(res);
9844 FLAG_X = FLAG_C = CFLAG_16(res);
9845 FLAG_V = VFLAG_SUB_16(src, dst, res);
9846 FLAG_Z = MASK_OUT_ABOVE_16(res);
9848 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9852 M68KMAKE_OP(sub, 32, er, d)
9857 uint res = dst - src;
9859 FLAG_N = NFLAG_32(res);
9860 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9861 FLAG_V = VFLAG_SUB_32(src, dst, res);
9862 FLAG_Z = MASK_OUT_ABOVE_32(res);
9868 M68KMAKE_OP(sub, 32, er, a)
9873 uint res = dst - src;
9875 FLAG_N = NFLAG_32(res);
9876 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9877 FLAG_V = VFLAG_SUB_32(src, dst, res);
9878 FLAG_Z = MASK_OUT_ABOVE_32(res);
9884 M68KMAKE_OP(sub, 32, er, .)
9887 uint src = M68KMAKE_GET_OPER_AY_32;
9889 uint res = dst - src;
9891 FLAG_N = NFLAG_32(res);
9892 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9893 FLAG_V = VFLAG_SUB_32(src, dst, res);
9894 FLAG_Z = MASK_OUT_ABOVE_32(res);
9900 M68KMAKE_OP(sub, 8, re, .)
9902 uint ea = M68KMAKE_GET_EA_AY_8;
9903 uint src = MASK_OUT_ABOVE_8(DX);
9904 uint dst = m68ki_read_8(state, ea);
9905 uint res = dst - src;
9907 FLAG_N = NFLAG_8(res);
9908 FLAG_Z = MASK_OUT_ABOVE_8(res);
9909 FLAG_X = FLAG_C = CFLAG_8(res);
9910 FLAG_V = VFLAG_SUB_8(src, dst, res);
9912 m68ki_write_8(state, ea, FLAG_Z);
9916 M68KMAKE_OP(sub, 16, re, .)
9918 uint ea = M68KMAKE_GET_EA_AY_16;
9919 uint src = MASK_OUT_ABOVE_16(DX);
9920 uint dst = m68ki_read_16(state, ea);
9921 uint res = dst - src;
9923 FLAG_N = NFLAG_16(res);
9924 FLAG_Z = MASK_OUT_ABOVE_16(res);
9925 FLAG_X = FLAG_C = CFLAG_16(res);
9926 FLAG_V = VFLAG_SUB_16(src, dst, res);
9928 m68ki_write_16(state, ea, FLAG_Z);
9932 M68KMAKE_OP(sub, 32, re, .)
9934 uint ea = M68KMAKE_GET_EA_AY_32;
9936 uint dst = m68ki_read_32(state, ea);
9937 uint res = dst - src;
9939 FLAG_N = NFLAG_32(res);
9940 FLAG_Z = MASK_OUT_ABOVE_32(res);
9941 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9942 FLAG_V = VFLAG_SUB_32(src, dst, res);
9944 m68ki_write_32(state, ea, FLAG_Z);
9948 M68KMAKE_OP(suba, 16, ., d)
9952 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
9956 M68KMAKE_OP(suba, 16, ., a)
9960 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
9964 M68KMAKE_OP(suba, 16, ., .)
9967 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
9969 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9973 M68KMAKE_OP(suba, 32, ., d)
9977 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
9981 M68KMAKE_OP(suba, 32, ., a)
9985 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
9989 M68KMAKE_OP(suba, 32, ., .)
9991 uint src = M68KMAKE_GET_OPER_AY_32;
9994 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9998 M68KMAKE_OP(subi, 8, ., d)
10001 uint src = OPER_I_8(state);
10002 uint dst = MASK_OUT_ABOVE_8(*r_dst);
10003 uint res = dst - src;
10005 FLAG_N = NFLAG_8(res);
10006 FLAG_Z = MASK_OUT_ABOVE_8(res);
10007 FLAG_X = FLAG_C = CFLAG_8(res);
10008 FLAG_V = VFLAG_SUB_8(src, dst, res);
10010 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
10014 M68KMAKE_OP(subi, 8, ., .)
10016 uint src = OPER_I_8(state);
10017 uint ea = M68KMAKE_GET_EA_AY_8;
10018 uint dst = m68ki_read_8(state, ea);
10019 uint res = dst - src;
10021 FLAG_N = NFLAG_8(res);
10022 FLAG_Z = MASK_OUT_ABOVE_8(res);
10023 FLAG_X = FLAG_C = CFLAG_8(res);
10024 FLAG_V = VFLAG_SUB_8(src, dst, res);
10026 m68ki_write_8(state, ea, FLAG_Z);
10030 M68KMAKE_OP(subi, 16, ., d)
10033 uint src = OPER_I_16(state);
10034 uint dst = MASK_OUT_ABOVE_16(*r_dst);
10035 uint res = dst - src;
10037 FLAG_N = NFLAG_16(res);
10038 FLAG_Z = MASK_OUT_ABOVE_16(res);
10039 FLAG_X = FLAG_C = CFLAG_16(res);
10040 FLAG_V = VFLAG_SUB_16(src, dst, res);
10042 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
10046 M68KMAKE_OP(subi, 16, ., .)
10048 uint src = OPER_I_16(state);
10049 uint ea = M68KMAKE_GET_EA_AY_16;
10050 uint dst = m68ki_read_16(state, ea);
10051 uint res = dst - src;
10053 FLAG_N = NFLAG_16(res);
10054 FLAG_Z = MASK_OUT_ABOVE_16(res);
10055 FLAG_X = FLAG_C = CFLAG_16(res);
10056 FLAG_V = VFLAG_SUB_16(src, dst, res);
10058 m68ki_write_16(state, ea, FLAG_Z);
10062 M68KMAKE_OP(subi, 32, ., d)
10065 uint src = OPER_I_32(state);
10067 uint res = dst - src;
10069 FLAG_N = NFLAG_32(res);
10070 FLAG_Z = MASK_OUT_ABOVE_32(res);
10071 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10072 FLAG_V = VFLAG_SUB_32(src, dst, res);
10078 M68KMAKE_OP(subi, 32, ., .)
10080 uint src = OPER_I_32(state);
10081 uint ea = M68KMAKE_GET_EA_AY_32;
10082 uint dst = m68ki_read_32(state, ea);
10083 uint res = dst - src;
10085 FLAG_N = NFLAG_32(res);
10086 FLAG_Z = MASK_OUT_ABOVE_32(res);
10087 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10088 FLAG_V = VFLAG_SUB_32(src, dst, res);
10090 m68ki_write_32(state, ea, FLAG_Z);
10094 M68KMAKE_OP(subq, 8, ., d)
10097 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10098 uint dst = MASK_OUT_ABOVE_8(*r_dst);
10099 uint res = dst - src;
10101 FLAG_N = NFLAG_8(res);
10102 FLAG_Z = MASK_OUT_ABOVE_8(res);
10103 FLAG_X = FLAG_C = CFLAG_8(res);
10104 FLAG_V = VFLAG_SUB_8(src, dst, res);
10106 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
10110 M68KMAKE_OP(subq, 8, ., .)
10112 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10113 uint ea = M68KMAKE_GET_EA_AY_8;
10114 uint dst = m68ki_read_8(state, ea);
10115 uint res = dst - src;
10117 FLAG_N = NFLAG_8(res);
10118 FLAG_Z = MASK_OUT_ABOVE_8(res);
10119 FLAG_X = FLAG_C = CFLAG_8(res);
10120 FLAG_V = VFLAG_SUB_8(src, dst, res);
10122 m68ki_write_8(state, ea, FLAG_Z);
10126 M68KMAKE_OP(subq, 16, ., d)
10129 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10130 uint dst = MASK_OUT_ABOVE_16(*r_dst);
10131 uint res = dst - src;
10133 FLAG_N = NFLAG_16(res);
10134 FLAG_Z = MASK_OUT_ABOVE_16(res);
10135 FLAG_X = FLAG_C = CFLAG_16(res);
10136 FLAG_V = VFLAG_SUB_16(src, dst, res);
10138 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
10142 M68KMAKE_OP(subq, 16, ., a)
10146 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
10150 M68KMAKE_OP(subq, 16, ., .)
10152 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10153 uint ea = M68KMAKE_GET_EA_AY_16;
10154 uint dst = m68ki_read_16(state, ea);
10155 uint res = dst - src;
10157 FLAG_N = NFLAG_16(res);
10158 FLAG_Z = MASK_OUT_ABOVE_16(res);
10159 FLAG_X = FLAG_C = CFLAG_16(res);
10160 FLAG_V = VFLAG_SUB_16(src, dst, res);
10162 m68ki_write_16(state, ea, FLAG_Z);
10166 M68KMAKE_OP(subq, 32, ., d)
10169 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10171 uint res = dst - src;
10173 FLAG_N = NFLAG_32(res);
10174 FLAG_Z = MASK_OUT_ABOVE_32(res);
10175 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10176 FLAG_V = VFLAG_SUB_32(src, dst, res);
10182 M68KMAKE_OP(subq, 32, ., a)
10186 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
10190 M68KMAKE_OP(subq, 32, ., .)
10192 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10193 uint ea = M68KMAKE_GET_EA_AY_32;
10194 uint dst = m68ki_read_32(state, ea);
10195 uint res = dst - src;
10197 FLAG_N = NFLAG_32(res);
10198 FLAG_Z = MASK_OUT_ABOVE_32(res);
10199 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10200 FLAG_V = VFLAG_SUB_32(src, dst, res);
10202 m68ki_write_32(state, ea, FLAG_Z);
10206 M68KMAKE_OP(subx, 8, rr, .)
10209 uint src = MASK_OUT_ABOVE_8(DY);
10210 uint dst = MASK_OUT_ABOVE_8(*r_dst);
10211 uint res = dst - src - XFLAG_AS_1();
10213 FLAG_N = NFLAG_8(res);
10214 FLAG_X = FLAG_C = CFLAG_8(res);
10215 FLAG_V = VFLAG_SUB_8(src, dst, res);
10217 res = MASK_OUT_ABOVE_8(res);
10220 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
10224 M68KMAKE_OP(subx, 16, rr, .)
10227 uint src = MASK_OUT_ABOVE_16(DY);
10228 uint dst = MASK_OUT_ABOVE_16(*r_dst);
10229 uint res = dst - src - XFLAG_AS_1();
10231 FLAG_N = NFLAG_16(res);
10232 FLAG_X = FLAG_C = CFLAG_16(res);
10233 FLAG_V = VFLAG_SUB_16(src, dst, res);
10235 res = MASK_OUT_ABOVE_16(res);
10238 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
10242 M68KMAKE_OP(subx, 32, rr, .)
10247 uint res = dst - src - XFLAG_AS_1();
10249 FLAG_N = NFLAG_32(res);
10250 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10251 FLAG_V = VFLAG_SUB_32(src, dst, res);
10253 res = MASK_OUT_ABOVE_32(res);
10260 M68KMAKE_OP(subx, 8, mm, ax7)
10262 uint src = OPER_AY_PD_8(state);
10263 uint ea = EA_A7_PD_8();
10264 uint dst = m68ki_read_8(state, ea);
10265 uint res = dst - src - XFLAG_AS_1();
10267 FLAG_N = NFLAG_8(res);
10268 FLAG_X = FLAG_C = CFLAG_8(res);
10269 FLAG_V = VFLAG_SUB_8(src, dst, res);
10271 res = MASK_OUT_ABOVE_8(res);
10274 m68ki_write_8(state, ea, res);
10278 M68KMAKE_OP(subx, 8, mm, ay7)
10280 uint src = OPER_A7_PD_8(state);
10281 uint ea = EA_AX_PD_8();
10282 uint dst = m68ki_read_8(state, ea);
10283 uint res = dst - src - XFLAG_AS_1();
10285 FLAG_N = NFLAG_8(res);
10286 FLAG_X = FLAG_C = CFLAG_8(res);
10287 FLAG_V = VFLAG_SUB_8(src, dst, res);
10289 res = MASK_OUT_ABOVE_8(res);
10292 m68ki_write_8(state, ea, res);
10296 M68KMAKE_OP(subx, 8, mm, axy7)
10298 uint src = OPER_A7_PD_8(state);
10299 uint ea = EA_A7_PD_8();
10300 uint dst = m68ki_read_8(state, ea);
10301 uint res = dst - src - XFLAG_AS_1();
10303 FLAG_N = NFLAG_8(res);
10304 FLAG_X = FLAG_C = CFLAG_8(res);
10305 FLAG_V = VFLAG_SUB_8(src, dst, res);
10307 res = MASK_OUT_ABOVE_8(res);
10310 m68ki_write_8(state, ea, res);
10314 M68KMAKE_OP(subx, 8, mm, .)
10316 uint src = OPER_AY_PD_8(state);
10317 uint ea = EA_AX_PD_8();
10318 uint dst = m68ki_read_8(state, ea);
10319 uint res = dst - src - XFLAG_AS_1();
10321 FLAG_N = NFLAG_8(res);
10322 FLAG_X = FLAG_C = CFLAG_8(res);
10323 FLAG_V = VFLAG_SUB_8(src, dst, res);
10325 res = MASK_OUT_ABOVE_8(res);
10328 m68ki_write_8(state, ea, res);
10332 M68KMAKE_OP(subx, 16, mm, .)
10334 uint src = OPER_AY_PD_16(state);
10335 uint ea = EA_AX_PD_16();
10336 uint dst = m68ki_read_16(state, ea);
10337 uint res = dst - src - XFLAG_AS_1();
10339 FLAG_N = NFLAG_16(res);
10340 FLAG_X = FLAG_C = CFLAG_16(res);
10341 FLAG_V = VFLAG_SUB_16(src, dst, res);
10343 res = MASK_OUT_ABOVE_16(res);
10346 m68ki_write_16(state, ea, res);
10350 M68KMAKE_OP(subx, 32, mm, .)
10352 uint src = OPER_AY_PD_32(state);
10353 uint ea = EA_AX_PD_32();
10354 uint dst = m68ki_read_32(state, ea);
10355 uint res = dst - src - XFLAG_AS_1();
10357 FLAG_N = NFLAG_32(res);
10358 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10359 FLAG_V = VFLAG_SUB_32(src, dst, res);
10361 res = MASK_OUT_ABOVE_32(res);
10364 m68ki_write_32(state, ea, res);
10368 M68KMAKE_OP(swap, 32, ., .)
10372 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
10373 *r_dst = (*r_dst>>16) | FLAG_Z;
10376 FLAG_N = NFLAG_32(*r_dst);
10377 FLAG_C = CFLAG_CLEAR;
10378 FLAG_V = VFLAG_CLEAR;
10382 M68KMAKE_OP(tas, 8, ., d)
10386 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
10387 FLAG_N = NFLAG_8(*r_dst);
10388 FLAG_V = VFLAG_CLEAR;
10389 FLAG_C = CFLAG_CLEAR;
10394 M68KMAKE_OP(tas, 8, ., .)
10396 uint ea = M68KMAKE_GET_EA_AY_8;
10397 uint dst = m68ki_read_8(state, ea);
10398 uint allow_writeback;
10401 FLAG_N = NFLAG_8(dst);
10402 FLAG_V = VFLAG_CLEAR;
10403 FLAG_C = CFLAG_CLEAR;
10405 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
10406 disabled in order to function properly. Some Amiga software may also rely
10407 on this, but only when accessing specific addresses so additional functionality
10409 allow_writeback = m68ki_tas_callback();
10411 if (allow_writeback==1) m68ki_write_8(state, ea, dst | 0x80);
10415 M68KMAKE_OP(trap, 0, ., .)
10417 /* Trap#n stacks exception frame type 0 */
10418 m68ki_exception_trapN(state, EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
10422 M68KMAKE_OP(trapt, 0, ., .)
10424 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10426 m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
10429 m68ki_exception_illegal(state);
10433 M68KMAKE_OP(trapt, 16, ., .)
10435 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10437 // TODO: review this... as mame is not using it...
10438 REG_PC += 2; // JFF else stackframe & return addresses are incorrect
10439 m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
10442 m68ki_exception_illegal(state);
10446 M68KMAKE_OP(trapt, 32, ., .)
10448 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10450 // TODO: review this... as mame is not using it...
10451 REG_PC += 4; // JFF else stackframe & return addresses are incorrect
10452 m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
10455 m68ki_exception_illegal(state);
10459 M68KMAKE_OP(trapf, 0, ., .)
10461 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10465 m68ki_exception_illegal(state);
10469 M68KMAKE_OP(trapf, 16, ., .)
10471 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10476 m68ki_exception_illegal(state);
10480 M68KMAKE_OP(trapf, 32, ., .)
10482 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10487 m68ki_exception_illegal(state);
10491 M68KMAKE_OP(trapcc, 0, ., .)
10493 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10496 m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
10499 m68ki_exception_illegal(state);
10503 M68KMAKE_OP(trapcc, 16, ., .)
10505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10507 // TODO: review this... as mame is not using it...
10508 REG_PC += 2; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10511 m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
10517 m68ki_exception_illegal(state);
10521 M68KMAKE_OP(trapcc, 32, ., .)
10523 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10525 // TODO: review this... as mame is not using it...
10526 REG_PC += 4; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10529 m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
10534 m68ki_exception_illegal(state);
10538 M68KMAKE_OP(trapv, 0, ., .)
10544 m68ki_exception_trap(state, EXCEPTION_TRAPV); /* HJB 990403 */
10548 M68KMAKE_OP(tst, 8, ., d)
10550 uint res = MASK_OUT_ABOVE_8(DY);
10552 FLAG_N = NFLAG_8(res);
10554 FLAG_V = VFLAG_CLEAR;
10555 FLAG_C = CFLAG_CLEAR;
10559 M68KMAKE_OP(tst, 8, ., .)
10561 uint res = M68KMAKE_GET_OPER_AY_8;
10563 FLAG_N = NFLAG_8(res);
10565 FLAG_V = VFLAG_CLEAR;
10566 FLAG_C = CFLAG_CLEAR;
10570 M68KMAKE_OP(tst, 8, ., pcdi)
10572 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10574 uint res = OPER_PCDI_8(state);
10576 FLAG_N = NFLAG_8(res);
10578 FLAG_V = VFLAG_CLEAR;
10579 FLAG_C = CFLAG_CLEAR;
10582 m68ki_exception_illegal(state);
10586 M68KMAKE_OP(tst, 8, ., pcix)
10588 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10590 uint res = OPER_PCIX_8(state);
10592 FLAG_N = NFLAG_8(res);
10594 FLAG_V = VFLAG_CLEAR;
10595 FLAG_C = CFLAG_CLEAR;
10598 m68ki_exception_illegal(state);
10602 M68KMAKE_OP(tst, 8, ., i)
10604 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10606 uint res = OPER_I_8(state);
10608 FLAG_N = NFLAG_8(res);
10610 FLAG_V = VFLAG_CLEAR;
10611 FLAG_C = CFLAG_CLEAR;
10614 m68ki_exception_illegal(state);
10618 M68KMAKE_OP(tst, 16, ., d)
10620 uint res = MASK_OUT_ABOVE_16(DY);
10622 FLAG_N = NFLAG_16(res);
10624 FLAG_V = VFLAG_CLEAR;
10625 FLAG_C = CFLAG_CLEAR;
10629 M68KMAKE_OP(tst, 16, ., a)
10631 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10633 uint res = MAKE_INT_16(AY);
10635 FLAG_N = NFLAG_16(res);
10637 FLAG_V = VFLAG_CLEAR;
10638 FLAG_C = CFLAG_CLEAR;
10641 m68ki_exception_illegal(state);
10645 M68KMAKE_OP(tst, 16, ., .)
10647 uint res = M68KMAKE_GET_OPER_AY_16;
10649 FLAG_N = NFLAG_16(res);
10651 FLAG_V = VFLAG_CLEAR;
10652 FLAG_C = CFLAG_CLEAR;
10656 M68KMAKE_OP(tst, 16, ., pcdi)
10658 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10660 uint res = OPER_PCDI_16(state);
10662 FLAG_N = NFLAG_16(res);
10664 FLAG_V = VFLAG_CLEAR;
10665 FLAG_C = CFLAG_CLEAR;
10668 m68ki_exception_illegal(state);
10672 M68KMAKE_OP(tst, 16, ., pcix)
10674 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10676 uint res = OPER_PCIX_16(state);
10678 FLAG_N = NFLAG_16(res);
10680 FLAG_V = VFLAG_CLEAR;
10681 FLAG_C = CFLAG_CLEAR;
10684 m68ki_exception_illegal(state);
10688 M68KMAKE_OP(tst, 16, ., i)
10690 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10692 uint res = OPER_I_16(state);
10694 FLAG_N = NFLAG_16(res);
10696 FLAG_V = VFLAG_CLEAR;
10697 FLAG_C = CFLAG_CLEAR;
10700 m68ki_exception_illegal(state);
10704 M68KMAKE_OP(tst, 32, ., d)
10708 FLAG_N = NFLAG_32(res);
10710 FLAG_V = VFLAG_CLEAR;
10711 FLAG_C = CFLAG_CLEAR;
10715 M68KMAKE_OP(tst, 32, ., a)
10717 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10721 FLAG_N = NFLAG_32(res);
10723 FLAG_V = VFLAG_CLEAR;
10724 FLAG_C = CFLAG_CLEAR;
10727 m68ki_exception_illegal(state);
10731 M68KMAKE_OP(tst, 32, ., .)
10733 uint res = M68KMAKE_GET_OPER_AY_32;
10735 FLAG_N = NFLAG_32(res);
10737 FLAG_V = VFLAG_CLEAR;
10738 FLAG_C = CFLAG_CLEAR;
10742 M68KMAKE_OP(tst, 32, ., pcdi)
10744 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10746 uint res = OPER_PCDI_32(state);
10748 FLAG_N = NFLAG_32(res);
10750 FLAG_V = VFLAG_CLEAR;
10751 FLAG_C = CFLAG_CLEAR;
10754 m68ki_exception_illegal(state);
10758 M68KMAKE_OP(tst, 32, ., pcix)
10760 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10762 uint res = OPER_PCIX_32(state);
10764 FLAG_N = NFLAG_32(res);
10766 FLAG_V = VFLAG_CLEAR;
10767 FLAG_C = CFLAG_CLEAR;
10770 m68ki_exception_illegal(state);
10774 M68KMAKE_OP(tst, 32, ., i)
10776 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10778 uint res = OPER_I_32(state);
10780 FLAG_N = NFLAG_32(res);
10782 FLAG_V = VFLAG_CLEAR;
10783 FLAG_C = CFLAG_CLEAR;
10786 m68ki_exception_illegal(state);
10790 M68KMAKE_OP(unlk, 32, ., a7)
10792 REG_A[7] = m68ki_read_32(state, REG_A[7]);
10796 M68KMAKE_OP(unlk, 32, ., .)
10801 *r_dst = m68ki_pull_32(state);
10805 M68KMAKE_OP(unpk, 16, rr, .)
10807 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10809 /* Note: DX and DY are reversed in Motorola's docs */
10813 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state)) & 0xffff);
10816 m68ki_exception_illegal(state);
10820 M68KMAKE_OP(unpk, 16, mm, ax7)
10822 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10824 /* Note: AX and AY are reversed in Motorola's docs */
10825 uint src = OPER_AY_PD_8(state);
10828 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
10829 ea_dst = EA_A7_PD_8();
10830 m68ki_write_8(state, ea_dst, src & 0xff);
10831 ea_dst = EA_A7_PD_8();
10832 m68ki_write_8(state, ea_dst, (src >> 8) & 0xff);
10835 m68ki_exception_illegal(state);
10839 M68KMAKE_OP(unpk, 16, mm, ay7)
10841 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10843 /* Note: AX and AY are reversed in Motorola's docs */
10844 uint src = OPER_A7_PD_8(state);
10847 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
10848 ea_dst = EA_AX_PD_8();
10849 m68ki_write_8(state, ea_dst, src & 0xff);
10850 ea_dst = EA_AX_PD_8();
10851 m68ki_write_8(state, ea_dst, (src >> 8) & 0xff);
10854 m68ki_exception_illegal(state);
10858 M68KMAKE_OP(unpk, 16, mm, axy7)
10860 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10862 uint src = OPER_A7_PD_8(state);
10865 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
10866 ea_dst = EA_A7_PD_8();
10867 m68ki_write_8(state, ea_dst, src & 0xff);
10868 ea_dst = EA_A7_PD_8();
10869 m68ki_write_8(state, ea_dst, (src >> 8) & 0xff);
10872 m68ki_exception_illegal(state);
10876 M68KMAKE_OP(unpk, 16, mm, .)
10878 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10880 /* Note: AX and AY are reversed in Motorola's docs */
10881 uint src = OPER_AY_PD_8(state);
10884 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
10885 ea_dst = EA_AX_PD_8();
10886 m68ki_write_8(state, ea_dst, src & 0xff);
10887 ea_dst = EA_AX_PD_8();
10888 m68ki_write_8(state, ea_dst, (src >> 8) & 0xff);
10891 m68ki_exception_illegal(state);
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projects / pistorm / blob