6 /* ======================================================================== */
7 /* ========================= LICENSING & COPYRIGHT ======================== */
8 /* ======================================================================== */
13 * A portable Motorola M680x0 processor emulation engine.
14 * Copyright Karl Stenerud. All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a copy
17 * of this software and associated documentation files (the "Software"), to deal
18 * in the Software without restriction, including without limitation the rights
19 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
20 * copies of the Software, and to permit persons to whom the Software is
21 * furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice shall be included in
24 * all copies or substantial portions of the Software.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
28 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
29 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
30 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
31 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 /* Special thanks to Bart Trzynadlowski for his insight into the
36 * undocumented features of this chip:
38 * http://dynarec.com/~bart/files/68knotes.txt
42 /* Input file for m68kmake
43 * -----------------------
45 * All sections begin with 80 X's in a row followed by an end-of-line
47 * After this, m68kmake will expect to find one of the following section
49 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
50 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
51 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
52 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
53 * M68KMAKE_TABLE_BODY - the table itself
54 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
55 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
56 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
58 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
59 * M68KMAKE_TABLE_BODY must be second last in the file.
61 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
62 * primitives themselves. Each opcode handler begins with:
63 * M68KMAKE_OP(A, B, C, D)
65 * where A is the opcode handler name, B is the size of the operation,
66 * C denotes any special processing mode, and D denotes a specific
68 * For C and D where nothing is specified, use "."
71 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
72 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
73 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
75 * All opcode handler primitives end with a closing curly brace "}" at column 1
77 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
78 * and do not put a closing curly brace at column 1 unless it is
79 * marking the end of the handler!
81 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
82 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
83 * opcode handlers to handle variations in the opcode handler.
84 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
85 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
86 * be interpreted on instructions where the corresponding table entry
87 * specifies multiple effective addressing modes.
89 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
91 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
92 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
93 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
96 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
97 M68KMAKE_PROTOTYPE_HEADER
99 #ifndef M68KOPS__HEADER
100 #define M68KOPS__HEADER
102 /* ======================================================================== */
103 /* ============================ OPCODE HANDLERS =========================== */
104 /* ======================================================================== */
108 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
109 M68KMAKE_PROTOTYPE_FOOTER
112 /* Build the opcode handler table */
113 void m68ki_build_opcode_table(void);
115 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
116 extern unsigned char m68ki_cycles[][0x10000];
119 /* ======================================================================== */
120 /* ============================== END OF FILE ============================= */
121 /* ======================================================================== */
123 #endif /* M68KOPS__HEADER */
127 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
128 M68KMAKE_TABLE_HEADER
130 /* ======================================================================== */
131 /* ========================= OPCODE TABLE BUILDER ========================= */
132 /* ======================================================================== */
137 #define NUM_CPU_TYPES 5
139 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
140 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
142 /* This is used to generate the opcode handler jump table */
145 void (*opcode_handler)(void); /* handler function */
146 unsigned int mask; /* mask on opcode */
147 unsigned int match; /* what to match after masking */
148 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
149 } opcode_handler_struct;
152 /* Opcode handler table */
153 static const opcode_handler_struct m68k_opcode_handler_table[] =
155 /* function mask match 000 010 020 040 */
159 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
160 M68KMAKE_TABLE_FOOTER
162 {0, 0, 0, {0, 0, 0, 0, 0}}
166 /* Build the opcode handler jump table */
167 void m68ki_build_opcode_table(void)
169 const opcode_handler_struct *ostruct;
176 for(i = 0; i < 0x10000; i++)
178 /* default to illegal */
179 m68ki_instruction_jump_table[i] = m68k_op_illegal;
180 for(k=0;k<NUM_CPU_TYPES;k++)
181 m68ki_cycles[k][i] = 0;
184 ostruct = m68k_opcode_handler_table;
185 while(ostruct->mask != 0xff00)
187 for(i = 0;i < 0x10000;i++)
189 if((i & ostruct->mask) == ostruct->match)
191 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
192 for(k=0;k<NUM_CPU_TYPES;k++)
193 m68ki_cycles[k][i] = ostruct->cycles[k];
198 while(ostruct->mask == 0xff00)
200 for(i = 0;i <= 0xff;i++)
202 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
203 for(k=0;k<NUM_CPU_TYPES;k++)
204 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
208 while(ostruct->mask == 0xf1f8)
214 instr = ostruct->match | (i << 9) | j;
215 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
216 for(k=0;k<NUM_CPU_TYPES;k++)
217 m68ki_cycles[k][instr] = ostruct->cycles[k];
218 // For all shift operations with known shift distance (encoded in instruction word)
219 if((instr & 0xf000) == 0xe000 && (!(instr & 0x20)))
221 // On the 68000 and 68010 shift distance affect execution time.
222 // Add the cycle cost of shifting; 2 times the shift distance
223 cycle_cost = ((((i-1)&7)+1)<<1);
224 m68ki_cycles[0][instr] += cycle_cost;
225 m68ki_cycles[1][instr] += cycle_cost;
226 // On the 68020 shift distance does not affect execution time
227 m68ki_cycles[2][instr] += 0;
233 while(ostruct->mask == 0xfff0)
235 for(i = 0;i <= 0x0f;i++)
237 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
238 for(k=0;k<NUM_CPU_TYPES;k++)
239 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
243 while(ostruct->mask == 0xf1ff)
245 for(i = 0;i <= 0x07;i++)
247 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
248 for(k=0;k<NUM_CPU_TYPES;k++)
249 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
253 while(ostruct->mask == 0xfff8)
255 for(i = 0;i <= 0x07;i++)
257 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
258 for(k=0;k<NUM_CPU_TYPES;k++)
259 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
263 while(ostruct->mask == 0xffff)
265 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
266 for(k=0;k<NUM_CPU_TYPES;k++)
267 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
273 /* ======================================================================== */
274 /* ============================== END OF FILE ============================= */
275 /* ======================================================================== */
279 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
280 M68KMAKE_OPCODE_HANDLER_HEADER
284 extern void m68040_fpu_op0(void);
285 extern void m68040_fpu_op1(void);
286 extern void m68881_mmu_ops();
288 /* ======================================================================== */
289 /* ========================= INSTRUCTION HANDLERS ========================= */
290 /* ======================================================================== */
294 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
295 M68KMAKE_OPCODE_HANDLER_FOOTER
297 /* ======================================================================== */
298 /* ============================== END OF FILE ============================= */
299 /* ======================================================================== */
303 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
306 The following table is arranged as follows:
308 name: Opcode mnemonic
312 spec proc: Special processing mode:
316 rr: register to register
318 er: effective address to register
319 re: register to effective address
320 dd: data register to data register
321 da: data register to address register
322 aa: address register to address register
323 cr: control register to register
324 rc: register to control register
325 toc: to condition code register
326 tos: to status register
327 tou: to user stack pointer
328 frc: from condition code register
329 frs: from status register
330 fru: from user stack pointer
331 * for move.x, the special processing mode is a specific
332 destination effective addressing mode.
334 spec ea: Specific effective addressing mode:
339 ai: address register indirect
340 pi: address register indirect with postincrement
341 pd: address register indirect with predecrement
342 di: address register indirect with displacement
343 ix: address register indirect with index
344 aw: absolute word address
345 al: absolute long address
346 pcdi: program counter relative with displacement
347 pcix: program counter relative with index
348 a7: register specified in instruction is A7
349 ax7: register field X of instruction is A7
350 ay7: register field Y of instruction is A7
351 axy7: register fields X and Y of instruction are A7
353 bit pattern: Pattern to recognize this opcode. "." means don't care.
355 allowed ea: List of allowed addressing modes:
357 A: address register indirect
358 +: ARI (address register indirect) with postincrement
359 -: ARI with predecrement
360 D: ARI with displacement
362 W: absolute word address
363 L: absolute long address
364 d: program counter indirect with displacement
365 x: program counter indirect with index
367 mode: CPU operating mode for each cpu type. U = user or supervisor,
368 S = supervisor only, "." = opcode not present.
370 cpu cycles: Base number of cycles required to execute this opcode on the
372 Use "." if CPU does not have this opcode.
376 spec spec allowed ea mode cpu cycles
377 name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 000 010 020 030 040 comments
378 ====== ==== ==== ==== ================ ========== = = = = = === === === === === =============
380 1010 0 . . 1010............ .......... U U U U U 4 4 4 4 4
381 1111 0 . . 1111............ .......... U U U U U 4 4 4 4 4
382 040fpu0 32 . . 11110010........ .......... . . . . U . . . . 0
383 040fpu1 32 . . 11110011........ .......... . . . . U . . . . 0
384 abcd 8 rr . 1100...100000... .......... U U U U U 6 6 4 4 4
385 abcd 8 mm ax7 1100111100001... .......... U U U U U 18 18 16 16 16
386 abcd 8 mm ay7 1100...100001111 .......... U U U U U 18 18 16 16 16
387 abcd 8 mm axy7 1100111100001111 .......... U U U U U 18 18 16 16 16
388 abcd 8 mm . 1100...100001... .......... U U U U U 18 18 16 16 16
389 add 8 er d 1101...000000... .......... U U U U U 4 4 2 2 2
390 add 8 er . 1101...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
391 add 16 er d 1101...001000... .......... U U U U U 4 4 2 2 2
392 add 16 er a 1101...001001... .......... U U U U U 4 4 2 2 2
393 add 16 er . 1101...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
394 add 32 er d 1101...010000... .......... U U U U U 6 6 2 2 2
395 add 32 er a 1101...010001... .......... U U U U U 6 6 2 2 2
396 add 32 er . 1101...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
397 add 8 re . 1101...100...... A+-DXWL... U U U U U 8 8 4 4 4
398 add 16 re . 1101...101...... A+-DXWL... U U U U U 8 8 4 4 4
399 add 32 re . 1101...110...... A+-DXWL... U U U U U 12 12 4 4 4
400 adda 16 . d 1101...011000... .......... U U U U U 8 8 2 2 2
401 adda 16 . a 1101...011001... .......... U U U U U 8 8 2 2 2
402 adda 16 . . 1101...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
403 adda 32 . d 1101...111000... .......... U U U U U 6 6 2 2 2
404 adda 32 . a 1101...111001... .......... U U U U U 6 6 2 2 2
405 adda 32 . . 1101...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
406 addi 8 . d 0000011000000... .......... U U U U U 8 8 2 2 2
407 addi 8 . . 0000011000...... A+-DXWL... U U U U U 12 12 4 4 4
408 addi 16 . d 0000011001000... .......... U U U U U 8 8 2 2 2
409 addi 16 . . 0000011001...... A+-DXWL... U U U U U 12 12 4 4 4
410 addi 32 . d 0000011010000... .......... U U U U U 16 14 2 2 2
411 addi 32 . . 0000011010...... A+-DXWL... U U U U U 20 20 4 4 4
412 addq 8 . d 0101...000000... .......... U U U U U 4 4 2 2 2
413 addq 8 . . 0101...000...... A+-DXWL... U U U U U 8 8 4 4 4
414 addq 16 . d 0101...001000... .......... U U U U U 4 4 2 2 2
415 addq 16 . a 0101...001001... .......... U U U U U 4 4 2 2 2
416 addq 16 . . 0101...001...... A+-DXWL... U U U U U 8 8 4 4 4
417 addq 32 . d 0101...010000... .......... U U U U U 8 8 2 2 2
418 addq 32 . a 0101...010001... .......... U U U U U 8 8 2 2 2
419 addq 32 . . 0101...010...... A+-DXWL... U U U U U 12 12 4 4 4
420 addx 8 rr . 1101...100000... .......... U U U U U 4 4 2 2 2
421 addx 16 rr . 1101...101000... .......... U U U U U 4 4 2 2 2
422 addx 32 rr . 1101...110000... .......... U U U U U 8 6 2 2 2
423 addx 8 mm ax7 1101111100001... .......... U U U U U 18 18 12 12 12
424 addx 8 mm ay7 1101...100001111 .......... U U U U U 18 18 12 12 12
425 addx 8 mm axy7 1101111100001111 .......... U U U U U 18 18 12 12 12
426 addx 8 mm . 1101...100001... .......... U U U U U 18 18 12 12 12
427 addx 16 mm . 1101...101001... .......... U U U U U 18 18 12 12 12
428 addx 32 mm . 1101...110001... .......... U U U U U 30 30 12 12 12
429 and 8 er d 1100...000000... .......... U U U U U 4 4 2 2 2
430 and 8 er . 1100...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
431 and 16 er d 1100...001000... .......... U U U U U 4 4 2 2 2
432 and 16 er . 1100...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
433 and 32 er d 1100...010000... .......... U U U U U 6 6 2 2 2
434 and 32 er . 1100...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
435 and 8 re . 1100...100...... A+-DXWL... U U U U U 8 8 4 4 4
436 and 16 re . 1100...101...... A+-DXWL... U U U U U 8 8 4 4 4
437 and 32 re . 1100...110...... A+-DXWL... U U U U U 12 12 4 4 4
438 andi 16 toc . 0000001000111100 .......... U U U U U 20 16 12 12 12
439 andi 16 tos . 0000001001111100 .......... S S S S S 20 16 12 12 12
440 andi 8 . d 0000001000000... .......... U U U U U 8 8 2 2 2
441 andi 8 . . 0000001000...... A+-DXWL... U U U U U 12 12 4 4 4
442 andi 16 . d 0000001001000... .......... U U U U U 8 8 2 2 2
443 andi 16 . . 0000001001...... A+-DXWL... U U U U U 12 12 4 4 4
444 andi 32 . d 0000001010000... .......... U U U U U 14 14 2 2 2
445 andi 32 . . 0000001010...... A+-DXWL... U U U U U 20 20 4 4 4
446 asr 8 s . 1110...000000... .......... U U U U U 6 6 6 6 6
447 asr 16 s . 1110...001000... .......... U U U U U 6 6 6 6 6
448 asr 32 s . 1110...010000... .......... U U U U U 8 8 6 6 6
449 asr 8 r . 1110...000100... .......... U U U U U 6 6 6 6 6
450 asr 16 r . 1110...001100... .......... U U U U U 6 6 6 6 6
451 asr 32 r . 1110...010100... .......... U U U U U 8 8 6 6 6
452 asr 16 . . 1110000011...... A+-DXWL... U U U U U 8 8 5 5 5
453 asl 8 s . 1110...100000... .......... U U U U U 6 6 8 8 8
454 asl 16 s . 1110...101000... .......... U U U U U 6 6 8 8 8
455 asl 32 s . 1110...110000... .......... U U U U U 8 8 8 8 8
456 asl 8 r . 1110...100100... .......... U U U U U 6 6 8 8 8
457 asl 16 r . 1110...101100... .......... U U U U U 6 6 8 8 8
458 asl 32 r . 1110...110100... .......... U U U U U 8 8 8 8 8
459 asl 16 . . 1110000111...... A+-DXWL... U U U U U 8 8 6 6 6
460 bcc 8 . . 0110............ .......... U U U U U 10 10 6 6 6
461 bcc 16 . . 0110....00000000 .......... U U U U U 10 10 6 6 6
462 bcc 32 . . 0110....11111111 .......... U U U U U 10 10 6 6 6
463 bchg 8 r . 0000...101...... A+-DXWL... U U U U U 8 8 4 4 4
464 bchg 32 r d 0000...101000... .......... U U U U U 8 8 4 4 4
465 bchg 8 s . 0000100001...... A+-DXWL... U U U U U 12 12 4 4 4
466 bchg 32 s d 0000100001000... .......... U U U U U 12 12 4 4 4
467 bclr 8 r . 0000...110...... A+-DXWL... U U U U U 8 10 4 4 4
468 bclr 32 r d 0000...110000... .......... U U U U U 10 10 4 4 4
469 bclr 8 s . 0000100010...... A+-DXWL... U U U U U 12 12 4 4 4
470 bclr 32 s d 0000100010000... .......... U U U U U 14 14 4 4 4
471 bfchg 32 . d 1110101011000... .......... . . U U U . . 12 12 12 timing not quite correct
472 bfchg 32 . . 1110101011...... A..DXWL... . . U U U . . 20 20 20
473 bfclr 32 . d 1110110011000... .......... . . U U U . . 12 12 12
474 bfclr 32 . . 1110110011...... A..DXWL... . . U U U . . 20 20 20
475 bfexts 32 . d 1110101111000... .......... . . U U U . . 8 8 8
476 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U . . 15 15 15
477 bfextu 32 . d 1110100111000... .......... . . U U U . . 8 8 8
478 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U . . 15 15 15
479 bfffo 32 . d 1110110111000... .......... . . U U U . . 18 18 18
480 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U . . 28 28 28
481 bfins 32 . d 1110111111000... .......... . . U U U . . 10 10 10
482 bfins 32 . . 1110111111...... A..DXWL... . . U U U . . 17 17 17
483 bfset 32 . d 1110111011000... .......... . . U U U . . 12 12 12
484 bfset 32 . . 1110111011...... A..DXWL... . . U U U . . 20 20 20
485 bftst 32 . d 1110100011000... .......... . . U U U . . 6 6 6
486 bftst 32 . . 1110100011...... A..DXWLdx. . . U U U . . 13 13 13
487 bkpt 0 . . 0100100001001... .......... . U U U U . 10 10 10 10
488 bra 8 . . 01100000........ .......... U U U U U 10 10 10 10 10
489 bra 16 . . 0110000000000000 .......... U U U U U 10 10 10 10 10
490 bra 32 . . 0110000011111111 .......... U U U U U 10 10 10 10 10
491 bset 32 r d 0000...111000... .......... U U U U U 8 8 4 4 4
492 bset 8 r . 0000...111...... A+-DXWL... U U U U U 8 8 4 4 4
493 bset 8 s . 0000100011...... A+-DXWL... U U U U U 12 12 4 4 4
494 bset 32 s d 0000100011000... .......... U U U U U 12 12 4 4 4
495 bsr 8 . . 01100001........ .......... U U U U U 18 18 7 7 7
496 bsr 16 . . 0110000100000000 .......... U U U U U 18 18 7 7 7
497 bsr 32 . . 0110000111111111 .......... U U U U U 18 18 7 7 7
498 btst 8 r . 0000...100...... A+-DXWLdxI U U U U U 4 4 4 4 4
499 btst 32 r d 0000...100000... .......... U U U U U 6 6 4 4 4
500 btst 8 s . 0000100000...... A+-DXWLdx. U U U U U 8 8 4 4 4
501 btst 32 s d 0000100000000... .......... U U U U U 10 10 4 4 4
502 callm 32 . . 0000011011...... A..DXWLdx. . . U U U . . 60 60 60 not properly emulated
503 cas 8 . . 0000101011...... A+-DXWL... . . U U U . . 12 12 12
504 cas 16 . . 0000110011...... A+-DXWL... . . U U U . . 12 12 12
505 cas 32 . . 0000111011...... A+-DXWL... . . U U U . . 12 12 12
506 cas2 16 . . 0000110011111100 .......... . . U U U . . 12 12 12
507 cas2 32 . . 0000111011111100 .......... . . U U U . . 12 12 12
508 chk 16 . d 0100...110000... .......... U U U U U 10 8 8 8 8
509 chk 16 . . 0100...110...... A+-DXWLdxI U U U U U 10 8 8 8 8
510 chk 32 . d 0100...100000... .......... . . U U U . . 8 8 8
511 chk 32 . . 0100...100...... A+-DXWLdxI . . U U U . . 8 8 8
512 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U . . 23 23 23
513 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U . . 23 23 23
514 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U . . 18 18 18
515 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U . . 23 23 23
516 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U . . 23 23 23
517 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U . . 18 18 18
518 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U . . 23 23 23
519 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U . . 23 23 23
520 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U . . 18 18 18
521 clr 8 . d 0100001000000... .......... U U U U U 4 4 2 2 2
522 clr 8 . . 0100001000...... A+-DXWL... U U U U U 8 4 4 4 4
523 clr 16 . d 0100001001000... .......... U U U U U 4 4 2 2 2
524 clr 16 . . 0100001001...... A+-DXWL... U U U U U 8 4 4 4 4
525 clr 32 . d 0100001010000... .......... U U U U U 6 6 2 2 2
526 clr 32 . . 0100001010...... A+-DXWL... U U U U U 12 6 4 4 4
527 cmp 8 . d 1011...000000... .......... U U U U U 4 4 2 2 2
528 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
529 cmp 16 . d 1011...001000... .......... U U U U U 4 4 2 2 2
530 cmp 16 . a 1011...001001... .......... U U U U U 4 4 2 2 2
531 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
532 cmp 32 . d 1011...010000... .......... U U U U U 6 6 2 2 2
533 cmp 32 . a 1011...010001... .......... U U U U U 6 6 2 2 2
534 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
535 cmpa 16 . d 1011...011000... .......... U U U U U 6 6 4 4 4
536 cmpa 16 . a 1011...011001... .......... U U U U U 6 6 4 4 4
537 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U 6 6 4 4 4
538 cmpa 32 . d 1011...111000... .......... U U U U U 6 6 4 4 4
539 cmpa 32 . a 1011...111001... .......... U U U U U 6 6 4 4 4
540 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U 6 6 4 4 4
541 cmpi 8 . d 0000110000000... .......... U U U U U 8 8 2 2 2
542 cmpi 8 . . 0000110000...... A+-DXWL... U U U U U 8 8 2 2 2
543 cmpi 8 . pcdi 0000110000111010 .......... . . U U U . . 7 7 7
544 cmpi 8 . pcix 0000110000111011 .......... . . U U U . . 9 9 9
545 cmpi 16 . d 0000110001000... .......... U U U U U 8 8 2 2 2
546 cmpi 16 . . 0000110001...... A+-DXWL... U U U U U 8 8 2 2 2
547 cmpi 16 . pcdi 0000110001111010 .......... . . U U U . . 7 7 7
548 cmpi 16 . pcix 0000110001111011 .......... . . U U U . . 9 9 9
549 cmpi 32 . d 0000110010000... .......... U U U U U 14 12 2 2 2
550 cmpi 32 . . 0000110010...... A+-DXWL... U U U U U 12 12 2 2 2
551 cmpi 32 . pcdi 0000110010111010 .......... . . U U U . . 7 7 7
552 cmpi 32 . pcix 0000110010111011 .......... . . U U U . . 9 9 9
553 cmpm 8 . ax7 1011111100001... .......... U U U U U 12 12 9 9 9
554 cmpm 8 . ay7 1011...100001111 .......... U U U U U 12 12 9 9 9
555 cmpm 8 . axy7 1011111100001111 .......... U U U U U 12 12 9 9 9
556 cmpm 8 . . 1011...100001... .......... U U U U U 12 12 9 9 9
557 cmpm 16 . . 1011...101001... .......... U U U U U 12 12 9 9 9
558 cmpm 32 . . 1011...110001... .......... U U U U U 20 20 9 9 9
559 cpbcc 32 . . 1111...01....... .......... . . U U . . . 4 4 . unemulated
560 cpdbcc 32 . . 1111...001001... .......... . . U U . . . 4 4 . unemulated
561 cpgen 32 . . 1111...000...... .......... . . U U . . . 4 4 . unemulated
562 cpscc 32 . . 1111...001...... .......... . . U U . . . 4 4 . unemulated
563 cptrapcc 32 . . 1111...001111... .......... . . U U . . . 4 4 . unemulated
564 dbt 16 . . 0101000011001... .......... U U U U U 12 12 6 6 6
565 dbf 16 . . 0101000111001... .......... U U U U U 12 12 6 6 6
566 dbcc 16 . . 0101....11001... .......... U U U U U 12 12 6 6 6
567 divs 16 . d 1000...111000... .......... U U U U U 158 122 56 56 56
568 divs 16 . . 1000...111...... A+-DXWLdxI U U U U U 158 122 56 56 56
569 divu 16 . d 1000...011000... .......... U U U U U 140 108 44 44 44
570 divu 16 . . 1000...011...... A+-DXWLdxI U U U U U 140 108 44 44 44
571 divl 32 . d 0100110001000... .......... . . U U U . . 84 84 84
572 divl 32 . . 0100110001...... A+-DXWLdxI . . U U U . . 84 84 84
573 eor 8 . d 1011...100000... .......... U U U U U 4 4 2 2 2
574 eor 8 . . 1011...100...... A+-DXWL... U U U U U 8 8 4 4 4
575 eor 16 . d 1011...101000... .......... U U U U U 4 4 2 2 2
576 eor 16 . . 1011...101...... A+-DXWL... U U U U U 8 8 4 4 4
577 eor 32 . d 1011...110000... .......... U U U U U 8 6 2 2 2
578 eor 32 . . 1011...110...... A+-DXWL... U U U U U 12 12 4 4 4
579 eori 16 toc . 0000101000111100 .......... U U U U U 20 16 12 12 12
580 eori 16 tos . 0000101001111100 .......... S S S S S 20 16 12 12 12
581 eori 8 . d 0000101000000... .......... U U U U U 8 8 2 2 2
582 eori 8 . . 0000101000...... A+-DXWL... U U U U U 12 12 4 4 4
583 eori 16 . d 0000101001000... .......... U U U U U 8 8 2 2 2
584 eori 16 . . 0000101001...... A+-DXWL... U U U U U 12 12 4 4 4
585 eori 32 . d 0000101010000... .......... U U U U U 16 14 2 2 2
586 eori 32 . . 0000101010...... A+-DXWL... U U U U U 20 20 4 4 4
587 exg 32 dd . 1100...101000... .......... U U U U U 6 6 2 2 2
588 exg 32 aa . 1100...101001... .......... U U U U U 6 6 2 2 2
589 exg 32 da . 1100...110001... .......... U U U U U 6 6 2 2 2
590 ext 16 . . 0100100010000... .......... U U U U U 4 4 4 4 4
591 ext 32 . . 0100100011000... .......... U U U U U 4 4 4 4 4
592 extb 32 . . 0100100111000... .......... . . U U U . . 4 4 4
593 illegal 0 . . 0100101011111100 .......... U U U U U 4 4 4 4 4
594 jmp 32 . . 0100111011...... A..DXWLdx. U U U U U 4 4 0 0 0
595 jsr 32 . . 0100111010...... A..DXWLdx. U U U U U 12 12 0 0 0
596 lea 32 . . 0100...111...... A..DXWLdx. U U U U U 0 0 2 2 2
597 link 16 . a7 0100111001010111 .......... U U U U U 16 16 5 5 5
598 link 16 . . 0100111001010... .......... U U U U U 16 16 5 5 5
599 link 32 . a7 0100100000001111 .......... . . U U U . . 6 6 6
600 link 32 . . 0100100000001... .......... . . U U U . . 6 6 6
601 lsr 8 s . 1110...000001... .......... U U U U U 6 6 4 4 4
602 lsr 16 s . 1110...001001... .......... U U U U U 6 6 4 4 4
603 lsr 32 s . 1110...010001... .......... U U U U U 8 8 4 4 4
604 lsr 8 r . 1110...000101... .......... U U U U U 6 6 6 6 6
605 lsr 16 r . 1110...001101... .......... U U U U U 6 6 6 6 6
606 lsr 32 r . 1110...010101... .......... U U U U U 8 8 6 6 6
607 lsr 16 . . 1110001011...... A+-DXWL... U U U U U 8 8 5 5 5
608 lsl 8 s . 1110...100001... .......... U U U U U 6 6 4 4 4
609 lsl 16 s . 1110...101001... .......... U U U U U 6 6 4 4 4
610 lsl 32 s . 1110...110001... .......... U U U U U 8 8 4 4 4
611 lsl 8 r . 1110...100101... .......... U U U U U 6 6 6 6 6
612 lsl 16 r . 1110...101101... .......... U U U U U 6 6 6 6 6
613 lsl 32 r . 1110...110101... .......... U U U U U 8 8 6 6 6
614 lsl 16 . . 1110001111...... A+-DXWL... U U U U U 8 8 5 5 5
615 move 8 d d 0001...000000... .......... U U U U U 4 4 2 2 2
616 move 8 d . 0001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
617 move 8 ai d 0001...010000... .......... U U U U U 8 8 4 4 4
618 move 8 ai . 0001...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
619 move 8 pi d 0001...011000... .......... U U U U U 8 8 4 4 4
620 move 8 pi . 0001...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
621 move 8 pi7 d 0001111011000... .......... U U U U U 8 8 4 4 4
622 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U 8 8 4 4 4
623 move 8 pd d 0001...100000... .......... U U U U U 8 8 5 5 5
624 move 8 pd . 0001...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
625 move 8 pd7 d 0001111100000... .......... U U U U U 8 8 5 5 5
626 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U 8 8 5 5 5
627 move 8 di d 0001...101000... .......... U U U U U 12 12 5 5 5
628 move 8 di . 0001...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
629 move 8 ix d 0001...110000... .......... U U U U U 14 14 7 7 7
630 move 8 ix . 0001...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
631 move 8 aw d 0001000111000... .......... U U U U U 12 12 4 4 4
632 move 8 aw . 0001000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
633 move 8 al d 0001001111000... .......... U U U U U 16 16 6 6 6
634 move 8 al . 0001001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
635 move 16 d d 0011...000000... .......... U U U U U 4 4 2 2 2
636 move 16 d a 0011...000001... .......... U U U U U 4 4 2 2 2
637 move 16 d . 0011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
638 move 16 ai d 0011...010000... .......... U U U U U 8 8 4 4 4
639 move 16 ai a 0011...010001... .......... U U U U U 8 8 4 4 4
640 move 16 ai . 0011...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
641 move 16 pi d 0011...011000... .......... U U U U U 8 8 4 4 4
642 move 16 pi a 0011...011001... .......... U U U U U 8 8 4 4 4
643 move 16 pi . 0011...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
644 move 16 pd d 0011...100000... .......... U U U U U 8 8 5 5 5
645 move 16 pd a 0011...100001... .......... U U U U U 8 8 5 5 5
646 move 16 pd . 0011...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
647 move 16 di d 0011...101000... .......... U U U U U 12 12 5 5 5
648 move 16 di a 0011...101001... .......... U U U U U 12 12 5 5 5
649 move 16 di . 0011...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
650 move 16 ix d 0011...110000... .......... U U U U U 14 14 7 7 7
651 move 16 ix a 0011...110001... .......... U U U U U 14 14 7 7 7
652 move 16 ix . 0011...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
653 move 16 aw d 0011000111000... .......... U U U U U 12 12 4 4 4
654 move 16 aw a 0011000111001... .......... U U U U U 12 12 4 4 4
655 move 16 aw . 0011000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
656 move 16 al d 0011001111000... .......... U U U U U 16 16 6 6 6
657 move 16 al a 0011001111001... .......... U U U U U 16 16 6 6 6
658 move 16 al . 0011001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
659 move 32 d d 0010...000000... .......... U U U U U 4 4 2 2 2
660 move 32 d a 0010...000001... .......... U U U U U 4 4 2 2 2
661 move 32 d . 0010...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
662 move 32 ai d 0010...010000... .......... U U U U U 12 12 4 4 4
663 move 32 ai a 0010...010001... .......... U U U U U 12 12 4 4 4
664 move 32 ai . 0010...010...... A+-DXWLdxI U U U U U 12 12 4 4 4
665 move 32 pi d 0010...011000... .......... U U U U U 12 12 4 4 4
666 move 32 pi a 0010...011001... .......... U U U U U 12 12 4 4 4
667 move 32 pi . 0010...011...... A+-DXWLdxI U U U U U 12 12 4 4 4
668 move 32 pd d 0010...100000... .......... U U U U U 12 14 5 5 5
669 move 32 pd a 0010...100001... .......... U U U U U 12 14 5 5 5
670 move 32 pd . 0010...100...... A+-DXWLdxI U U U U U 12 14 5 5 5
671 move 32 di d 0010...101000... .......... U U U U U 16 16 5 5 5
672 move 32 di a 0010...101001... .......... U U U U U 16 16 5 5 5
673 move 32 di . 0010...101...... A+-DXWLdxI U U U U U 16 16 5 5 5
674 move 32 ix d 0010...110000... .......... U U U U U 18 18 7 7 7
675 move 32 ix a 0010...110001... .......... U U U U U 18 18 7 7 7
676 move 32 ix . 0010...110...... A+-DXWLdxI U U U U U 18 18 7 7 7
677 move 32 aw d 0010000111000... .......... U U U U U 16 16 4 4 4
678 move 32 aw a 0010000111001... .......... U U U U U 16 16 4 4 4
679 move 32 aw . 0010000111...... A+-DXWLdxI U U U U U 16 16 4 4 4
680 move 32 al d 0010001111000... .......... U U U U U 20 20 6 6 6
681 move 32 al a 0010001111001... .......... U U U U U 20 20 6 6 6
682 move 32 al . 0010001111...... A+-DXWLdxI U U U U U 20 20 6 6 6
683 movea 16 . d 0011...001000... .......... U U U U U 4 4 2 2 2
684 movea 16 . a 0011...001001... .......... U U U U U 4 4 2 2 2
685 movea 16 . . 0011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
686 movea 32 . d 0010...001000... .......... U U U U U 4 4 2 2 2
687 movea 32 . a 0010...001001... .......... U U U U U 4 4 2 2 2
688 movea 32 . . 0010...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
689 move 16 frc d 0100001011000... .......... . U U U U . 4 4 4 4
690 move 16 frc . 0100001011...... A+-DXWL... . U U U U . 8 4 4 4
691 move 16 toc d 0100010011000... .......... U U U U U 12 12 4 4 4
692 move 16 toc . 0100010011...... A+-DXWLdxI U U U U U 12 12 4 4 4
693 move 16 frs d 0100000011000... .......... U S S S S 6 4 8 8 8 U only for 000
694 move 16 frs . 0100000011...... A+-DXWL... U S S S S 8 8 8 8 8 U only for 000
695 move 16 tos d 0100011011000... .......... S S S S S 12 12 8 8 8
696 move 16 tos . 0100011011...... A+-DXWLdxI S S S S S 12 12 8 8 8
697 move 32 fru . 0100111001101... .......... S S S S S 4 6 2 2 2
698 move 32 tou . 0100111001100... .......... S S S S S 4 6 2 2 2
699 movec 32 cr . 0100111001111010 .......... . S S S S . 12 6 6 6
700 movec 32 rc . 0100111001111011 .......... . S S S S . 10 12 12 12
701 movem 16 re pd 0100100010100... .......... U U U U U 8 8 4 4 4
702 movem 16 re . 0100100010...... A..DXWL... U U U U U 8 8 4 4 4
703 movem 32 re pd 0100100011100... .......... U U U U U 8 8 4 4 4
704 movem 32 re . 0100100011...... A..DXWL... U U U U U 8 8 4 4 4
705 movem 16 er pi 0100110010011... .......... U U U U U 12 12 8 8 8
706 movem 16 er pcdi 0100110010111010 .......... U U U U U 16 16 9 9 9
707 movem 16 er pcix 0100110010111011 .......... U U U U U 18 18 11 11 11
708 movem 16 er . 0100110010...... A..DXWL... U U U U U 12 12 8 8 8
709 movem 32 er pi 0100110011011... .......... U U U U U 12 12 8 8 8
710 movem 32 er pcdi 0100110011111010 .......... U U U U U 16 16 9 9 9
711 movem 32 er pcix 0100110011111011 .......... U U U U U 18 18 11 11 11
712 movem 32 er . 0100110011...... A..DXWL... U U U U U 12 12 8 8 8
713 movep 16 er . 0000...100001... .......... U U U U U 16 16 12 12 12
714 movep 32 er . 0000...101001... .......... U U U U U 24 24 18 18 18
715 movep 16 re . 0000...110001... .......... U U U U U 16 16 11 11 11
716 movep 32 re . 0000...111001... .......... U U U U U 24 24 17 17 17
717 moveq 32 . . 0111...0........ .......... U U U U U 4 4 2 2 2
718 moves 8 . . 0000111000...... A+-DXWL... . S S S S . 14 5 5 5
719 moves 16 . . 0000111001...... A+-DXWL... . S S S S . 14 5 5 5
720 moves 32 . . 0000111010...... A+-DXWL... . S S S S . 16 5 5 5
721 move16 32 . . 1111011000100... .......... . . . . U . . . . 4 TODO: correct timing
722 muls 16 . d 1100...111000... .......... U U U U U 54 32 27 27 27
723 muls 16 . . 1100...111...... A+-DXWLdxI U U U U U 54 32 27 27 27
724 mulu 16 . d 1100...011000... .......... U U U U U 54 30 27 27 27
725 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U 54 30 27 27 27
726 mull 32 . d 0100110000000... .......... . . U U U . . 43 43 43
727 mull 32 . . 0100110000...... A+-DXWLdxI . . U U U . . 43 43 43
728 nbcd 8 . d 0100100000000... .......... U U U U U 6 6 6 6 6
729 nbcd 8 . . 0100100000...... A+-DXWL... U U U U U 8 8 6 6 6
730 neg 8 . d 0100010000000... .......... U U U U U 4 4 2 2 2
731 neg 8 . . 0100010000...... A+-DXWL... U U U U U 8 8 4 4 4
732 neg 16 . d 0100010001000... .......... U U U U U 4 4 2 2 2
733 neg 16 . . 0100010001...... A+-DXWL... U U U U U 8 8 4 4 4
734 neg 32 . d 0100010010000... .......... U U U U U 6 6 2 2 2
735 neg 32 . . 0100010010...... A+-DXWL... U U U U U 12 12 4 4 4
736 negx 8 . d 0100000000000... .......... U U U U U 4 4 2 2 2
737 negx 8 . . 0100000000...... A+-DXWL... U U U U U 8 8 4 4 4
738 negx 16 . d 0100000001000... .......... U U U U U 4 4 2 2 2
739 negx 16 . . 0100000001...... A+-DXWL... U U U U U 8 8 4 4 4
740 negx 32 . d 0100000010000... .......... U U U U U 6 6 2 2 2
741 negx 32 . . 0100000010...... A+-DXWL... U U U U U 12 12 4 4 4
742 nop 0 . . 0100111001110001 .......... U U U U U 4 4 2 2 2
743 not 8 . d 0100011000000... .......... U U U U U 4 4 2 2 2
744 not 8 . . 0100011000...... A+-DXWL... U U U U U 8 8 4 4 4
745 not 16 . d 0100011001000... .......... U U U U U 4 4 2 2 2
746 not 16 . . 0100011001...... A+-DXWL... U U U U U 8 8 4 4 4
747 not 32 . d 0100011010000... .......... U U U U U 6 6 2 2 2
748 not 32 . . 0100011010...... A+-DXWL... U U U U U 12 12 4 4 4
749 or 8 er d 1000...000000... .......... U U U U U 4 4 2 2 2
750 or 8 er . 1000...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
751 or 16 er d 1000...001000... .......... U U U U U 4 4 2 2 2
752 or 16 er . 1000...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
753 or 32 er d 1000...010000... .......... U U U U U 6 6 2 2 2
754 or 32 er . 1000...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
755 or 8 re . 1000...100...... A+-DXWL... U U U U U 8 8 4 4 4
756 or 16 re . 1000...101...... A+-DXWL... U U U U U 8 8 4 4 4
757 or 32 re . 1000...110...... A+-DXWL... U U U U U 12 12 4 4 4
758 ori 16 toc . 0000000000111100 .......... U U U U U 20 16 12 12 12
759 ori 16 tos . 0000000001111100 .......... S S S S S 20 16 12 12 12
760 ori 8 . d 0000000000000... .......... U U U U U 8 8 2 2 2
761 ori 8 . . 0000000000...... A+-DXWL... U U U U U 12 12 4 4 4
762 ori 16 . d 0000000001000... .......... U U U U U 8 8 2 2 2
763 ori 16 . . 0000000001...... A+-DXWL... U U U U U 12 12 4 4 4
764 ori 32 . d 0000000010000... .......... U U U U U 16 14 2 2 2
765 ori 32 . . 0000000010...... A+-DXWL... U U U U U 20 20 4 4 4
766 pack 16 rr . 1000...101000... .......... . . U U U . . 6 6 6
767 pack 16 mm ax7 1000111101001... .......... . . U U U . . 13 13 13
768 pack 16 mm ay7 1000...101001111 .......... . . U U U . . 13 13 13
769 pack 16 mm axy7 1000111101001111 .......... . . U U U . . 13 13 13
770 pack 16 mm . 1000...101001... .......... . . U U U . . 13 13 13
771 pea 32 . . 0100100001...... A..DXWLdx. U U U U U 6 6 5 5 5
772 pflush 32 . . 1111010100011000 .......... . . . . S . . . . 4 TODO: correct timing
773 pmmu 32 . . 1111000......... .......... . . S S S . . 8 8 8
774 reset 0 . . 0100111001110000 .......... S S S S S 0 0 0 0 0
775 ror 8 s . 1110...000011... .......... U U U U U 6 6 8 8 8
776 ror 16 s . 1110...001011... .......... U U U U U 6 6 8 8 8
777 ror 32 s . 1110...010011... .......... U U U U U 8 8 8 8 8
778 ror 8 r . 1110...000111... .......... U U U U U 6 6 8 8 8
779 ror 16 r . 1110...001111... .......... U U U U U 6 6 8 8 8
780 ror 32 r . 1110...010111... .......... U U U U U 8 8 8 8 8
781 ror 16 . . 1110011011...... A+-DXWL... U U U U U 8 8 7 7 7
782 rol 8 s . 1110...100011... .......... U U U U U 6 6 8 8 8
783 rol 16 s . 1110...101011... .......... U U U U U 6 6 8 8 8
784 rol 32 s . 1110...110011... .......... U U U U U 8 8 8 8 8
785 rol 8 r . 1110...100111... .......... U U U U U 6 6 8 8 8
786 rol 16 r . 1110...101111... .......... U U U U U 6 6 8 8 8
787 rol 32 r . 1110...110111... .......... U U U U U 8 8 8 8 8
788 rol 16 . . 1110011111...... A+-DXWL... U U U U U 8 8 7 7 7
789 roxr 8 s . 1110...000010... .......... U U U U U 6 6 12 12 12
790 roxr 16 s . 1110...001010... .......... U U U U U 6 6 12 12 12
791 roxr 32 s . 1110...010010... .......... U U U U U 8 8 12 12 12
792 roxr 8 r . 1110...000110... .......... U U U U U 6 6 12 12 12
793 roxr 16 r . 1110...001110... .......... U U U U U 6 6 12 12 12
794 roxr 32 r . 1110...010110... .......... U U U U U 8 8 12 12 12
795 roxr 16 . . 1110010011...... A+-DXWL... U U U U U 8 8 5 5 5
796 roxl 8 s . 1110...100010... .......... U U U U U 6 6 12 12 12
797 roxl 16 s . 1110...101010... .......... U U U U U 6 6 12 12 12
798 roxl 32 s . 1110...110010... .......... U U U U U 8 8 12 12 12
799 roxl 8 r . 1110...100110... .......... U U U U U 6 6 12 12 12
800 roxl 16 r . 1110...101110... .......... U U U U U 6 6 12 12 12
801 roxl 32 r . 1110...110110... .......... U U U U U 8 8 12 12 12
802 roxl 16 . . 1110010111...... A+-DXWL... U U U U U 8 8 5 5 5
803 rtd 32 . . 0100111001110100 .......... . U U U U . 16 10 10 10
804 rte 32 . . 0100111001110011 .......... S S S S S 20 24 20 20 20 bus fault not emulated
805 rtm 32 . . 000001101100.... .......... . . U U U . . 19 19 19 not properly emulated
806 rtr 32 . . 0100111001110111 .......... U U U U U 20 20 14 14 14
807 rts 32 . . 0100111001110101 .......... U U U U U 16 16 10 10 10
808 sbcd 8 rr . 1000...100000... .......... U U U U U 6 6 4 4 4
809 sbcd 8 mm ax7 1000111100001... .......... U U U U U 18 18 16 16 16
810 sbcd 8 mm ay7 1000...100001111 .......... U U U U U 18 18 16 16 16
811 sbcd 8 mm axy7 1000111100001111 .......... U U U U U 18 18 16 16 16
812 sbcd 8 mm . 1000...100001... .......... U U U U U 18 18 16 16 16
813 st 8 . d 0101000011000... .......... U U U U U 6 4 4 4 4
814 st 8 . . 0101000011...... A+-DXWL... U U U U U 8 8 6 6 6
815 sf 8 . d 0101000111000... .......... U U U U U 4 4 4 4 4
816 sf 8 . . 0101000111...... A+-DXWL... U U U U U 8 8 6 6 6
817 scc 8 . d 0101....11000... .......... U U U U U 4 4 4 4 4
818 scc 8 . . 0101....11...... A+-DXWL... U U U U U 8 8 6 6 6
819 stop 0 . . 0100111001110010 .......... S S S S S 4 4 8 8 8
820 sub 8 er d 1001...000000... .......... U U U U U 4 4 2 2 2
821 sub 8 er . 1001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
822 sub 16 er d 1001...001000... .......... U U U U U 4 4 2 2 2
823 sub 16 er a 1001...001001... .......... U U U U U 4 4 2 2 2
824 sub 16 er . 1001...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
825 sub 32 er d 1001...010000... .......... U U U U U 6 6 2 2 2
826 sub 32 er a 1001...010001... .......... U U U U U 6 6 2 2 2
827 sub 32 er . 1001...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
828 sub 8 re . 1001...100...... A+-DXWL... U U U U U 8 8 4 4 4
829 sub 16 re . 1001...101...... A+-DXWL... U U U U U 8 8 4 4 4
830 sub 32 re . 1001...110...... A+-DXWL... U U U U U 12 12 4 4 4
831 suba 16 . d 1001...011000... .......... U U U U U 8 8 2 2 2
832 suba 16 . a 1001...011001... .......... U U U U U 8 8 2 2 2
833 suba 16 . . 1001...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
834 suba 32 . d 1001...111000... .......... U U U U U 6 6 2 2 2
835 suba 32 . a 1001...111001... .......... U U U U U 6 6 2 2 2
836 suba 32 . . 1001...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
837 subi 8 . d 0000010000000... .......... U U U U U 8 8 2 2 2
838 subi 8 . . 0000010000...... A+-DXWL... U U U U U 12 12 4 4 4
839 subi 16 . d 0000010001000... .......... U U U U U 8 8 2 2 2
840 subi 16 . . 0000010001...... A+-DXWL... U U U U U 12 12 4 4 4
841 subi 32 . d 0000010010000... .......... U U U U U 16 14 2 2 2
842 subi 32 . . 0000010010...... A+-DXWL... U U U U U 20 20 4 4 4
843 subq 8 . d 0101...100000... .......... U U U U U 4 4 2 2 2
844 subq 8 . . 0101...100...... A+-DXWL... U U U U U 8 8 4 4 4
845 subq 16 . d 0101...101000... .......... U U U U U 4 4 2 2 2
846 subq 16 . a 0101...101001... .......... U U U U U 8 4 2 2 2
847 subq 16 . . 0101...101...... A+-DXWL... U U U U U 8 8 4 4 4
848 subq 32 . d 0101...110000... .......... U U U U U 8 8 2 2 2
849 subq 32 . a 0101...110001... .......... U U U U U 8 8 2 2 2
850 subq 32 . . 0101...110...... A+-DXWL... U U U U U 12 12 4 4 4
851 subx 8 rr . 1001...100000... .......... U U U U U 4 4 2 2 2
852 subx 16 rr . 1001...101000... .......... U U U U U 4 4 2 2 2
853 subx 32 rr . 1001...110000... .......... U U U U U 8 6 2 2 2
854 subx 8 mm ax7 1001111100001... .......... U U U U U 18 18 12 12 12
855 subx 8 mm ay7 1001...100001111 .......... U U U U U 18 18 12 12 12
856 subx 8 mm axy7 1001111100001111 .......... U U U U U 18 18 12 12 12
857 subx 8 mm . 1001...100001... .......... U U U U U 18 18 12 12 12
858 subx 16 mm . 1001...101001... .......... U U U U U 18 18 12 12 12
859 subx 32 mm . 1001...110001... .......... U U U U U 30 30 12 12 12
860 swap 32 . . 0100100001000... .......... U U U U U 4 4 4 4 4
861 tas 8 . d 0100101011000... .......... U U U U U 4 4 4 4 4
862 tas 8 . . 0100101011...... A+-DXWL... U U U U U 14 14 12 12 12
863 trap 0 . . 010011100100.... .......... U U U U U 4 4 4 4 4
864 trapt 0 . . 0101000011111100 .......... . . U U U . . 4 4 4
865 trapt 16 . . 0101000011111010 .......... . . U U U . . 6 6 6
866 trapt 32 . . 0101000011111011 .......... . . U U U . . 8 8 8
867 trapf 0 . . 0101000111111100 .......... . . U U U . . 4 4 4
868 trapf 16 . . 0101000111111010 .......... . . U U U . . 6 6 6
869 trapf 32 . . 0101000111111011 .......... . . U U U . . 8 8 8
870 trapcc 0 . . 0101....11111100 .......... . . U U U . . 4 4 4
871 trapcc 16 . . 0101....11111010 .......... . . U U U . . 6 6 6
872 trapcc 32 . . 0101....11111011 .......... . . U U U . . 8 8 8
873 trapv 0 . . 0100111001110110 .......... U U U U U 4 4 4 4 4
874 tst 8 . d 0100101000000... .......... U U U U U 4 4 2 2 2
875 tst 8 . . 0100101000...... A+-DXWL... U U U U U 4 4 2 2 2
876 tst 8 . pcdi 0100101000111010 .......... . . U U U . . 7 7 7
877 tst 8 . pcix 0100101000111011 .......... . . U U U . . 9 9 9
878 tst 8 . i 0100101000111100 .......... . . U U U . . 6 6 6
879 tst 16 . d 0100101001000... .......... U U U U U 4 4 2 2 2
880 tst 16 . a 0100101001001... .......... . . U U U . . 2 2 2
881 tst 16 . . 0100101001...... A+-DXWL... U U U U U 4 4 2 2 2
882 tst 16 . pcdi 0100101001111010 .......... . . U U U . . 7 7 7
883 tst 16 . pcix 0100101001111011 .......... . . U U U . . 9 9 9
884 tst 16 . i 0100101001111100 .......... . . U U U . . 6 6 6
885 tst 32 . d 0100101010000... .......... U U U U U 4 4 2 2 2
886 tst 32 . a 0100101010001... .......... . . U U U . . 2 2 2
887 tst 32 . . 0100101010...... A+-DXWL... U U U U U 4 4 2 2 2
888 tst 32 . pcdi 0100101010111010 .......... . . U U U . . 7 7 7
889 tst 32 . pcix 0100101010111011 .......... . . U U U . . 9 9 9
890 tst 32 . i 0100101010111100 .......... . . U U U . . 6 6 6
891 unlk 32 . a7 0100111001011111 .......... U U U U U 12 12 6 6 6
892 unlk 32 . . 0100111001011... .......... U U U U U 12 12 6 6 6
893 unpk 16 rr . 1000...110000... .......... . . U U U . . 8 8 8
894 unpk 16 mm ax7 1000111110001... .......... . . U U U . . 13 13 13
895 unpk 16 mm ay7 1000...110001111 .......... . . U U U . . 13 13 13
896 unpk 16 mm axy7 1000111110001111 .......... . . U U U . . 13 13 13
897 unpk 16 mm . 1000...110001... .......... . . U U U . . 13 13 13
901 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
902 M68KMAKE_OPCODE_HANDLER_BODY
904 M68KMAKE_OP(1010, 0, ., .)
906 m68ki_exception_1010();
910 M68KMAKE_OP(1111, 0, ., .)
912 m68ki_exception_1111();
916 M68KMAKE_OP(040fpu0, 32, ., .)
918 if(CPU_TYPE_IS_030_PLUS(CPU_TYPE))
923 m68ki_exception_1111();
927 M68KMAKE_OP(040fpu1, 32, ., .)
929 if(CPU_TYPE_IS_030_PLUS(CPU_TYPE))
934 m68ki_exception_1111();
939 M68KMAKE_OP(abcd, 8, rr, .)
944 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
946 FLAG_V = ~res; /* Undefined V behavior */
950 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
951 FLAG_X = FLAG_C = (res > 0x99) << 8;
955 FLAG_V &= res; /* Undefined V behavior part II */
956 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
958 res = MASK_OUT_ABOVE_8(res);
961 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
965 M68KMAKE_OP(abcd, 8, mm, ax7)
967 uint src = OPER_AY_PD_8();
968 uint ea = EA_A7_PD_8();
969 uint dst = m68ki_read_8(ea);
970 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
972 FLAG_V = ~res; /* Undefined V behavior */
976 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
977 FLAG_X = FLAG_C = (res > 0x99) << 8;
981 FLAG_V &= res; /* Undefined V behavior part II */
982 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
984 res = MASK_OUT_ABOVE_8(res);
987 m68ki_write_8(ea, res);
991 M68KMAKE_OP(abcd, 8, mm, ay7)
993 uint src = OPER_A7_PD_8();
994 uint ea = EA_AX_PD_8();
995 uint dst = m68ki_read_8(ea);
996 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
998 FLAG_V = ~res; /* Undefined V behavior */
1002 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1003 FLAG_X = FLAG_C = (res > 0x99) << 8;
1007 FLAG_V &= res; /* Undefined V behavior part II */
1008 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1010 res = MASK_OUT_ABOVE_8(res);
1013 m68ki_write_8(ea, res);
1017 M68KMAKE_OP(abcd, 8, mm, axy7)
1019 uint src = OPER_A7_PD_8();
1020 uint ea = EA_A7_PD_8();
1021 uint dst = m68ki_read_8(ea);
1022 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1024 FLAG_V = ~res; /* Undefined V behavior */
1028 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1029 FLAG_X = FLAG_C = (res > 0x99) << 8;
1033 FLAG_V &= res; /* Undefined V behavior part II */
1034 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1036 res = MASK_OUT_ABOVE_8(res);
1039 m68ki_write_8(ea, res);
1043 M68KMAKE_OP(abcd, 8, mm, .)
1045 uint src = OPER_AY_PD_8();
1046 uint ea = EA_AX_PD_8();
1047 uint dst = m68ki_read_8(ea);
1048 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1050 FLAG_V = ~res; /* Undefined V behavior */
1054 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1055 FLAG_X = FLAG_C = (res > 0x99) << 8;
1059 FLAG_V &= res; /* Undefined V behavior part II */
1060 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1062 res = MASK_OUT_ABOVE_8(res);
1065 m68ki_write_8(ea, res);
1069 M68KMAKE_OP(add, 8, er, d)
1072 uint src = MASK_OUT_ABOVE_8(DY);
1073 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1074 uint res = src + dst;
1076 FLAG_N = NFLAG_8(res);
1077 FLAG_V = VFLAG_ADD_8(src, dst, res);
1078 FLAG_X = FLAG_C = CFLAG_8(res);
1079 FLAG_Z = MASK_OUT_ABOVE_8(res);
1081 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1085 M68KMAKE_OP(add, 8, er, .)
1088 uint src = M68KMAKE_GET_OPER_AY_8;
1089 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1090 uint res = src + dst;
1092 FLAG_N = NFLAG_8(res);
1093 FLAG_V = VFLAG_ADD_8(src, dst, res);
1094 FLAG_X = FLAG_C = CFLAG_8(res);
1095 FLAG_Z = MASK_OUT_ABOVE_8(res);
1097 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1101 M68KMAKE_OP(add, 16, er, d)
1104 uint src = MASK_OUT_ABOVE_16(DY);
1105 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1106 uint res = src + dst;
1108 FLAG_N = NFLAG_16(res);
1109 FLAG_V = VFLAG_ADD_16(src, dst, res);
1110 FLAG_X = FLAG_C = CFLAG_16(res);
1111 FLAG_Z = MASK_OUT_ABOVE_16(res);
1113 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1117 M68KMAKE_OP(add, 16, er, a)
1120 uint src = MASK_OUT_ABOVE_16(AY);
1121 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1122 uint res = src + dst;
1124 FLAG_N = NFLAG_16(res);
1125 FLAG_V = VFLAG_ADD_16(src, dst, res);
1126 FLAG_X = FLAG_C = CFLAG_16(res);
1127 FLAG_Z = MASK_OUT_ABOVE_16(res);
1129 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1133 M68KMAKE_OP(add, 16, er, .)
1136 uint src = M68KMAKE_GET_OPER_AY_16;
1137 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1138 uint res = src + dst;
1140 FLAG_N = NFLAG_16(res);
1141 FLAG_V = VFLAG_ADD_16(src, dst, res);
1142 FLAG_X = FLAG_C = CFLAG_16(res);
1143 FLAG_Z = MASK_OUT_ABOVE_16(res);
1145 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1149 M68KMAKE_OP(add, 32, er, d)
1154 uint res = src + dst;
1156 FLAG_N = NFLAG_32(res);
1157 FLAG_V = VFLAG_ADD_32(src, dst, res);
1158 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1159 FLAG_Z = MASK_OUT_ABOVE_32(res);
1165 M68KMAKE_OP(add, 32, er, a)
1170 uint res = src + dst;
1172 FLAG_N = NFLAG_32(res);
1173 FLAG_V = VFLAG_ADD_32(src, dst, res);
1174 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1175 FLAG_Z = MASK_OUT_ABOVE_32(res);
1181 M68KMAKE_OP(add, 32, er, .)
1184 uint src = M68KMAKE_GET_OPER_AY_32;
1186 uint res = src + dst;
1188 FLAG_N = NFLAG_32(res);
1189 FLAG_V = VFLAG_ADD_32(src, dst, res);
1190 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1191 FLAG_Z = MASK_OUT_ABOVE_32(res);
1197 M68KMAKE_OP(add, 8, re, .)
1199 uint ea = M68KMAKE_GET_EA_AY_8;
1200 uint src = MASK_OUT_ABOVE_8(DX);
1201 uint dst = m68ki_read_8(ea);
1202 uint res = src + dst;
1204 FLAG_N = NFLAG_8(res);
1205 FLAG_V = VFLAG_ADD_8(src, dst, res);
1206 FLAG_X = FLAG_C = CFLAG_8(res);
1207 FLAG_Z = MASK_OUT_ABOVE_8(res);
1209 m68ki_write_8(ea, FLAG_Z);
1213 M68KMAKE_OP(add, 16, re, .)
1215 uint ea = M68KMAKE_GET_EA_AY_16;
1216 uint src = MASK_OUT_ABOVE_16(DX);
1217 uint dst = m68ki_read_16(ea);
1218 uint res = src + dst;
1220 FLAG_N = NFLAG_16(res);
1221 FLAG_V = VFLAG_ADD_16(src, dst, res);
1222 FLAG_X = FLAG_C = CFLAG_16(res);
1223 FLAG_Z = MASK_OUT_ABOVE_16(res);
1225 m68ki_write_16(ea, FLAG_Z);
1229 M68KMAKE_OP(add, 32, re, .)
1231 uint ea = M68KMAKE_GET_EA_AY_32;
1233 uint dst = m68ki_read_32(ea);
1234 uint res = src + dst;
1236 FLAG_N = NFLAG_32(res);
1237 FLAG_V = VFLAG_ADD_32(src, dst, res);
1238 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1239 FLAG_Z = MASK_OUT_ABOVE_32(res);
1241 m68ki_write_32(ea, FLAG_Z);
1245 M68KMAKE_OP(adda, 16, ., d)
1249 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
1253 M68KMAKE_OP(adda, 16, ., a)
1257 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
1261 M68KMAKE_OP(adda, 16, ., .)
1264 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
1266 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1270 M68KMAKE_OP(adda, 32, ., d)
1274 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
1278 M68KMAKE_OP(adda, 32, ., a)
1282 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
1286 M68KMAKE_OP(adda, 32, ., .)
1288 uint src = M68KMAKE_GET_OPER_AY_32;
1291 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1295 M68KMAKE_OP(addi, 8, ., d)
1298 uint src = OPER_I_8();
1299 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1300 uint res = src + dst;
1302 FLAG_N = NFLAG_8(res);
1303 FLAG_V = VFLAG_ADD_8(src, dst, res);
1304 FLAG_X = FLAG_C = CFLAG_8(res);
1305 FLAG_Z = MASK_OUT_ABOVE_8(res);
1307 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1311 M68KMAKE_OP(addi, 8, ., .)
1313 uint src = OPER_I_8();
1314 uint ea = M68KMAKE_GET_EA_AY_8;
1315 uint dst = m68ki_read_8(ea);
1316 uint res = src + dst;
1318 FLAG_N = NFLAG_8(res);
1319 FLAG_V = VFLAG_ADD_8(src, dst, res);
1320 FLAG_X = FLAG_C = CFLAG_8(res);
1321 FLAG_Z = MASK_OUT_ABOVE_8(res);
1323 m68ki_write_8(ea, FLAG_Z);
1327 M68KMAKE_OP(addi, 16, ., d)
1330 uint src = OPER_I_16();
1331 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1332 uint res = src + dst;
1334 FLAG_N = NFLAG_16(res);
1335 FLAG_V = VFLAG_ADD_16(src, dst, res);
1336 FLAG_X = FLAG_C = CFLAG_16(res);
1337 FLAG_Z = MASK_OUT_ABOVE_16(res);
1339 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1343 M68KMAKE_OP(addi, 16, ., .)
1345 uint src = OPER_I_16();
1346 uint ea = M68KMAKE_GET_EA_AY_16;
1347 uint dst = m68ki_read_16(ea);
1348 uint res = src + dst;
1350 FLAG_N = NFLAG_16(res);
1351 FLAG_V = VFLAG_ADD_16(src, dst, res);
1352 FLAG_X = FLAG_C = CFLAG_16(res);
1353 FLAG_Z = MASK_OUT_ABOVE_16(res);
1355 m68ki_write_16(ea, FLAG_Z);
1359 M68KMAKE_OP(addi, 32, ., d)
1362 uint src = OPER_I_32();
1364 uint res = src + dst;
1366 FLAG_N = NFLAG_32(res);
1367 FLAG_V = VFLAG_ADD_32(src, dst, res);
1368 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1369 FLAG_Z = MASK_OUT_ABOVE_32(res);
1375 M68KMAKE_OP(addi, 32, ., .)
1377 uint src = OPER_I_32();
1378 uint ea = M68KMAKE_GET_EA_AY_32;
1379 uint dst = m68ki_read_32(ea);
1380 uint res = src + dst;
1382 FLAG_N = NFLAG_32(res);
1383 FLAG_V = VFLAG_ADD_32(src, dst, res);
1384 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1385 FLAG_Z = MASK_OUT_ABOVE_32(res);
1387 m68ki_write_32(ea, FLAG_Z);
1391 M68KMAKE_OP(addq, 8, ., d)
1394 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1395 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1396 uint res = src + dst;
1398 FLAG_N = NFLAG_8(res);
1399 FLAG_V = VFLAG_ADD_8(src, dst, res);
1400 FLAG_X = FLAG_C = CFLAG_8(res);
1401 FLAG_Z = MASK_OUT_ABOVE_8(res);
1403 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1407 M68KMAKE_OP(addq, 8, ., .)
1409 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1410 uint ea = M68KMAKE_GET_EA_AY_8;
1411 uint dst = m68ki_read_8(ea);
1412 uint res = src + dst;
1414 FLAG_N = NFLAG_8(res);
1415 FLAG_V = VFLAG_ADD_8(src, dst, res);
1416 FLAG_X = FLAG_C = CFLAG_8(res);
1417 FLAG_Z = MASK_OUT_ABOVE_8(res);
1419 m68ki_write_8(ea, FLAG_Z);
1423 M68KMAKE_OP(addq, 16, ., d)
1426 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1427 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1428 uint res = src + dst;
1430 FLAG_N = NFLAG_16(res);
1431 FLAG_V = VFLAG_ADD_16(src, dst, res);
1432 FLAG_X = FLAG_C = CFLAG_16(res);
1433 FLAG_Z = MASK_OUT_ABOVE_16(res);
1435 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1439 M68KMAKE_OP(addq, 16, ., a)
1443 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1447 M68KMAKE_OP(addq, 16, ., .)
1449 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1450 uint ea = M68KMAKE_GET_EA_AY_16;
1451 uint dst = m68ki_read_16(ea);
1452 uint res = src + dst;
1454 FLAG_N = NFLAG_16(res);
1455 FLAG_V = VFLAG_ADD_16(src, dst, res);
1456 FLAG_X = FLAG_C = CFLAG_16(res);
1457 FLAG_Z = MASK_OUT_ABOVE_16(res);
1459 m68ki_write_16(ea, FLAG_Z);
1463 M68KMAKE_OP(addq, 32, ., d)
1466 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1468 uint res = src + dst;
1470 FLAG_N = NFLAG_32(res);
1471 FLAG_V = VFLAG_ADD_32(src, dst, res);
1472 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1473 FLAG_Z = MASK_OUT_ABOVE_32(res);
1479 M68KMAKE_OP(addq, 32, ., a)
1483 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1487 M68KMAKE_OP(addq, 32, ., .)
1489 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1490 uint ea = M68KMAKE_GET_EA_AY_32;
1491 uint dst = m68ki_read_32(ea);
1492 uint res = src + dst;
1495 FLAG_N = NFLAG_32(res);
1496 FLAG_V = VFLAG_ADD_32(src, dst, res);
1497 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1498 FLAG_Z = MASK_OUT_ABOVE_32(res);
1500 m68ki_write_32(ea, FLAG_Z);
1504 M68KMAKE_OP(addx, 8, rr, .)
1507 uint src = MASK_OUT_ABOVE_8(DY);
1508 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1509 uint res = src + dst + XFLAG_AS_1();
1511 FLAG_N = NFLAG_8(res);
1512 FLAG_V = VFLAG_ADD_8(src, dst, res);
1513 FLAG_X = FLAG_C = CFLAG_8(res);
1515 res = MASK_OUT_ABOVE_8(res);
1518 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1522 M68KMAKE_OP(addx, 16, rr, .)
1525 uint src = MASK_OUT_ABOVE_16(DY);
1526 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1527 uint res = src + dst + XFLAG_AS_1();
1529 FLAG_N = NFLAG_16(res);
1530 FLAG_V = VFLAG_ADD_16(src, dst, res);
1531 FLAG_X = FLAG_C = CFLAG_16(res);
1533 res = MASK_OUT_ABOVE_16(res);
1536 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1540 M68KMAKE_OP(addx, 32, rr, .)
1545 uint res = src + dst + XFLAG_AS_1();
1547 FLAG_N = NFLAG_32(res);
1548 FLAG_V = VFLAG_ADD_32(src, dst, res);
1549 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1551 res = MASK_OUT_ABOVE_32(res);
1558 M68KMAKE_OP(addx, 8, mm, ax7)
1560 uint src = OPER_AY_PD_8();
1561 uint ea = EA_A7_PD_8();
1562 uint dst = m68ki_read_8(ea);
1563 uint res = src + dst + XFLAG_AS_1();
1565 FLAG_N = NFLAG_8(res);
1566 FLAG_V = VFLAG_ADD_8(src, dst, res);
1567 FLAG_X = FLAG_C = CFLAG_8(res);
1569 res = MASK_OUT_ABOVE_8(res);
1572 m68ki_write_8(ea, res);
1576 M68KMAKE_OP(addx, 8, mm, ay7)
1578 uint src = OPER_A7_PD_8();
1579 uint ea = EA_AX_PD_8();
1580 uint dst = m68ki_read_8(ea);
1581 uint res = src + dst + XFLAG_AS_1();
1583 FLAG_N = NFLAG_8(res);
1584 FLAG_V = VFLAG_ADD_8(src, dst, res);
1585 FLAG_X = FLAG_C = CFLAG_8(res);
1587 res = MASK_OUT_ABOVE_8(res);
1590 m68ki_write_8(ea, res);
1594 M68KMAKE_OP(addx, 8, mm, axy7)
1596 uint src = OPER_A7_PD_8();
1597 uint ea = EA_A7_PD_8();
1598 uint dst = m68ki_read_8(ea);
1599 uint res = src + dst + XFLAG_AS_1();
1601 FLAG_N = NFLAG_8(res);
1602 FLAG_V = VFLAG_ADD_8(src, dst, res);
1603 FLAG_X = FLAG_C = CFLAG_8(res);
1605 res = MASK_OUT_ABOVE_8(res);
1608 m68ki_write_8(ea, res);
1612 M68KMAKE_OP(addx, 8, mm, .)
1614 uint src = OPER_AY_PD_8();
1615 uint ea = EA_AX_PD_8();
1616 uint dst = m68ki_read_8(ea);
1617 uint res = src + dst + XFLAG_AS_1();
1619 FLAG_N = NFLAG_8(res);
1620 FLAG_V = VFLAG_ADD_8(src, dst, res);
1621 FLAG_X = FLAG_C = CFLAG_8(res);
1623 res = MASK_OUT_ABOVE_8(res);
1626 m68ki_write_8(ea, res);
1630 M68KMAKE_OP(addx, 16, mm, .)
1632 uint src = OPER_AY_PD_16();
1633 uint ea = EA_AX_PD_16();
1634 uint dst = m68ki_read_16(ea);
1635 uint res = src + dst + XFLAG_AS_1();
1637 FLAG_N = NFLAG_16(res);
1638 FLAG_V = VFLAG_ADD_16(src, dst, res);
1639 FLAG_X = FLAG_C = CFLAG_16(res);
1641 res = MASK_OUT_ABOVE_16(res);
1644 m68ki_write_16(ea, res);
1648 M68KMAKE_OP(addx, 32, mm, .)
1650 uint src = OPER_AY_PD_32();
1651 uint ea = EA_AX_PD_32();
1652 uint dst = m68ki_read_32(ea);
1653 uint res = src + dst + XFLAG_AS_1();
1655 FLAG_N = NFLAG_32(res);
1656 FLAG_V = VFLAG_ADD_32(src, dst, res);
1657 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1659 res = MASK_OUT_ABOVE_32(res);
1662 m68ki_write_32(ea, res);
1666 M68KMAKE_OP(and, 8, er, d)
1668 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
1670 FLAG_N = NFLAG_8(FLAG_Z);
1671 FLAG_C = CFLAG_CLEAR;
1672 FLAG_V = VFLAG_CLEAR;
1676 M68KMAKE_OP(and, 8, er, .)
1678 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
1680 FLAG_N = NFLAG_8(FLAG_Z);
1681 FLAG_C = CFLAG_CLEAR;
1682 FLAG_V = VFLAG_CLEAR;
1686 M68KMAKE_OP(and, 16, er, d)
1688 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
1690 FLAG_N = NFLAG_16(FLAG_Z);
1691 FLAG_C = CFLAG_CLEAR;
1692 FLAG_V = VFLAG_CLEAR;
1696 M68KMAKE_OP(and, 16, er, .)
1698 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
1700 FLAG_N = NFLAG_16(FLAG_Z);
1701 FLAG_C = CFLAG_CLEAR;
1702 FLAG_V = VFLAG_CLEAR;
1706 M68KMAKE_OP(and, 32, er, d)
1710 FLAG_N = NFLAG_32(FLAG_Z);
1711 FLAG_C = CFLAG_CLEAR;
1712 FLAG_V = VFLAG_CLEAR;
1716 M68KMAKE_OP(and, 32, er, .)
1718 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
1720 FLAG_N = NFLAG_32(FLAG_Z);
1721 FLAG_C = CFLAG_CLEAR;
1722 FLAG_V = VFLAG_CLEAR;
1726 M68KMAKE_OP(and, 8, re, .)
1728 uint ea = M68KMAKE_GET_EA_AY_8;
1729 uint res = DX & m68ki_read_8(ea);
1731 FLAG_N = NFLAG_8(res);
1732 FLAG_C = CFLAG_CLEAR;
1733 FLAG_V = VFLAG_CLEAR;
1734 FLAG_Z = MASK_OUT_ABOVE_8(res);
1736 m68ki_write_8(ea, FLAG_Z);
1740 M68KMAKE_OP(and, 16, re, .)
1742 uint ea = M68KMAKE_GET_EA_AY_16;
1743 uint res = DX & m68ki_read_16(ea);
1745 FLAG_N = NFLAG_16(res);
1746 FLAG_C = CFLAG_CLEAR;
1747 FLAG_V = VFLAG_CLEAR;
1748 FLAG_Z = MASK_OUT_ABOVE_16(res);
1750 m68ki_write_16(ea, FLAG_Z);
1754 M68KMAKE_OP(and, 32, re, .)
1756 uint ea = M68KMAKE_GET_EA_AY_32;
1757 uint res = DX & m68ki_read_32(ea);
1759 FLAG_N = NFLAG_32(res);
1761 FLAG_C = CFLAG_CLEAR;
1762 FLAG_V = VFLAG_CLEAR;
1764 m68ki_write_32(ea, res);
1768 M68KMAKE_OP(andi, 8, ., d)
1770 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
1772 FLAG_N = NFLAG_8(FLAG_Z);
1773 FLAG_C = CFLAG_CLEAR;
1774 FLAG_V = VFLAG_CLEAR;
1778 M68KMAKE_OP(andi, 8, ., .)
1780 uint src = OPER_I_8();
1781 uint ea = M68KMAKE_GET_EA_AY_8;
1782 uint res = src & m68ki_read_8(ea);
1784 FLAG_N = NFLAG_8(res);
1786 FLAG_C = CFLAG_CLEAR;
1787 FLAG_V = VFLAG_CLEAR;
1789 m68ki_write_8(ea, res);
1793 M68KMAKE_OP(andi, 16, ., d)
1795 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
1797 FLAG_N = NFLAG_16(FLAG_Z);
1798 FLAG_C = CFLAG_CLEAR;
1799 FLAG_V = VFLAG_CLEAR;
1803 M68KMAKE_OP(andi, 16, ., .)
1805 uint src = OPER_I_16();
1806 uint ea = M68KMAKE_GET_EA_AY_16;
1807 uint res = src & m68ki_read_16(ea);
1809 FLAG_N = NFLAG_16(res);
1811 FLAG_C = CFLAG_CLEAR;
1812 FLAG_V = VFLAG_CLEAR;
1814 m68ki_write_16(ea, res);
1818 M68KMAKE_OP(andi, 32, ., d)
1820 FLAG_Z = DY &= (OPER_I_32());
1822 FLAG_N = NFLAG_32(FLAG_Z);
1823 FLAG_C = CFLAG_CLEAR;
1824 FLAG_V = VFLAG_CLEAR;
1828 M68KMAKE_OP(andi, 32, ., .)
1830 uint src = OPER_I_32();
1831 uint ea = M68KMAKE_GET_EA_AY_32;
1832 uint res = src & m68ki_read_32(ea);
1834 FLAG_N = NFLAG_32(res);
1836 FLAG_C = CFLAG_CLEAR;
1837 FLAG_V = VFLAG_CLEAR;
1839 m68ki_write_32(ea, res);
1843 M68KMAKE_OP(andi, 16, toc, .)
1845 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8());
1849 M68KMAKE_OP(andi, 16, tos, .)
1853 uint src = OPER_I_16();
1854 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
1855 m68ki_set_sr(m68ki_get_sr() & src);
1858 m68ki_exception_privilege_violation();
1862 M68KMAKE_OP(asr, 8, s, .)
1865 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1866 uint src = MASK_OUT_ABOVE_8(*r_dst);
1867 uint res = src >> shift;
1870 USE_CYCLES(shift<<CYC_SHIFT);
1873 res |= m68ki_shift_8_table[shift];
1875 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1877 FLAG_N = NFLAG_8(res);
1879 FLAG_V = VFLAG_CLEAR;
1880 FLAG_X = FLAG_C = src << (9-shift);
1884 M68KMAKE_OP(asr, 16, s, .)
1887 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1888 uint src = MASK_OUT_ABOVE_16(*r_dst);
1889 uint res = src >> shift;
1892 USE_CYCLES(shift<<CYC_SHIFT);
1895 res |= m68ki_shift_16_table[shift];
1897 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1899 FLAG_N = NFLAG_16(res);
1901 FLAG_V = VFLAG_CLEAR;
1902 FLAG_X = FLAG_C = src << (9-shift);
1906 M68KMAKE_OP(asr, 32, s, .)
1909 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1911 uint res = src >> shift;
1914 USE_CYCLES(shift<<CYC_SHIFT);
1917 res |= m68ki_shift_32_table[shift];
1921 FLAG_N = NFLAG_32(res);
1923 FLAG_V = VFLAG_CLEAR;
1924 FLAG_X = FLAG_C = src << (9-shift);
1928 M68KMAKE_OP(asr, 8, r, .)
1931 uint shift = DX & 0x3f;
1932 uint src = MASK_OUT_ABOVE_8(*r_dst);
1933 uint res = src >> shift;
1937 USE_CYCLES(shift<<CYC_SHIFT);
1942 res |= m68ki_shift_8_table[shift];
1944 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1946 FLAG_X = FLAG_C = src << (9-shift);
1947 FLAG_N = NFLAG_8(res);
1949 FLAG_V = VFLAG_CLEAR;
1959 FLAG_Z = ZFLAG_CLEAR;
1960 FLAG_V = VFLAG_CLEAR;
1964 *r_dst &= 0xffffff00;
1965 FLAG_C = CFLAG_CLEAR;
1966 FLAG_X = XFLAG_CLEAR;
1967 FLAG_N = NFLAG_CLEAR;
1969 FLAG_V = VFLAG_CLEAR;
1973 FLAG_C = CFLAG_CLEAR;
1974 FLAG_N = NFLAG_8(src);
1976 FLAG_V = VFLAG_CLEAR;
1980 M68KMAKE_OP(asr, 16, r, .)
1983 uint shift = DX & 0x3f;
1984 uint src = MASK_OUT_ABOVE_16(*r_dst);
1985 uint res = src >> shift;
1989 USE_CYCLES(shift<<CYC_SHIFT);
1994 res |= m68ki_shift_16_table[shift];
1996 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1998 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
1999 FLAG_N = NFLAG_16(res);
2001 FLAG_V = VFLAG_CLEAR;
2011 FLAG_Z = ZFLAG_CLEAR;
2012 FLAG_V = VFLAG_CLEAR;
2016 *r_dst &= 0xffff0000;
2017 FLAG_C = CFLAG_CLEAR;
2018 FLAG_X = XFLAG_CLEAR;
2019 FLAG_N = NFLAG_CLEAR;
2021 FLAG_V = VFLAG_CLEAR;
2025 FLAG_C = CFLAG_CLEAR;
2026 FLAG_N = NFLAG_16(src);
2028 FLAG_V = VFLAG_CLEAR;
2032 M68KMAKE_OP(asr, 32, r, .)
2035 uint shift = DX & 0x3f;
2037 uint res = src >> shift;
2041 USE_CYCLES(shift<<CYC_SHIFT);
2046 res |= m68ki_shift_32_table[shift];
2050 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2051 FLAG_N = NFLAG_32(res);
2053 FLAG_V = VFLAG_CLEAR;
2059 *r_dst = 0xffffffff;
2063 FLAG_Z = ZFLAG_CLEAR;
2064 FLAG_V = VFLAG_CLEAR;
2069 FLAG_C = CFLAG_CLEAR;
2070 FLAG_X = XFLAG_CLEAR;
2071 FLAG_N = NFLAG_CLEAR;
2073 FLAG_V = VFLAG_CLEAR;
2077 FLAG_C = CFLAG_CLEAR;
2078 FLAG_N = NFLAG_32(src);
2080 FLAG_V = VFLAG_CLEAR;
2084 M68KMAKE_OP(asr, 16, ., .)
2086 uint ea = M68KMAKE_GET_EA_AY_16;
2087 uint src = m68ki_read_16(ea);
2088 uint res = src >> 1;
2093 m68ki_write_16(ea, res);
2095 FLAG_N = NFLAG_16(res);
2097 FLAG_V = VFLAG_CLEAR;
2098 FLAG_C = FLAG_X = src << 8;
2102 M68KMAKE_OP(asl, 8, s, .)
2105 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2106 uint src = MASK_OUT_ABOVE_8(*r_dst);
2107 uint res = MASK_OUT_ABOVE_8(src << shift);
2110 USE_CYCLES(shift<<CYC_SHIFT);
2112 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2114 FLAG_X = FLAG_C = src << shift;
2115 FLAG_N = NFLAG_8(res);
2117 src &= m68ki_shift_8_table[shift + 1];
2118 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
2122 M68KMAKE_OP(asl, 16, s, .)
2125 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2126 uint src = MASK_OUT_ABOVE_16(*r_dst);
2127 uint res = MASK_OUT_ABOVE_16(src << shift);
2130 USE_CYCLES(shift<<CYC_SHIFT);
2132 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2134 FLAG_N = NFLAG_16(res);
2136 FLAG_X = FLAG_C = src >> (8-shift);
2137 src &= m68ki_shift_16_table[shift + 1];
2138 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2142 M68KMAKE_OP(asl, 32, s, .)
2145 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2147 uint res = MASK_OUT_ABOVE_32(src << shift);
2150 USE_CYCLES(shift<<CYC_SHIFT);
2154 FLAG_N = NFLAG_32(res);
2156 FLAG_X = FLAG_C = src >> (24-shift);
2157 src &= m68ki_shift_32_table[shift + 1];
2158 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2162 M68KMAKE_OP(asl, 8, r, .)
2165 uint shift = DX & 0x3f;
2166 uint src = MASK_OUT_ABOVE_8(*r_dst);
2167 uint res = MASK_OUT_ABOVE_8(src << shift);
2171 USE_CYCLES(shift<<CYC_SHIFT);
2175 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2176 FLAG_X = FLAG_C = src << shift;
2177 FLAG_N = NFLAG_8(res);
2179 src &= m68ki_shift_8_table[shift + 1];
2180 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
2184 *r_dst &= 0xffffff00;
2185 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
2186 FLAG_N = NFLAG_CLEAR;
2188 FLAG_V = (!(src == 0))<<7;
2192 FLAG_C = CFLAG_CLEAR;
2193 FLAG_N = NFLAG_8(src);
2195 FLAG_V = VFLAG_CLEAR;
2199 M68KMAKE_OP(asl, 16, r, .)
2202 uint shift = DX & 0x3f;
2203 uint src = MASK_OUT_ABOVE_16(*r_dst);
2204 uint res = MASK_OUT_ABOVE_16(src << shift);
2208 USE_CYCLES(shift<<CYC_SHIFT);
2212 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2213 FLAG_X = FLAG_C = (src << shift) >> 8;
2214 FLAG_N = NFLAG_16(res);
2216 src &= m68ki_shift_16_table[shift + 1];
2217 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2221 *r_dst &= 0xffff0000;
2222 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
2223 FLAG_N = NFLAG_CLEAR;
2225 FLAG_V = (!(src == 0))<<7;
2229 FLAG_C = CFLAG_CLEAR;
2230 FLAG_N = NFLAG_16(src);
2232 FLAG_V = VFLAG_CLEAR;
2236 M68KMAKE_OP(asl, 32, r, .)
2239 uint shift = DX & 0x3f;
2241 uint res = MASK_OUT_ABOVE_32(src << shift);
2245 USE_CYCLES(shift<<CYC_SHIFT);
2250 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
2251 FLAG_N = NFLAG_32(res);
2253 src &= m68ki_shift_32_table[shift + 1];
2254 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2259 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
2260 FLAG_N = NFLAG_CLEAR;
2262 FLAG_V = (!(src == 0))<<7;
2266 FLAG_C = CFLAG_CLEAR;
2267 FLAG_N = NFLAG_32(src);
2269 FLAG_V = VFLAG_CLEAR;
2273 M68KMAKE_OP(asl, 16, ., .)
2275 uint ea = M68KMAKE_GET_EA_AY_16;
2276 uint src = m68ki_read_16(ea);
2277 uint res = MASK_OUT_ABOVE_16(src << 1);
2279 m68ki_write_16(ea, res);
2281 FLAG_N = NFLAG_16(res);
2283 FLAG_X = FLAG_C = src >> 7;
2285 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
2289 M68KMAKE_OP(bcc, 8, ., .)
2293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2294 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2297 USE_CYCLES(CYC_BCC_NOTAKE_B);
2301 M68KMAKE_OP(bcc, 16, ., .)
2305 uint offset = OPER_I_16();
2307 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2308 m68ki_branch_16(offset);
2312 USE_CYCLES(CYC_BCC_NOTAKE_W);
2316 M68KMAKE_OP(bcc, 32, ., .)
2318 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2322 uint offset = OPER_I_32();
2324 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2325 m68ki_branch_32(offset);
2335 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2336 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2339 USE_CYCLES(CYC_BCC_NOTAKE_B);
2344 M68KMAKE_OP(bchg, 32, r, d)
2347 uint mask = 1 << (DX & 0x1f);
2349 FLAG_Z = *r_dst & mask;
2354 M68KMAKE_OP(bchg, 8, r, .)
2356 uint ea = M68KMAKE_GET_EA_AY_8;
2357 uint src = m68ki_read_8(ea);
2358 uint mask = 1 << (DX & 7);
2360 FLAG_Z = src & mask;
2361 m68ki_write_8(ea, src ^ mask);
2365 M68KMAKE_OP(bchg, 32, s, d)
2368 uint mask = 1 << (OPER_I_8() & 0x1f);
2370 FLAG_Z = *r_dst & mask;
2375 M68KMAKE_OP(bchg, 8, s, .)
2377 uint mask = 1 << (OPER_I_8() & 7);
2378 uint ea = M68KMAKE_GET_EA_AY_8;
2379 uint src = m68ki_read_8(ea);
2381 FLAG_Z = src & mask;
2382 m68ki_write_8(ea, src ^ mask);
2386 M68KMAKE_OP(bclr, 32, r, d)
2389 uint mask = 1 << (DX & 0x1f);
2391 FLAG_Z = *r_dst & mask;
2396 M68KMAKE_OP(bclr, 8, r, .)
2398 uint ea = M68KMAKE_GET_EA_AY_8;
2399 uint src = m68ki_read_8(ea);
2400 uint mask = 1 << (DX & 7);
2402 FLAG_Z = src & mask;
2403 m68ki_write_8(ea, src & ~mask);
2407 M68KMAKE_OP(bclr, 32, s, d)
2410 uint mask = 1 << (OPER_I_8() & 0x1f);
2412 FLAG_Z = *r_dst & mask;
2417 M68KMAKE_OP(bclr, 8, s, .)
2419 uint mask = 1 << (OPER_I_8() & 7);
2420 uint ea = M68KMAKE_GET_EA_AY_8;
2421 uint src = m68ki_read_8(ea);
2423 FLAG_Z = src & mask;
2424 m68ki_write_8(ea, src & ~mask);
2428 M68KMAKE_OP(bfchg, 32, ., d)
2430 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2432 uint word2 = OPER_I_16();
2433 uint offset = (word2>>6)&31;
2440 offset = REG_D[offset&7];
2442 width = REG_D[width&7];
2445 width = ((width-1) & 31) + 1;
2447 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2448 mask = ROR_32(mask, offset);
2450 FLAG_N = NFLAG_32(*data<<offset);
2451 FLAG_Z = *data & mask;
2452 FLAG_V = VFLAG_CLEAR;
2453 FLAG_C = CFLAG_CLEAR;
2459 m68ki_exception_illegal();
2463 M68KMAKE_OP(bfchg, 32, ., .)
2465 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2467 uint word2 = OPER_I_16();
2468 sint offset = (word2>>6)&31;
2475 uint ea = M68KMAKE_GET_EA_AY_8;
2479 offset = MAKE_INT_32(REG_D[offset&7]);
2481 width = REG_D[width&7];
2483 /* Offset is signed so we have to use ugly math =( */
2491 width = ((width-1) & 31) + 1;
2493 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2494 mask_long = mask_base >> offset;
2496 data_long = m68ki_read_32(ea);
2497 FLAG_N = NFLAG_32(data_long << offset);
2498 FLAG_Z = data_long & mask_long;
2499 FLAG_V = VFLAG_CLEAR;
2500 FLAG_C = CFLAG_CLEAR;
2502 m68ki_write_32(ea, data_long ^ mask_long);
2504 if((width + offset) > 32)
2506 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2507 data_byte = m68ki_read_8(ea+4);
2508 FLAG_Z |= (data_byte & mask_byte);
2509 m68ki_write_8(ea+4, data_byte ^ mask_byte);
2513 m68ki_exception_illegal();
2517 M68KMAKE_OP(bfclr, 32, ., d)
2519 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2521 uint word2 = OPER_I_16();
2522 uint offset = (word2>>6)&31;
2529 offset = REG_D[offset&7];
2531 width = REG_D[width&7];
2535 width = ((width-1) & 31) + 1;
2538 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2539 mask = ROR_32(mask, offset);
2541 FLAG_N = NFLAG_32(*data<<offset);
2542 FLAG_Z = *data & mask;
2543 FLAG_V = VFLAG_CLEAR;
2544 FLAG_C = CFLAG_CLEAR;
2550 m68ki_exception_illegal();
2554 M68KMAKE_OP(bfclr, 32, ., .)
2556 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2558 uint word2 = OPER_I_16();
2559 sint offset = (word2>>6)&31;
2566 uint ea = M68KMAKE_GET_EA_AY_8;
2570 offset = MAKE_INT_32(REG_D[offset&7]);
2572 width = REG_D[width&7];
2574 /* Offset is signed so we have to use ugly math =( */
2582 width = ((width-1) & 31) + 1;
2584 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2585 mask_long = mask_base >> offset;
2587 data_long = m68ki_read_32(ea);
2588 FLAG_N = NFLAG_32(data_long << offset);
2589 FLAG_Z = data_long & mask_long;
2590 FLAG_V = VFLAG_CLEAR;
2591 FLAG_C = CFLAG_CLEAR;
2593 m68ki_write_32(ea, data_long & ~mask_long);
2595 if((width + offset) > 32)
2597 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2598 data_byte = m68ki_read_8(ea+4);
2599 FLAG_Z |= (data_byte & mask_byte);
2600 m68ki_write_8(ea+4, data_byte & ~mask_byte);
2604 m68ki_exception_illegal();
2608 M68KMAKE_OP(bfexts, 32, ., d)
2610 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2612 uint word2 = OPER_I_16();
2613 uint offset = (word2>>6)&31;
2619 offset = REG_D[offset&7];
2621 width = REG_D[width&7];
2624 width = ((width-1) & 31) + 1;
2626 data = ROL_32(data, offset);
2627 FLAG_N = NFLAG_32(data);
2628 data = MAKE_INT_32(data) >> (32 - width);
2631 FLAG_V = VFLAG_CLEAR;
2632 FLAG_C = CFLAG_CLEAR;
2634 REG_D[(word2>>12)&7] = data;
2638 m68ki_exception_illegal();
2642 M68KMAKE_OP(bfexts, 32, ., .)
2644 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2646 uint word2 = OPER_I_16();
2647 sint offset = (word2>>6)&31;
2650 uint ea = M68KMAKE_GET_EA_AY_8;
2654 offset = MAKE_INT_32(REG_D[offset&7]);
2656 width = REG_D[width&7];
2658 /* Offset is signed so we have to use ugly math =( */
2666 width = ((width-1) & 31) + 1;
2668 data = m68ki_read_32(ea);
2670 data = MASK_OUT_ABOVE_32(data<<offset);
2672 if((offset+width) > 32)
2673 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2675 FLAG_N = NFLAG_32(data);
2676 data = MAKE_INT_32(data) >> (32 - width);
2679 FLAG_V = VFLAG_CLEAR;
2680 FLAG_C = CFLAG_CLEAR;
2682 REG_D[(word2 >> 12) & 7] = data;
2686 m68ki_exception_illegal();
2690 M68KMAKE_OP(bfextu, 32, ., d)
2692 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2694 uint word2 = OPER_I_16();
2695 uint offset = (word2>>6)&31;
2701 offset = REG_D[offset&7];
2703 width = REG_D[width&7];
2706 width = ((width-1) & 31) + 1;
2708 data = ROL_32(data, offset);
2709 FLAG_N = NFLAG_32(data);
2710 data >>= 32 - width;
2713 FLAG_V = VFLAG_CLEAR;
2714 FLAG_C = CFLAG_CLEAR;
2716 REG_D[(word2>>12)&7] = data;
2720 m68ki_exception_illegal();
2724 M68KMAKE_OP(bfextu, 32, ., .)
2726 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2728 uint word2 = OPER_I_16();
2729 sint offset = (word2>>6)&31;
2732 uint ea = M68KMAKE_GET_EA_AY_8;
2736 offset = MAKE_INT_32(REG_D[offset&7]);
2738 width = REG_D[width&7];
2740 /* Offset is signed so we have to use ugly math =( */
2748 width = ((width-1) & 31) + 1;
2750 data = m68ki_read_32(ea);
2751 data = MASK_OUT_ABOVE_32(data<<offset);
2753 if((offset+width) > 32)
2754 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2756 FLAG_N = NFLAG_32(data);
2757 data >>= (32 - width);
2760 FLAG_V = VFLAG_CLEAR;
2761 FLAG_C = CFLAG_CLEAR;
2763 REG_D[(word2 >> 12) & 7] = data;
2767 m68ki_exception_illegal();
2771 M68KMAKE_OP(bfffo, 32, ., d)
2773 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2775 uint word2 = OPER_I_16();
2776 uint offset = (word2>>6)&31;
2783 offset = REG_D[offset&7];
2785 width = REG_D[width&7];
2788 width = ((width-1) & 31) + 1;
2790 data = ROL_32(data, offset);
2791 FLAG_N = NFLAG_32(data);
2792 data >>= 32 - width;
2795 FLAG_V = VFLAG_CLEAR;
2796 FLAG_C = CFLAG_CLEAR;
2798 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2801 REG_D[(word2>>12)&7] = offset;
2805 m68ki_exception_illegal();
2809 M68KMAKE_OP(bfffo, 32, ., .)
2811 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2813 uint word2 = OPER_I_16();
2814 sint offset = (word2>>6)&31;
2819 uint ea = M68KMAKE_GET_EA_AY_8;
2823 offset = MAKE_INT_32(REG_D[offset&7]);
2825 width = REG_D[width&7];
2827 /* Offset is signed so we have to use ugly math =( */
2829 local_offset = offset % 8;
2830 if(local_offset < 0)
2835 width = ((width-1) & 31) + 1;
2837 data = m68ki_read_32(ea);
2838 data = MASK_OUT_ABOVE_32(data<<local_offset);
2840 if((local_offset+width) > 32)
2841 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
2843 FLAG_N = NFLAG_32(data);
2844 data >>= (32 - width);
2847 FLAG_V = VFLAG_CLEAR;
2848 FLAG_C = CFLAG_CLEAR;
2850 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2853 REG_D[(word2>>12)&7] = offset;
2857 m68ki_exception_illegal();
2861 M68KMAKE_OP(bfins, 32, ., d)
2863 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2865 uint word2 = OPER_I_16();
2866 uint offset = (word2>>6)&31;
2870 uint64 insert = REG_D[(word2>>12)&7];
2874 offset = REG_D[offset&7];
2876 width = REG_D[width&7];
2880 width = ((width-1) & 31) + 1;
2883 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2884 mask = ROR_32(mask, offset);
2886 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
2887 FLAG_N = NFLAG_32(insert);
2889 insert = ROR_32(insert, offset);
2891 FLAG_V = VFLAG_CLEAR;
2892 FLAG_C = CFLAG_CLEAR;
2899 m68ki_exception_illegal();
2903 M68KMAKE_OP(bfins, 32, ., .)
2905 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2907 uint word2 = OPER_I_16();
2908 sint offset = (word2>>6)&31;
2910 uint insert_base = REG_D[(word2>>12)&7];
2918 uint ea = M68KMAKE_GET_EA_AY_8;
2922 offset = MAKE_INT_32(REG_D[offset&7]);
2924 width = REG_D[width&7];
2926 /* Offset is signed so we have to use ugly math =( */
2934 width = ((width-1) & 31) + 1;
2936 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2937 mask_long = mask_base >> offset;
2939 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
2940 FLAG_N = NFLAG_32(insert_base);
2941 FLAG_Z = insert_base;
2942 insert_long = insert_base >> offset;
2944 data_long = m68ki_read_32(ea);
2945 FLAG_V = VFLAG_CLEAR;
2946 FLAG_C = CFLAG_CLEAR;
2948 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
2950 if((width + offset) > 32)
2952 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2953 insert_byte = MASK_OUT_ABOVE_8(insert_base);
2954 data_byte = m68ki_read_8(ea+4);
2955 FLAG_Z |= (data_byte & mask_byte);
2956 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
2960 m68ki_exception_illegal();
2964 M68KMAKE_OP(bfset, 32, ., d)
2966 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2968 uint word2 = OPER_I_16();
2969 uint offset = (word2>>6)&31;
2976 offset = REG_D[offset&7];
2978 width = REG_D[width&7];
2982 width = ((width-1) & 31) + 1;
2985 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2986 mask = ROR_32(mask, offset);
2988 FLAG_N = NFLAG_32(*data<<offset);
2989 FLAG_Z = *data & mask;
2990 FLAG_V = VFLAG_CLEAR;
2991 FLAG_C = CFLAG_CLEAR;
2997 m68ki_exception_illegal();
3001 M68KMAKE_OP(bfset, 32, ., .)
3003 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3005 uint word2 = OPER_I_16();
3006 sint offset = (word2>>6)&31;
3013 uint ea = M68KMAKE_GET_EA_AY_8;
3017 offset = MAKE_INT_32(REG_D[offset&7]);
3019 width = REG_D[width&7];
3021 /* Offset is signed so we have to use ugly math =( */
3029 width = ((width-1) & 31) + 1;
3032 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3033 mask_long = mask_base >> offset;
3035 data_long = m68ki_read_32(ea);
3036 FLAG_N = NFLAG_32(data_long << offset);
3037 FLAG_Z = data_long & mask_long;
3038 FLAG_V = VFLAG_CLEAR;
3039 FLAG_C = CFLAG_CLEAR;
3041 m68ki_write_32(ea, data_long | mask_long);
3043 if((width + offset) > 32)
3045 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3046 data_byte = m68ki_read_8(ea+4);
3047 FLAG_Z |= (data_byte & mask_byte);
3048 m68ki_write_8(ea+4, data_byte | mask_byte);
3052 m68ki_exception_illegal();
3056 M68KMAKE_OP(bftst, 32, ., d)
3058 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3060 uint word2 = OPER_I_16();
3061 uint offset = (word2>>6)&31;
3068 offset = REG_D[offset&7];
3070 width = REG_D[width&7];
3074 width = ((width-1) & 31) + 1;
3077 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3078 mask = ROR_32(mask, offset);
3080 FLAG_N = NFLAG_32(*data<<offset);
3081 FLAG_Z = *data & mask;
3082 FLAG_V = VFLAG_CLEAR;
3083 FLAG_C = CFLAG_CLEAR;
3087 m68ki_exception_illegal();
3091 M68KMAKE_OP(bftst, 32, ., .)
3093 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3095 uint word2 = OPER_I_16();
3096 sint offset = (word2>>6)&31;
3103 uint ea = M68KMAKE_GET_EA_AY_8;
3106 offset = MAKE_INT_32(REG_D[offset&7]);
3108 width = REG_D[width&7];
3110 /* Offset is signed so we have to use ugly math =( */
3118 width = ((width-1) & 31) + 1;
3121 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3122 mask_long = mask_base >> offset;
3124 data_long = m68ki_read_32(ea);
3125 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
3126 FLAG_Z = data_long & mask_long;
3127 FLAG_V = VFLAG_CLEAR;
3128 FLAG_C = CFLAG_CLEAR;
3130 if((width + offset) > 32)
3132 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3133 data_byte = m68ki_read_8(ea+4);
3134 FLAG_Z |= (data_byte & mask_byte);
3138 m68ki_exception_illegal();
3142 M68KMAKE_OP(bkpt, 0, ., .)
3144 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
3146 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
3148 m68ki_exception_illegal();
3152 M68KMAKE_OP(bra, 8, ., .)
3154 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3155 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3156 if(REG_PC == REG_PPC)
3161 M68KMAKE_OP(bra, 16, ., .)
3163 uint offset = OPER_I_16();
3165 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3166 m68ki_branch_16(offset);
3167 if(REG_PC == REG_PPC)
3172 M68KMAKE_OP(bra, 32, ., .)
3174 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3176 uint offset = OPER_I_32();
3178 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3179 m68ki_branch_32(offset);
3180 if(REG_PC == REG_PPC)
3186 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3187 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3188 if(REG_PC == REG_PPC)
3194 M68KMAKE_OP(bset, 32, r, d)
3197 uint mask = 1 << (DX & 0x1f);
3199 FLAG_Z = *r_dst & mask;
3204 M68KMAKE_OP(bset, 8, r, .)
3206 uint ea = M68KMAKE_GET_EA_AY_8;
3207 uint src = m68ki_read_8(ea);
3208 uint mask = 1 << (DX & 7);
3210 FLAG_Z = src & mask;
3211 m68ki_write_8(ea, src | mask);
3215 M68KMAKE_OP(bset, 32, s, d)
3218 uint mask = 1 << (OPER_I_8() & 0x1f);
3220 FLAG_Z = *r_dst & mask;
3225 M68KMAKE_OP(bset, 8, s, .)
3227 uint mask = 1 << (OPER_I_8() & 7);
3228 uint ea = M68KMAKE_GET_EA_AY_8;
3229 uint src = m68ki_read_8(ea);
3231 FLAG_Z = src & mask;
3232 m68ki_write_8(ea, src | mask);
3236 M68KMAKE_OP(bsr, 8, ., .)
3238 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3239 m68ki_push_32(REG_PC);
3240 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3244 M68KMAKE_OP(bsr, 16, ., .)
3246 uint offset = OPER_I_16();
3247 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3248 m68ki_push_32(REG_PC);
3250 m68ki_branch_16(offset);
3254 M68KMAKE_OP(bsr, 32, ., .)
3256 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3258 uint offset = OPER_I_32();
3259 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3260 m68ki_push_32(REG_PC);
3262 m68ki_branch_32(offset);
3267 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3268 m68ki_push_32(REG_PC);
3269 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3274 M68KMAKE_OP(btst, 32, r, d)
3276 FLAG_Z = DY & (1 << (DX & 0x1f));
3280 M68KMAKE_OP(btst, 8, r, .)
3282 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
3286 M68KMAKE_OP(btst, 32, s, d)
3288 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
3292 M68KMAKE_OP(btst, 8, s, .)
3294 uint bit = OPER_I_8() & 7;
3296 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
3300 M68KMAKE_OP(callm, 32, ., .)
3302 /* note: watch out for pcrelative modes */
3303 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
3305 uint ea = M68KMAKE_GET_EA_AY_32;
3307 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3309 (void)ea; /* just to avoid an 'unused variable' warning */
3310 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
3311 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
3312 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
3315 m68ki_exception_illegal();
3319 M68KMAKE_OP(cas, 8, ., .)
3321 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3323 uint word2 = OPER_I_16();
3324 uint ea = M68KMAKE_GET_EA_AY_8;
3325 uint dest = m68ki_read_8(ea);
3326 uint* compare = ®_D[word2 & 7];
3327 uint res = dest - MASK_OUT_ABOVE_8(*compare);
3329 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3330 FLAG_N = NFLAG_8(res);
3331 FLAG_Z = MASK_OUT_ABOVE_8(res);
3332 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
3333 FLAG_C = CFLAG_8(res);
3336 *compare = MASK_OUT_BELOW_8(*compare) | dest;
3340 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
3344 m68ki_exception_illegal();
3348 M68KMAKE_OP(cas, 16, ., .)
3350 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3352 uint word2 = OPER_I_16();
3353 uint ea = M68KMAKE_GET_EA_AY_16;
3354 uint dest = m68ki_read_16(ea);
3355 uint* compare = ®_D[word2 & 7];
3356 uint res = dest - MASK_OUT_ABOVE_16(*compare);
3358 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3359 FLAG_N = NFLAG_16(res);
3360 FLAG_Z = MASK_OUT_ABOVE_16(res);
3361 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
3362 FLAG_C = CFLAG_16(res);
3365 *compare = MASK_OUT_BELOW_16(*compare) | dest;
3369 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
3373 m68ki_exception_illegal();
3377 M68KMAKE_OP(cas, 32, ., .)
3379 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3381 uint word2 = OPER_I_16();
3382 uint ea = M68KMAKE_GET_EA_AY_32;
3383 uint dest = m68ki_read_32(ea);
3384 uint* compare = ®_D[word2 & 7];
3385 uint res = dest - *compare;
3387 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3388 FLAG_N = NFLAG_32(res);
3389 FLAG_Z = MASK_OUT_ABOVE_32(res);
3390 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
3391 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
3398 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
3402 m68ki_exception_illegal();
3406 M68KMAKE_OP(cas2, 16, ., .)
3408 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3410 uint word2 = OPER_I_32();
3411 uint* compare1 = ®_D[(word2 >> 16) & 7];
3412 uint ea1 = REG_DA[(word2 >> 28) & 15];
3413 uint dest1 = m68ki_read_16(ea1);
3414 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
3415 uint* compare2 = ®_D[word2 & 7];
3416 uint ea2 = REG_DA[(word2 >> 12) & 15];
3417 uint dest2 = m68ki_read_16(ea2);
3420 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3421 FLAG_N = NFLAG_16(res1);
3422 FLAG_Z = MASK_OUT_ABOVE_16(res1);
3423 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
3424 FLAG_C = CFLAG_16(res1);
3428 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
3430 FLAG_N = NFLAG_16(res2);
3431 FLAG_Z = MASK_OUT_ABOVE_16(res2);
3432 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
3433 FLAG_C = CFLAG_16(res2);
3438 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
3439 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
3443 *compare1 = BIT_1F(word2) ? (uint)MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
3444 *compare2 = BIT_F(word2) ? (uint)MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
3447 m68ki_exception_illegal();
3451 M68KMAKE_OP(cas2, 32, ., .)
3453 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3455 uint word2 = OPER_I_32();
3456 uint* compare1 = ®_D[(word2 >> 16) & 7];
3457 uint ea1 = REG_DA[(word2 >> 28) & 15];
3458 uint dest1 = m68ki_read_32(ea1);
3459 uint res1 = dest1 - *compare1;
3460 uint* compare2 = ®_D[word2 & 7];
3461 uint ea2 = REG_DA[(word2 >> 12) & 15];
3462 uint dest2 = m68ki_read_32(ea2);
3465 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3466 FLAG_N = NFLAG_32(res1);
3467 FLAG_Z = MASK_OUT_ABOVE_32(res1);
3468 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
3469 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
3473 res2 = dest2 - *compare2;
3475 FLAG_N = NFLAG_32(res2);
3476 FLAG_Z = MASK_OUT_ABOVE_32(res2);
3477 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
3478 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
3483 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
3484 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
3492 m68ki_exception_illegal();
3496 M68KMAKE_OP(chk, 16, ., d)
3498 sint src = MAKE_INT_16(DX);
3499 sint bound = MAKE_INT_16(DY);
3501 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3502 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3503 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3505 if(src >= 0 && src <= bound)
3509 FLAG_N = (src < 0)<<7;
3510 m68ki_exception_trap(EXCEPTION_CHK);
3514 M68KMAKE_OP(chk, 16, ., .)
3516 sint src = MAKE_INT_16(DX);
3517 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3519 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3520 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3521 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3523 if(src >= 0 && src <= bound)
3527 FLAG_N = (src < 0)<<7;
3528 m68ki_exception_trap(EXCEPTION_CHK);
3532 M68KMAKE_OP(chk, 32, ., d)
3534 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3536 sint src = MAKE_INT_32(DX);
3537 sint bound = MAKE_INT_32(DY);
3539 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3540 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3541 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3543 if(src >= 0 && src <= bound)
3547 FLAG_N = (src < 0)<<7;
3548 m68ki_exception_trap(EXCEPTION_CHK);
3551 m68ki_exception_illegal();
3555 M68KMAKE_OP(chk, 32, ., .)
3557 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3559 sint src = MAKE_INT_32(DX);
3560 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
3562 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3563 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3564 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3566 if(src >= 0 && src <= bound)
3570 FLAG_N = (src < 0)<<7;
3571 m68ki_exception_trap(EXCEPTION_CHK);
3574 m68ki_exception_illegal();
3578 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
3580 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3582 uint word2 = OPER_I_16();
3583 sint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3584 uint ea = EA_PCDI_8();
3585 sint lower_bound = m68ki_read_pcrel_8(ea);
3586 sint upper_bound = m68ki_read_pcrel_8(ea + 1);
3589 compare = (int32)(int8)compare;
3591 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3593 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3595 if(COND_CS() && BIT_B(word2))
3596 m68ki_exception_trap(EXCEPTION_CHK);
3601 m68ki_exception_illegal();
3605 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
3607 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3609 uint word2 = OPER_I_16();
3610 sint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3611 uint ea = EA_PCIX_8();
3612 sint lower_bound = m68ki_read_pcrel_8(ea);
3613 sint upper_bound = m68ki_read_pcrel_8(ea + 1);
3616 compare = (int32)(int8)compare;
3617 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||, faster operation short circuits
3619 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3621 if(COND_CS() && BIT_B(word2))
3622 m68ki_exception_trap(EXCEPTION_CHK);
3626 m68ki_exception_illegal();
3630 M68KMAKE_OP(chk2cmp2, 8, ., .)
3632 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3634 uint word2 = OPER_I_16();
3635 sint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3636 uint ea = M68KMAKE_GET_EA_AY_8;
3637 sint lower_bound = (int8)m68ki_read_8(ea);
3638 sint upper_bound = (int8)m68ki_read_8(ea + 1);
3641 compare = (int32)(int8)compare;
3643 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3645 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3647 if(COND_CS() && BIT_B(word2))
3648 m68ki_exception_trap(EXCEPTION_CHK);
3651 m68ki_exception_illegal();
3655 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
3657 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3659 uint word2 = OPER_I_16();
3660 sint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3661 uint ea = EA_PCDI_16();
3662 sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
3663 sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
3666 compare = (int32)(int16)compare;
3667 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3669 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3671 if(COND_CS() && BIT_B(word2))
3672 m68ki_exception_trap(EXCEPTION_CHK);
3675 m68ki_exception_illegal();
3679 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
3681 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3683 uint word2 = OPER_I_16();
3684 sint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3685 uint ea = EA_PCIX_16();
3686 sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
3687 sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
3690 compare = (int32)(int16)compare;
3691 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3693 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3695 if(COND_CS() && BIT_B(word2))
3696 m68ki_exception_trap(EXCEPTION_CHK);
3699 m68ki_exception_illegal();
3703 M68KMAKE_OP(chk2cmp2, 16, ., .)
3705 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3707 uint word2 = OPER_I_16();
3708 sint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3709 uint ea = M68KMAKE_GET_EA_AY_16;
3710 sint lower_bound = (int16)m68ki_read_16(ea);
3711 sint upper_bound = (int16)m68ki_read_16(ea + 2);
3714 compare = (int32)(int16)compare;
3715 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3717 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3719 if(COND_CS() && BIT_B(word2))
3720 m68ki_exception_trap(EXCEPTION_CHK);
3723 m68ki_exception_illegal();
3727 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
3729 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3731 uint word2 = OPER_I_16();
3732 sint compare = REG_DA[(word2 >> 12) & 15];
3733 uint ea = EA_PCDI_32();
3734 sint lower_bound = m68ki_read_pcrel_32(ea);
3735 sint upper_bound = m68ki_read_pcrel_32(ea + 4);
3737 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3739 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3741 if(COND_CS() && BIT_B(word2))
3742 m68ki_exception_trap(EXCEPTION_CHK);
3745 m68ki_exception_illegal();
3749 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
3751 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3753 uint word2 = OPER_I_16();
3754 sint compare = REG_DA[(word2 >> 12) & 15];
3755 uint ea = EA_PCIX_32();
3756 sint lower_bound = m68ki_read_32(ea);
3757 sint upper_bound = m68ki_read_32(ea + 4);
3759 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3761 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3763 if(COND_CS() && BIT_B(word2))
3764 m68ki_exception_trap(EXCEPTION_CHK);
3767 m68ki_exception_illegal();
3771 M68KMAKE_OP(chk2cmp2, 32, ., .)
3773 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3775 uint word2 = OPER_I_16();
3776 // JFF changed the logic. chk2/cmp2 uses signed values, not unsigned
3777 sint compare = REG_DA[(word2 >> 12) & 15];
3778 uint ea = M68KMAKE_GET_EA_AY_32;
3779 sint lower_bound = m68ki_read_32(ea);
3780 sint upper_bound = m68ki_read_32(ea + 4);
3782 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3784 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3786 if(COND_CS() && BIT_B(word2))
3787 m68ki_exception_trap(EXCEPTION_CHK);
3790 m68ki_exception_illegal();
3794 M68KMAKE_OP(clr, 8, ., d)
3798 FLAG_N = NFLAG_CLEAR;
3799 FLAG_V = VFLAG_CLEAR;
3800 FLAG_C = CFLAG_CLEAR;
3805 M68KMAKE_OP(clr, 8, ., .)
3807 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
3809 FLAG_N = NFLAG_CLEAR;
3810 FLAG_V = VFLAG_CLEAR;
3811 FLAG_C = CFLAG_CLEAR;
3816 M68KMAKE_OP(clr, 16, ., d)
3820 FLAG_N = NFLAG_CLEAR;
3821 FLAG_V = VFLAG_CLEAR;
3822 FLAG_C = CFLAG_CLEAR;
3827 M68KMAKE_OP(clr, 16, ., .)
3829 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
3831 FLAG_N = NFLAG_CLEAR;
3832 FLAG_V = VFLAG_CLEAR;
3833 FLAG_C = CFLAG_CLEAR;
3838 M68KMAKE_OP(clr, 32, ., d)
3842 FLAG_N = NFLAG_CLEAR;
3843 FLAG_V = VFLAG_CLEAR;
3844 FLAG_C = CFLAG_CLEAR;
3849 M68KMAKE_OP(clr, 32, ., .)
3851 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
3853 FLAG_N = NFLAG_CLEAR;
3854 FLAG_V = VFLAG_CLEAR;
3855 FLAG_C = CFLAG_CLEAR;
3860 M68KMAKE_OP(cmp, 8, ., d)
3862 uint src = MASK_OUT_ABOVE_8(DY);
3863 uint dst = MASK_OUT_ABOVE_8(DX);
3864 uint res = dst - src;
3866 FLAG_N = NFLAG_8(res);
3867 FLAG_Z = MASK_OUT_ABOVE_8(res);
3868 FLAG_V = VFLAG_SUB_8(src, dst, res);
3869 FLAG_C = CFLAG_8(res);
3873 M68KMAKE_OP(cmp, 8, ., .)
3875 uint src = M68KMAKE_GET_OPER_AY_8;
3876 uint dst = MASK_OUT_ABOVE_8(DX);
3877 uint res = dst - src;
3879 FLAG_N = NFLAG_8(res);
3880 FLAG_Z = MASK_OUT_ABOVE_8(res);
3881 FLAG_V = VFLAG_SUB_8(src, dst, res);
3882 FLAG_C = CFLAG_8(res);
3886 M68KMAKE_OP(cmp, 16, ., d)
3888 uint src = MASK_OUT_ABOVE_16(DY);
3889 uint dst = MASK_OUT_ABOVE_16(DX);
3890 uint res = dst - src;
3892 FLAG_N = NFLAG_16(res);
3893 FLAG_Z = MASK_OUT_ABOVE_16(res);
3894 FLAG_V = VFLAG_SUB_16(src, dst, res);
3895 FLAG_C = CFLAG_16(res);
3899 M68KMAKE_OP(cmp, 16, ., a)
3901 uint src = MASK_OUT_ABOVE_16(AY);
3902 uint dst = MASK_OUT_ABOVE_16(DX);
3903 uint res = dst - src;
3905 FLAG_N = NFLAG_16(res);
3906 FLAG_Z = MASK_OUT_ABOVE_16(res);
3907 FLAG_V = VFLAG_SUB_16(src, dst, res);
3908 FLAG_C = CFLAG_16(res);
3912 M68KMAKE_OP(cmp, 16, ., .)
3914 uint src = M68KMAKE_GET_OPER_AY_16;
3915 uint dst = MASK_OUT_ABOVE_16(DX);
3916 uint res = dst - src;
3918 FLAG_N = NFLAG_16(res);
3919 FLAG_Z = MASK_OUT_ABOVE_16(res);
3920 FLAG_V = VFLAG_SUB_16(src, dst, res);
3921 FLAG_C = CFLAG_16(res);
3925 M68KMAKE_OP(cmp, 32, ., d)
3929 uint res = dst - src;
3931 FLAG_N = NFLAG_32(res);
3932 FLAG_Z = MASK_OUT_ABOVE_32(res);
3933 FLAG_V = VFLAG_SUB_32(src, dst, res);
3934 FLAG_C = CFLAG_SUB_32(src, dst, res);
3938 M68KMAKE_OP(cmp, 32, ., a)
3942 uint res = dst - src;
3944 FLAG_N = NFLAG_32(res);
3945 FLAG_Z = MASK_OUT_ABOVE_32(res);
3946 FLAG_V = VFLAG_SUB_32(src, dst, res);
3947 FLAG_C = CFLAG_SUB_32(src, dst, res);
3951 M68KMAKE_OP(cmp, 32, ., .)
3953 uint src = M68KMAKE_GET_OPER_AY_32;
3955 uint res = dst - src;
3957 FLAG_N = NFLAG_32(res);
3958 FLAG_Z = MASK_OUT_ABOVE_32(res);
3959 FLAG_V = VFLAG_SUB_32(src, dst, res);
3960 FLAG_C = CFLAG_SUB_32(src, dst, res);
3964 M68KMAKE_OP(cmpa, 16, ., d)
3966 uint src = MAKE_INT_16(DY);
3968 uint res = dst - src;
3970 FLAG_N = NFLAG_32(res);
3971 FLAG_Z = MASK_OUT_ABOVE_32(res);
3972 FLAG_V = VFLAG_SUB_32(src, dst, res);
3973 FLAG_C = CFLAG_SUB_32(src, dst, res);
3977 M68KMAKE_OP(cmpa, 16, ., a)
3979 uint src = MAKE_INT_16(AY);
3981 uint res = dst - src;
3983 FLAG_N = NFLAG_32(res);
3984 FLAG_Z = MASK_OUT_ABOVE_32(res);
3985 FLAG_V = VFLAG_SUB_32(src, dst, res);
3986 FLAG_C = CFLAG_SUB_32(src, dst, res);
3990 M68KMAKE_OP(cmpa, 16, ., .)
3992 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3994 uint res = dst - src;
3996 FLAG_N = NFLAG_32(res);
3997 FLAG_Z = MASK_OUT_ABOVE_32(res);
3998 FLAG_V = VFLAG_SUB_32(src, dst, res);
3999 FLAG_C = CFLAG_SUB_32(src, dst, res);
4003 M68KMAKE_OP(cmpa, 32, ., d)
4007 uint res = dst - src;
4009 FLAG_N = NFLAG_32(res);
4010 FLAG_Z = MASK_OUT_ABOVE_32(res);
4011 FLAG_V = VFLAG_SUB_32(src, dst, res);
4012 FLAG_C = CFLAG_SUB_32(src, dst, res);
4016 M68KMAKE_OP(cmpa, 32, ., a)
4020 uint res = dst - src;
4022 FLAG_N = NFLAG_32(res);
4023 FLAG_Z = MASK_OUT_ABOVE_32(res);
4024 FLAG_V = VFLAG_SUB_32(src, dst, res);
4025 FLAG_C = CFLAG_SUB_32(src, dst, res);
4029 M68KMAKE_OP(cmpa, 32, ., .)
4031 uint src = M68KMAKE_GET_OPER_AY_32;
4033 uint res = dst - src;
4035 FLAG_N = NFLAG_32(res);
4036 FLAG_Z = MASK_OUT_ABOVE_32(res);
4037 FLAG_V = VFLAG_SUB_32(src, dst, res);
4038 FLAG_C = CFLAG_SUB_32(src, dst, res);
4042 M68KMAKE_OP(cmpi, 8, ., d)
4044 uint src = OPER_I_8();
4045 uint dst = MASK_OUT_ABOVE_8(DY);
4046 uint res = dst - src;
4048 FLAG_N = NFLAG_8(res);
4049 FLAG_Z = MASK_OUT_ABOVE_8(res);
4050 FLAG_V = VFLAG_SUB_8(src, dst, res);
4051 FLAG_C = CFLAG_8(res);
4055 M68KMAKE_OP(cmpi, 8, ., .)
4057 uint src = OPER_I_8();
4058 uint dst = M68KMAKE_GET_OPER_AY_8;
4059 uint res = dst - src;
4061 FLAG_N = NFLAG_8(res);
4062 FLAG_Z = MASK_OUT_ABOVE_8(res);
4063 FLAG_V = VFLAG_SUB_8(src, dst, res);
4064 FLAG_C = CFLAG_8(res);
4068 M68KMAKE_OP(cmpi, 8, ., pcdi)
4070 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4072 uint src = OPER_I_8();
4073 uint dst = OPER_PCDI_8();
4074 uint res = dst - src;
4076 FLAG_N = NFLAG_8(res);
4077 FLAG_Z = MASK_OUT_ABOVE_8(res);
4078 FLAG_V = VFLAG_SUB_8(src, dst, res);
4079 FLAG_C = CFLAG_8(res);
4082 m68ki_exception_illegal();
4086 M68KMAKE_OP(cmpi, 8, ., pcix)
4088 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4090 uint src = OPER_I_8();
4091 uint dst = OPER_PCIX_8();
4092 uint res = dst - src;
4094 FLAG_N = NFLAG_8(res);
4095 FLAG_Z = MASK_OUT_ABOVE_8(res);
4096 FLAG_V = VFLAG_SUB_8(src, dst, res);
4097 FLAG_C = CFLAG_8(res);
4100 m68ki_exception_illegal();
4104 M68KMAKE_OP(cmpi, 16, ., d)
4106 uint src = OPER_I_16();
4107 uint dst = MASK_OUT_ABOVE_16(DY);
4108 uint res = dst - src;
4110 FLAG_N = NFLAG_16(res);
4111 FLAG_Z = MASK_OUT_ABOVE_16(res);
4112 FLAG_V = VFLAG_SUB_16(src, dst, res);
4113 FLAG_C = CFLAG_16(res);
4117 M68KMAKE_OP(cmpi, 16, ., .)
4119 uint src = OPER_I_16();
4120 uint dst = M68KMAKE_GET_OPER_AY_16;
4121 uint res = dst - src;
4123 FLAG_N = NFLAG_16(res);
4124 FLAG_Z = MASK_OUT_ABOVE_16(res);
4125 FLAG_V = VFLAG_SUB_16(src, dst, res);
4126 FLAG_C = CFLAG_16(res);
4130 M68KMAKE_OP(cmpi, 16, ., pcdi)
4132 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4134 uint src = OPER_I_16();
4135 uint dst = OPER_PCDI_16();
4136 uint res = dst - src;
4138 FLAG_N = NFLAG_16(res);
4139 FLAG_Z = MASK_OUT_ABOVE_16(res);
4140 FLAG_V = VFLAG_SUB_16(src, dst, res);
4141 FLAG_C = CFLAG_16(res);
4144 m68ki_exception_illegal();
4148 M68KMAKE_OP(cmpi, 16, ., pcix)
4150 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4152 uint src = OPER_I_16();
4153 uint dst = OPER_PCIX_16();
4154 uint res = dst - src;
4156 FLAG_N = NFLAG_16(res);
4157 FLAG_Z = MASK_OUT_ABOVE_16(res);
4158 FLAG_V = VFLAG_SUB_16(src, dst, res);
4159 FLAG_C = CFLAG_16(res);
4162 m68ki_exception_illegal();
4166 M68KMAKE_OP(cmpi, 32, ., d)
4168 uint src = OPER_I_32();
4170 uint res = dst - src;
4172 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
4173 FLAG_N = NFLAG_32(res);
4174 FLAG_Z = MASK_OUT_ABOVE_32(res);
4175 FLAG_V = VFLAG_SUB_32(src, dst, res);
4176 FLAG_C = CFLAG_SUB_32(src, dst, res);
4180 M68KMAKE_OP(cmpi, 32, ., .)
4182 uint src = OPER_I_32();
4183 uint dst = M68KMAKE_GET_OPER_AY_32;
4184 uint res = dst - src;
4186 FLAG_N = NFLAG_32(res);
4187 FLAG_Z = MASK_OUT_ABOVE_32(res);
4188 FLAG_V = VFLAG_SUB_32(src, dst, res);
4189 FLAG_C = CFLAG_SUB_32(src, dst, res);
4193 M68KMAKE_OP(cmpi, 32, ., pcdi)
4195 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4197 uint src = OPER_I_32();
4198 uint dst = OPER_PCDI_32();
4199 uint res = dst - src;
4201 FLAG_N = NFLAG_32(res);
4202 FLAG_Z = MASK_OUT_ABOVE_32(res);
4203 FLAG_V = VFLAG_SUB_32(src, dst, res);
4204 FLAG_C = CFLAG_SUB_32(src, dst, res);
4207 m68ki_exception_illegal();
4211 M68KMAKE_OP(cmpi, 32, ., pcix)
4213 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4215 uint src = OPER_I_32();
4216 uint dst = OPER_PCIX_32();
4217 uint res = dst - src;
4219 FLAG_N = NFLAG_32(res);
4220 FLAG_Z = MASK_OUT_ABOVE_32(res);
4221 FLAG_V = VFLAG_SUB_32(src, dst, res);
4222 FLAG_C = CFLAG_SUB_32(src, dst, res);
4225 m68ki_exception_illegal();
4229 M68KMAKE_OP(cmpm, 8, ., ax7)
4231 uint src = OPER_AY_PI_8();
4232 uint dst = OPER_A7_PI_8();
4233 uint res = dst - src;
4235 FLAG_N = NFLAG_8(res);
4236 FLAG_Z = MASK_OUT_ABOVE_8(res);
4237 FLAG_V = VFLAG_SUB_8(src, dst, res);
4238 FLAG_C = CFLAG_8(res);
4242 M68KMAKE_OP(cmpm, 8, ., ay7)
4244 uint src = OPER_A7_PI_8();
4245 uint dst = OPER_AX_PI_8();
4246 uint res = dst - src;
4248 FLAG_N = NFLAG_8(res);
4249 FLAG_Z = MASK_OUT_ABOVE_8(res);
4250 FLAG_V = VFLAG_SUB_8(src, dst, res);
4251 FLAG_C = CFLAG_8(res);
4255 M68KMAKE_OP(cmpm, 8, ., axy7)
4257 uint src = OPER_A7_PI_8();
4258 uint dst = OPER_A7_PI_8();
4259 uint res = dst - src;
4261 FLAG_N = NFLAG_8(res);
4262 FLAG_Z = MASK_OUT_ABOVE_8(res);
4263 FLAG_V = VFLAG_SUB_8(src, dst, res);
4264 FLAG_C = CFLAG_8(res);
4268 M68KMAKE_OP(cmpm, 8, ., .)
4270 uint src = OPER_AY_PI_8();
4271 uint dst = OPER_AX_PI_8();
4272 uint res = dst - src;
4274 FLAG_N = NFLAG_8(res);
4275 FLAG_Z = MASK_OUT_ABOVE_8(res);
4276 FLAG_V = VFLAG_SUB_8(src, dst, res);
4277 FLAG_C = CFLAG_8(res);
4281 M68KMAKE_OP(cmpm, 16, ., .)
4283 uint src = OPER_AY_PI_16();
4284 uint dst = OPER_AX_PI_16();
4285 uint res = dst - src;
4287 FLAG_N = NFLAG_16(res);
4288 FLAG_Z = MASK_OUT_ABOVE_16(res);
4289 FLAG_V = VFLAG_SUB_16(src, dst, res);
4290 FLAG_C = CFLAG_16(res);
4294 M68KMAKE_OP(cmpm, 32, ., .)
4296 uint src = OPER_AY_PI_32();
4297 uint dst = OPER_AX_PI_32();
4298 uint res = dst - src;
4300 FLAG_N = NFLAG_32(res);
4301 FLAG_Z = MASK_OUT_ABOVE_32(res);
4302 FLAG_V = VFLAG_SUB_32(src, dst, res);
4303 FLAG_C = CFLAG_SUB_32(src, dst, res);
4307 M68KMAKE_OP(cpbcc, 32, ., .)
4309 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4311 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4312 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4313 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4316 m68ki_exception_1111();
4320 M68KMAKE_OP(cpdbcc, 32, ., .)
4322 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4324 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4325 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4326 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4329 m68ki_exception_1111();
4333 M68KMAKE_OP(cpgen, 32, ., .)
4335 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4337 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4338 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4339 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4342 m68ki_exception_1111();
4346 M68KMAKE_OP(cpscc, 32, ., .)
4348 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4350 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4351 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4352 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4355 m68ki_exception_1111();
4359 M68KMAKE_OP(cptrapcc, 32, ., .)
4361 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4363 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4364 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4365 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4366 // JFF: unsupported, but at least if the trap doesn't occur, app should still work, so at least PC increase is correct
4370 m68ki_exception_1111();
4374 M68KMAKE_OP(dbt, 16, ., .)
4380 M68KMAKE_OP(dbf, 16, ., .)
4383 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4385 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4388 uint offset = OPER_I_16();
4390 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4391 m68ki_branch_16(offset);
4392 USE_CYCLES(CYC_DBCC_F_NOEXP);
4396 USE_CYCLES(CYC_DBCC_F_EXP);
4400 M68KMAKE_OP(dbcc, 16, ., .)
4405 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4407 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4410 uint offset = OPER_I_16();
4412 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4413 m68ki_branch_16(offset);
4414 USE_CYCLES(CYC_DBCC_F_NOEXP);
4418 USE_CYCLES(CYC_DBCC_F_EXP);
4425 M68KMAKE_OP(divs, 16, ., d)
4428 sint src = MAKE_INT_16(DY);
4434 if((uint32)*r_dst == 0x80000000 && src == -1)
4437 FLAG_N = NFLAG_CLEAR;
4438 FLAG_V = VFLAG_CLEAR;
4439 FLAG_C = CFLAG_CLEAR;
4444 quotient = MAKE_INT_32(*r_dst) / src;
4445 remainder = MAKE_INT_32(*r_dst) % src;
4447 if(quotient == MAKE_INT_16(quotient))
4450 FLAG_N = NFLAG_16(quotient);
4451 FLAG_V = VFLAG_CLEAR;
4452 FLAG_C = CFLAG_CLEAR;
4453 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4459 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4463 M68KMAKE_OP(divs, 16, ., .)
4466 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4472 if((uint32)*r_dst == 0x80000000 && src == -1)
4475 FLAG_N = NFLAG_CLEAR;
4476 FLAG_V = VFLAG_CLEAR;
4477 FLAG_C = CFLAG_CLEAR;
4482 quotient = MAKE_INT_32(*r_dst) / src;
4483 remainder = MAKE_INT_32(*r_dst) % src;
4485 if(quotient == MAKE_INT_16(quotient))
4488 FLAG_N = NFLAG_16(quotient);
4489 FLAG_V = VFLAG_CLEAR;
4490 FLAG_C = CFLAG_CLEAR;
4491 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4497 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4501 M68KMAKE_OP(divu, 16, ., d)
4504 uint src = MASK_OUT_ABOVE_16(DY);
4508 uint quotient = *r_dst / src;
4509 uint remainder = *r_dst % src;
4511 if(quotient < 0x10000)
4514 FLAG_N = NFLAG_16(quotient);
4515 FLAG_V = VFLAG_CLEAR;
4516 FLAG_C = CFLAG_CLEAR;
4517 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4523 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4527 M68KMAKE_OP(divu, 16, ., .)
4530 uint src = M68KMAKE_GET_OPER_AY_16;
4534 uint quotient = *r_dst / src;
4535 uint remainder = *r_dst % src;
4537 if(quotient < 0x10000)
4540 FLAG_N = NFLAG_16(quotient);
4541 FLAG_V = VFLAG_CLEAR;
4542 FLAG_C = CFLAG_CLEAR;
4543 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4549 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4553 M68KMAKE_OP(divl, 32, ., d)
4557 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4559 uint word2 = OPER_I_16();
4560 uint64 divisor = DY;
4561 uint64 dividend = 0;
4562 uint64 quotient = 0;
4563 uint64 remainder = 0;
4567 if(BIT_A(word2)) /* 64 bit */
4569 dividend = REG_D[word2 & 7];
4571 dividend |= REG_D[(word2 >> 12) & 7];
4573 if(BIT_B(word2)) /* signed */
4575 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4576 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4577 if((sint64)quotient != (sint64)((sint32)quotient))
4585 quotient = dividend / divisor;
4586 if(quotient > 0xffffffff)
4591 remainder = dividend % divisor;
4596 dividend = REG_D[(word2 >> 12) & 7];
4597 if(BIT_B(word2)) /* signed */
4599 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4600 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4604 quotient = dividend / divisor;
4605 remainder = dividend % divisor;
4609 REG_D[word2 & 7] = remainder;
4610 REG_D[(word2 >> 12) & 7] = quotient;
4612 FLAG_N = NFLAG_32(quotient);
4614 FLAG_V = VFLAG_CLEAR;
4615 FLAG_C = CFLAG_CLEAR;
4618 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4621 m68ki_exception_illegal();
4625 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4627 uint word2 = OPER_I_16();
4629 uint dividend_hi = REG_D[word2 & 7];
4630 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4633 uint dividend_neg = 0;
4634 uint divisor_neg = 0;
4640 /* quad / long : long quotient, long remainder */
4643 if(BIT_B(word2)) /* signed */
4645 /* special case in signed divide */
4646 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4648 REG_D[word2 & 7] = 0;
4649 REG_D[(word2 >> 12) & 7] = 0x80000000;
4652 FLAG_Z = ZFLAG_CLEAR;
4653 FLAG_V = VFLAG_CLEAR;
4654 FLAG_C = CFLAG_CLEAR;
4657 if(GET_MSB_32(dividend_hi))
4660 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4661 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4663 if(GET_MSB_32(divisor))
4666 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4671 /* if the upper long is greater than the divisor, we're overflowing. */
4672 if(dividend_hi >= divisor)
4678 for(i = 31; i >= 0; i--)
4681 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4682 if(remainder >= divisor)
4684 remainder -= divisor;
4688 for(i = 31; i >= 0; i--)
4691 overflow = GET_MSB_32(remainder);
4692 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4693 if(remainder >= divisor || overflow)
4695 remainder -= divisor;
4700 if(BIT_B(word2)) /* signed */
4702 if(quotient > 0x7fffffff)
4709 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4710 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4713 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4716 REG_D[word2 & 7] = remainder;
4717 REG_D[(word2 >> 12) & 7] = quotient;
4719 FLAG_N = NFLAG_32(quotient);
4721 FLAG_V = VFLAG_CLEAR;
4722 FLAG_C = CFLAG_CLEAR;
4726 /* long / long: long quotient, maybe long remainder */
4727 if(BIT_B(word2)) /* signed */
4729 /* Special case in divide */
4730 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4733 FLAG_Z = ZFLAG_CLEAR;
4734 FLAG_V = VFLAG_CLEAR;
4735 FLAG_C = CFLAG_CLEAR;
4736 REG_D[(word2 >> 12) & 7] = 0x80000000;
4737 REG_D[word2 & 7] = 0;
4740 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4741 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4745 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4746 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4749 FLAG_N = NFLAG_32(quotient);
4751 FLAG_V = VFLAG_CLEAR;
4752 FLAG_C = CFLAG_CLEAR;
4755 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4758 m68ki_exception_illegal();
4764 M68KMAKE_OP(divl, 32, ., .)
4768 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4770 uint word2 = OPER_I_16();
4771 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
4772 uint64 dividend = 0;
4773 uint64 quotient = 0;
4774 uint64 remainder = 0;
4778 if(BIT_A(word2)) /* 64 bit */
4780 dividend = REG_D[word2 & 7];
4782 dividend |= REG_D[(word2 >> 12) & 7];
4784 if(BIT_B(word2)) /* signed */
4786 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4787 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4788 if((sint64)quotient != (sint64)((sint32)quotient))
4796 quotient = dividend / divisor;
4797 if(quotient > 0xffffffff)
4802 remainder = dividend % divisor;
4807 dividend = REG_D[(word2 >> 12) & 7];
4808 if(BIT_B(word2)) /* signed */
4810 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4811 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4815 quotient = dividend / divisor;
4816 remainder = dividend % divisor;
4820 REG_D[word2 & 7] = remainder;
4821 REG_D[(word2 >> 12) & 7] = quotient;
4823 FLAG_N = NFLAG_32(quotient);
4825 FLAG_V = VFLAG_CLEAR;
4826 FLAG_C = CFLAG_CLEAR;
4829 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4832 m68ki_exception_illegal();
4836 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4838 uint word2 = OPER_I_16();
4839 uint divisor = M68KMAKE_GET_OPER_AY_32;
4840 uint dividend_hi = REG_D[word2 & 7];
4841 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4844 uint dividend_neg = 0;
4845 uint divisor_neg = 0;
4851 /* quad / long : long quotient, long remainder */
4854 if(BIT_B(word2)) /* signed */
4856 /* special case in signed divide */
4857 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4859 REG_D[word2 & 7] = 0;
4860 REG_D[(word2 >> 12) & 7] = 0x80000000;
4863 FLAG_Z = ZFLAG_CLEAR;
4864 FLAG_V = VFLAG_CLEAR;
4865 FLAG_C = CFLAG_CLEAR;
4868 if(GET_MSB_32(dividend_hi))
4871 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4872 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4874 if(GET_MSB_32(divisor))
4877 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4882 /* if the upper long is greater than the divisor, we're overflowing. */
4883 if(dividend_hi >= divisor)
4889 for(i = 31; i >= 0; i--)
4892 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4893 if(remainder >= divisor)
4895 remainder -= divisor;
4899 for(i = 31; i >= 0; i--)
4902 overflow = GET_MSB_32(remainder);
4903 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4904 if(remainder >= divisor || overflow)
4906 remainder -= divisor;
4911 if(BIT_B(word2)) /* signed */
4913 if(quotient > 0x7fffffff)
4920 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4921 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4924 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4927 REG_D[word2 & 7] = remainder;
4928 REG_D[(word2 >> 12) & 7] = quotient;
4930 FLAG_N = NFLAG_32(quotient);
4932 FLAG_V = VFLAG_CLEAR;
4933 FLAG_C = CFLAG_CLEAR;
4937 /* long / long: long quotient, maybe long remainder */
4938 if(BIT_B(word2)) /* signed */
4940 /* Special case in divide */
4941 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4944 FLAG_Z = ZFLAG_CLEAR;
4945 FLAG_V = VFLAG_CLEAR;
4946 FLAG_C = CFLAG_CLEAR;
4947 REG_D[(word2 >> 12) & 7] = 0x80000000;
4948 REG_D[word2 & 7] = 0;
4951 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4952 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4956 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4957 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4960 FLAG_N = NFLAG_32(quotient);
4962 FLAG_V = VFLAG_CLEAR;
4963 FLAG_C = CFLAG_CLEAR;
4966 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4969 m68ki_exception_illegal();
4975 M68KMAKE_OP(eor, 8, ., d)
4977 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
4979 FLAG_N = NFLAG_8(res);
4981 FLAG_C = CFLAG_CLEAR;
4982 FLAG_V = VFLAG_CLEAR;
4986 M68KMAKE_OP(eor, 8, ., .)
4988 uint ea = M68KMAKE_GET_EA_AY_8;
4989 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
4991 m68ki_write_8(ea, res);
4993 FLAG_N = NFLAG_8(res);
4995 FLAG_C = CFLAG_CLEAR;
4996 FLAG_V = VFLAG_CLEAR;
5000 M68KMAKE_OP(eor, 16, ., d)
5002 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
5004 FLAG_N = NFLAG_16(res);
5006 FLAG_C = CFLAG_CLEAR;
5007 FLAG_V = VFLAG_CLEAR;
5011 M68KMAKE_OP(eor, 16, ., .)
5013 uint ea = M68KMAKE_GET_EA_AY_16;
5014 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
5016 m68ki_write_16(ea, res);
5018 FLAG_N = NFLAG_16(res);
5020 FLAG_C = CFLAG_CLEAR;
5021 FLAG_V = VFLAG_CLEAR;
5025 M68KMAKE_OP(eor, 32, ., d)
5027 uint res = DY ^= DX;
5029 FLAG_N = NFLAG_32(res);
5031 FLAG_C = CFLAG_CLEAR;
5032 FLAG_V = VFLAG_CLEAR;
5036 M68KMAKE_OP(eor, 32, ., .)
5038 uint ea = M68KMAKE_GET_EA_AY_32;
5039 uint res = DX ^ m68ki_read_32(ea);
5041 m68ki_write_32(ea, res);
5043 FLAG_N = NFLAG_32(res);
5045 FLAG_C = CFLAG_CLEAR;
5046 FLAG_V = VFLAG_CLEAR;
5050 M68KMAKE_OP(eori, 8, ., d)
5052 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
5054 FLAG_N = NFLAG_8(res);
5056 FLAG_C = CFLAG_CLEAR;
5057 FLAG_V = VFLAG_CLEAR;
5061 M68KMAKE_OP(eori, 8, ., .)
5063 uint src = OPER_I_8();
5064 uint ea = M68KMAKE_GET_EA_AY_8;
5065 uint res = src ^ m68ki_read_8(ea);
5067 m68ki_write_8(ea, res);
5069 FLAG_N = NFLAG_8(res);
5071 FLAG_C = CFLAG_CLEAR;
5072 FLAG_V = VFLAG_CLEAR;
5076 M68KMAKE_OP(eori, 16, ., d)
5078 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
5080 FLAG_N = NFLAG_16(res);
5082 FLAG_C = CFLAG_CLEAR;
5083 FLAG_V = VFLAG_CLEAR;
5087 M68KMAKE_OP(eori, 16, ., .)
5089 uint src = OPER_I_16();
5090 uint ea = M68KMAKE_GET_EA_AY_16;
5091 uint res = src ^ m68ki_read_16(ea);
5093 m68ki_write_16(ea, res);
5095 FLAG_N = NFLAG_16(res);
5097 FLAG_C = CFLAG_CLEAR;
5098 FLAG_V = VFLAG_CLEAR;
5102 M68KMAKE_OP(eori, 32, ., d)
5104 uint res = DY ^= OPER_I_32();
5106 FLAG_N = NFLAG_32(res);
5108 FLAG_C = CFLAG_CLEAR;
5109 FLAG_V = VFLAG_CLEAR;
5113 M68KMAKE_OP(eori, 32, ., .)
5115 uint src = OPER_I_32();
5116 uint ea = M68KMAKE_GET_EA_AY_32;
5117 uint res = src ^ m68ki_read_32(ea);
5119 m68ki_write_32(ea, res);
5121 FLAG_N = NFLAG_32(res);
5123 FLAG_C = CFLAG_CLEAR;
5124 FLAG_V = VFLAG_CLEAR;
5128 M68KMAKE_OP(eori, 16, toc, .)
5130 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8());
5134 M68KMAKE_OP(eori, 16, tos, .)
5138 uint src = OPER_I_16();
5139 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5140 m68ki_set_sr(m68ki_get_sr() ^ src);
5143 m68ki_exception_privilege_violation();
5147 M68KMAKE_OP(exg, 32, dd, .)
5157 M68KMAKE_OP(exg, 32, aa, .)
5167 M68KMAKE_OP(exg, 32, da, .)
5177 M68KMAKE_OP(ext, 16, ., .)
5181 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
5183 FLAG_N = NFLAG_16(*r_dst);
5184 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
5185 FLAG_V = VFLAG_CLEAR;
5186 FLAG_C = CFLAG_CLEAR;
5190 M68KMAKE_OP(ext, 32, ., .)
5194 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
5196 FLAG_N = NFLAG_32(*r_dst);
5198 FLAG_V = VFLAG_CLEAR;
5199 FLAG_C = CFLAG_CLEAR;
5203 M68KMAKE_OP(extb, 32, ., .)
5205 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5209 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
5211 FLAG_N = NFLAG_32(*r_dst);
5213 FLAG_V = VFLAG_CLEAR;
5214 FLAG_C = CFLAG_CLEAR;
5217 m68ki_exception_illegal();
5221 M68KMAKE_OP(illegal, 0, ., .)
5223 m68ki_exception_illegal();
5226 M68KMAKE_OP(jmp, 32, ., .)
5228 m68ki_jump(M68KMAKE_GET_EA_AY_32);
5229 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5230 if(REG_PC == REG_PPC)
5235 M68KMAKE_OP(jsr, 32, ., .)
5237 uint ea = M68KMAKE_GET_EA_AY_32;
5238 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5239 m68ki_push_32(REG_PC);
5244 M68KMAKE_OP(lea, 32, ., .)
5246 AX = M68KMAKE_GET_EA_AY_32;
5250 M68KMAKE_OP(link, 16, ., a7)
5253 m68ki_write_32(REG_A[7], REG_A[7]);
5254 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5258 M68KMAKE_OP(link, 16, ., .)
5262 m68ki_push_32(*r_dst);
5264 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5268 M68KMAKE_OP(link, 32, ., a7)
5270 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5273 m68ki_write_32(REG_A[7], REG_A[7]);
5274 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5277 m68ki_exception_illegal();
5281 M68KMAKE_OP(link, 32, ., .)
5283 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5287 m68ki_push_32(*r_dst);
5289 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5292 m68ki_exception_illegal();
5296 M68KMAKE_OP(lsr, 8, s, .)
5299 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5300 uint src = MASK_OUT_ABOVE_8(*r_dst);
5301 uint res = src >> shift;
5304 USE_CYCLES(shift<<CYC_SHIFT);
5306 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5308 FLAG_N = NFLAG_CLEAR;
5310 FLAG_X = FLAG_C = src << (9-shift);
5311 FLAG_V = VFLAG_CLEAR;
5315 M68KMAKE_OP(lsr, 16, s, .)
5318 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5319 uint src = MASK_OUT_ABOVE_16(*r_dst);
5320 uint res = src >> shift;
5323 USE_CYCLES(shift<<CYC_SHIFT);
5325 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5327 FLAG_N = NFLAG_CLEAR;
5329 FLAG_X = FLAG_C = src << (9-shift);
5330 FLAG_V = VFLAG_CLEAR;
5334 M68KMAKE_OP(lsr, 32, s, .)
5337 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5339 uint res = src >> shift;
5342 USE_CYCLES(shift<<CYC_SHIFT);
5346 FLAG_N = NFLAG_CLEAR;
5348 FLAG_X = FLAG_C = src << (9-shift);
5349 FLAG_V = VFLAG_CLEAR;
5353 M68KMAKE_OP(lsr, 8, r, .)
5356 uint shift = DX & 0x3f;
5357 uint src = MASK_OUT_ABOVE_8(*r_dst);
5358 uint res = src >> shift;
5362 USE_CYCLES(shift<<CYC_SHIFT);
5366 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5367 FLAG_X = FLAG_C = src << (9-shift);
5368 FLAG_N = NFLAG_CLEAR;
5370 FLAG_V = VFLAG_CLEAR;
5374 *r_dst &= 0xffffff00;
5375 FLAG_X = XFLAG_CLEAR;
5376 FLAG_C = CFLAG_CLEAR;
5377 FLAG_N = NFLAG_CLEAR;
5379 FLAG_V = VFLAG_CLEAR;
5383 FLAG_C = CFLAG_CLEAR;
5384 FLAG_N = NFLAG_8(src);
5386 FLAG_V = VFLAG_CLEAR;
5390 M68KMAKE_OP(lsr, 16, r, .)
5393 uint shift = DX & 0x3f;
5394 uint src = MASK_OUT_ABOVE_16(*r_dst);
5395 uint res = src >> shift;
5399 USE_CYCLES(shift<<CYC_SHIFT);
5403 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5404 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5405 FLAG_N = NFLAG_CLEAR;
5407 FLAG_V = VFLAG_CLEAR;
5411 *r_dst &= 0xffff0000;
5412 FLAG_X = XFLAG_CLEAR;
5413 FLAG_C = CFLAG_CLEAR;
5414 FLAG_N = NFLAG_CLEAR;
5416 FLAG_V = VFLAG_CLEAR;
5420 FLAG_C = CFLAG_CLEAR;
5421 FLAG_N = NFLAG_16(src);
5423 FLAG_V = VFLAG_CLEAR;
5427 M68KMAKE_OP(lsr, 32, r, .)
5430 uint shift = DX & 0x3f;
5432 uint res = src >> shift;
5436 USE_CYCLES(shift<<CYC_SHIFT);
5441 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5442 FLAG_N = NFLAG_CLEAR;
5444 FLAG_V = VFLAG_CLEAR;
5449 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
5450 FLAG_N = NFLAG_CLEAR;
5452 FLAG_V = VFLAG_CLEAR;
5456 FLAG_C = CFLAG_CLEAR;
5457 FLAG_N = NFLAG_32(src);
5459 FLAG_V = VFLAG_CLEAR;
5463 M68KMAKE_OP(lsr, 16, ., .)
5465 uint ea = M68KMAKE_GET_EA_AY_16;
5466 uint src = m68ki_read_16(ea);
5467 uint res = src >> 1;
5469 m68ki_write_16(ea, res);
5471 FLAG_N = NFLAG_CLEAR;
5473 FLAG_C = FLAG_X = src << 8;
5474 FLAG_V = VFLAG_CLEAR;
5478 M68KMAKE_OP(lsl, 8, s, .)
5481 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5482 uint src = MASK_OUT_ABOVE_8(*r_dst);
5483 uint res = MASK_OUT_ABOVE_8(src << shift);
5486 USE_CYCLES(shift<<CYC_SHIFT);
5488 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5490 FLAG_N = NFLAG_8(res);
5492 FLAG_X = FLAG_C = src << shift;
5493 FLAG_V = VFLAG_CLEAR;
5497 M68KMAKE_OP(lsl, 16, s, .)
5500 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5501 uint src = MASK_OUT_ABOVE_16(*r_dst);
5502 uint res = MASK_OUT_ABOVE_16(src << shift);
5505 USE_CYCLES(shift<<CYC_SHIFT);
5507 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5509 FLAG_N = NFLAG_16(res);
5511 FLAG_X = FLAG_C = src >> (8-shift);
5512 FLAG_V = VFLAG_CLEAR;
5516 M68KMAKE_OP(lsl, 32, s, .)
5519 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5521 uint res = MASK_OUT_ABOVE_32(src << shift);
5524 USE_CYCLES(shift<<CYC_SHIFT);
5528 FLAG_N = NFLAG_32(res);
5530 FLAG_X = FLAG_C = src >> (24-shift);
5531 FLAG_V = VFLAG_CLEAR;
5535 M68KMAKE_OP(lsl, 8, r, .)
5538 uint shift = DX & 0x3f;
5539 uint src = MASK_OUT_ABOVE_8(*r_dst);
5540 uint res = MASK_OUT_ABOVE_8(src << shift);
5544 USE_CYCLES(shift<<CYC_SHIFT);
5548 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5549 FLAG_X = FLAG_C = src << shift;
5550 FLAG_N = NFLAG_8(res);
5552 FLAG_V = VFLAG_CLEAR;
5556 *r_dst &= 0xffffff00;
5557 FLAG_X = XFLAG_CLEAR;
5558 FLAG_C = CFLAG_CLEAR;
5559 FLAG_N = NFLAG_CLEAR;
5561 FLAG_V = VFLAG_CLEAR;
5565 FLAG_C = CFLAG_CLEAR;
5566 FLAG_N = NFLAG_8(src);
5568 FLAG_V = VFLAG_CLEAR;
5572 M68KMAKE_OP(lsl, 16, r, .)
5575 uint shift = DX & 0x3f;
5576 uint src = MASK_OUT_ABOVE_16(*r_dst);
5577 uint res = MASK_OUT_ABOVE_16(src << shift);
5581 USE_CYCLES(shift<<CYC_SHIFT);
5585 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5586 FLAG_X = FLAG_C = (src << shift) >> 8;
5587 FLAG_N = NFLAG_16(res);
5589 FLAG_V = VFLAG_CLEAR;
5593 *r_dst &= 0xffff0000;
5594 FLAG_X = XFLAG_CLEAR;
5595 FLAG_C = CFLAG_CLEAR;
5596 FLAG_N = NFLAG_CLEAR;
5598 FLAG_V = VFLAG_CLEAR;
5602 FLAG_C = CFLAG_CLEAR;
5603 FLAG_N = NFLAG_16(src);
5605 FLAG_V = VFLAG_CLEAR;
5609 M68KMAKE_OP(lsl, 32, r, .)
5612 uint shift = DX & 0x3f;
5614 uint res = MASK_OUT_ABOVE_32(src << shift);
5618 USE_CYCLES(shift<<CYC_SHIFT);
5623 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
5624 FLAG_N = NFLAG_32(res);
5626 FLAG_V = VFLAG_CLEAR;
5631 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
5632 FLAG_N = NFLAG_CLEAR;
5634 FLAG_V = VFLAG_CLEAR;
5638 FLAG_C = CFLAG_CLEAR;
5639 FLAG_N = NFLAG_32(src);
5641 FLAG_V = VFLAG_CLEAR;
5645 M68KMAKE_OP(lsl, 16, ., .)
5647 uint ea = M68KMAKE_GET_EA_AY_16;
5648 uint src = m68ki_read_16(ea);
5649 uint res = MASK_OUT_ABOVE_16(src << 1);
5651 m68ki_write_16(ea, res);
5653 FLAG_N = NFLAG_16(res);
5655 FLAG_X = FLAG_C = src >> 7;
5656 FLAG_V = VFLAG_CLEAR;
5660 M68KMAKE_OP(move, 8, d, d)
5662 uint res = MASK_OUT_ABOVE_8(DY);
5665 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5667 FLAG_N = NFLAG_8(res);
5669 FLAG_V = VFLAG_CLEAR;
5670 FLAG_C = CFLAG_CLEAR;
5674 M68KMAKE_OP(move, 8, d, .)
5676 uint res = M68KMAKE_GET_OPER_AY_8;
5679 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5681 FLAG_N = NFLAG_8(res);
5683 FLAG_V = VFLAG_CLEAR;
5684 FLAG_C = CFLAG_CLEAR;
5688 M68KMAKE_OP(move, 8, ai, d)
5690 uint res = MASK_OUT_ABOVE_8(DY);
5691 uint ea = EA_AX_AI_8();
5693 m68ki_write_8(ea, res);
5695 FLAG_N = NFLAG_8(res);
5697 FLAG_V = VFLAG_CLEAR;
5698 FLAG_C = CFLAG_CLEAR;
5702 M68KMAKE_OP(move, 8, ai, .)
5704 uint res = M68KMAKE_GET_OPER_AY_8;
5705 uint ea = EA_AX_AI_8();
5707 m68ki_write_8(ea, res);
5709 FLAG_N = NFLAG_8(res);
5711 FLAG_V = VFLAG_CLEAR;
5712 FLAG_C = CFLAG_CLEAR;
5716 M68KMAKE_OP(move, 8, pi7, d)
5718 uint res = MASK_OUT_ABOVE_8(DY);
5719 uint ea = EA_A7_PI_8();
5721 m68ki_write_8(ea, res);
5723 FLAG_N = NFLAG_8(res);
5725 FLAG_V = VFLAG_CLEAR;
5726 FLAG_C = CFLAG_CLEAR;
5730 M68KMAKE_OP(move, 8, pi, d)
5732 uint res = MASK_OUT_ABOVE_8(DY);
5733 uint ea = EA_AX_PI_8();
5735 m68ki_write_8(ea, res);
5737 FLAG_N = NFLAG_8(res);
5739 FLAG_V = VFLAG_CLEAR;
5740 FLAG_C = CFLAG_CLEAR;
5744 M68KMAKE_OP(move, 8, pi7, .)
5746 uint res = M68KMAKE_GET_OPER_AY_8;
5747 uint ea = EA_A7_PI_8();
5749 m68ki_write_8(ea, res);
5751 FLAG_N = NFLAG_8(res);
5753 FLAG_V = VFLAG_CLEAR;
5754 FLAG_C = CFLAG_CLEAR;
5758 M68KMAKE_OP(move, 8, pi, .)
5760 uint res = M68KMAKE_GET_OPER_AY_8;
5761 uint ea = EA_AX_PI_8();
5763 m68ki_write_8(ea, res);
5765 FLAG_N = NFLAG_8(res);
5767 FLAG_V = VFLAG_CLEAR;
5768 FLAG_C = CFLAG_CLEAR;
5772 M68KMAKE_OP(move, 8, pd7, d)
5774 uint res = MASK_OUT_ABOVE_8(DY);
5775 uint ea = EA_A7_PD_8();
5777 m68ki_write_8(ea, res);
5779 FLAG_N = NFLAG_8(res);
5781 FLAG_V = VFLAG_CLEAR;
5782 FLAG_C = CFLAG_CLEAR;
5786 M68KMAKE_OP(move, 8, pd, d)
5788 uint res = MASK_OUT_ABOVE_8(DY);
5789 uint ea = EA_AX_PD_8();
5791 m68ki_write_8(ea, res);
5793 FLAG_N = NFLAG_8(res);
5795 FLAG_V = VFLAG_CLEAR;
5796 FLAG_C = CFLAG_CLEAR;
5800 M68KMAKE_OP(move, 8, pd7, .)
5802 uint res = M68KMAKE_GET_OPER_AY_8;
5803 uint ea = EA_A7_PD_8();
5805 m68ki_write_8(ea, res);
5807 FLAG_N = NFLAG_8(res);
5809 FLAG_V = VFLAG_CLEAR;
5810 FLAG_C = CFLAG_CLEAR;
5814 M68KMAKE_OP(move, 8, pd, .)
5816 uint res = M68KMAKE_GET_OPER_AY_8;
5817 uint ea = EA_AX_PD_8();
5819 m68ki_write_8(ea, res);
5821 FLAG_N = NFLAG_8(res);
5823 FLAG_V = VFLAG_CLEAR;
5824 FLAG_C = CFLAG_CLEAR;
5828 M68KMAKE_OP(move, 8, di, d)
5830 uint res = MASK_OUT_ABOVE_8(DY);
5831 uint ea = EA_AX_DI_8();
5833 m68ki_write_8(ea, res);
5835 FLAG_N = NFLAG_8(res);
5837 FLAG_V = VFLAG_CLEAR;
5838 FLAG_C = CFLAG_CLEAR;
5842 M68KMAKE_OP(move, 8, di, .)
5844 uint res = M68KMAKE_GET_OPER_AY_8;
5845 uint ea = EA_AX_DI_8();
5847 m68ki_write_8(ea, res);
5849 FLAG_N = NFLAG_8(res);
5851 FLAG_V = VFLAG_CLEAR;
5852 FLAG_C = CFLAG_CLEAR;
5856 M68KMAKE_OP(move, 8, ix, d)
5858 uint res = MASK_OUT_ABOVE_8(DY);
5859 uint ea = EA_AX_IX_8();
5861 m68ki_write_8(ea, res);
5863 FLAG_N = NFLAG_8(res);
5865 FLAG_V = VFLAG_CLEAR;
5866 FLAG_C = CFLAG_CLEAR;
5870 M68KMAKE_OP(move, 8, ix, .)
5872 uint res = M68KMAKE_GET_OPER_AY_8;
5873 uint ea = EA_AX_IX_8();
5875 m68ki_write_8(ea, res);
5877 FLAG_N = NFLAG_8(res);
5879 FLAG_V = VFLAG_CLEAR;
5880 FLAG_C = CFLAG_CLEAR;
5884 M68KMAKE_OP(move, 8, aw, d)
5886 uint res = MASK_OUT_ABOVE_8(DY);
5887 uint ea = EA_AW_8();
5889 m68ki_write_8(ea, res);
5891 FLAG_N = NFLAG_8(res);
5893 FLAG_V = VFLAG_CLEAR;
5894 FLAG_C = CFLAG_CLEAR;
5898 M68KMAKE_OP(move, 8, aw, .)
5900 uint res = M68KMAKE_GET_OPER_AY_8;
5901 uint ea = EA_AW_8();
5903 m68ki_write_8(ea, res);
5905 FLAG_N = NFLAG_8(res);
5907 FLAG_V = VFLAG_CLEAR;
5908 FLAG_C = CFLAG_CLEAR;
5912 M68KMAKE_OP(move, 8, al, d)
5914 uint res = MASK_OUT_ABOVE_8(DY);
5915 uint ea = EA_AL_8();
5917 m68ki_write_8(ea, res);
5919 FLAG_N = NFLAG_8(res);
5921 FLAG_V = VFLAG_CLEAR;
5922 FLAG_C = CFLAG_CLEAR;
5926 M68KMAKE_OP(move, 8, al, .)
5928 uint res = M68KMAKE_GET_OPER_AY_8;
5929 uint ea = EA_AL_8();
5931 m68ki_write_8(ea, res);
5933 FLAG_N = NFLAG_8(res);
5935 FLAG_V = VFLAG_CLEAR;
5936 FLAG_C = CFLAG_CLEAR;
5940 M68KMAKE_OP(move, 16, d, d)
5942 uint res = MASK_OUT_ABOVE_16(DY);
5945 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5947 FLAG_N = NFLAG_16(res);
5949 FLAG_V = VFLAG_CLEAR;
5950 FLAG_C = CFLAG_CLEAR;
5954 M68KMAKE_OP(move, 16, d, a)
5956 uint res = MASK_OUT_ABOVE_16(AY);
5959 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5961 FLAG_N = NFLAG_16(res);
5963 FLAG_V = VFLAG_CLEAR;
5964 FLAG_C = CFLAG_CLEAR;
5968 M68KMAKE_OP(move, 16, d, .)
5970 uint res = M68KMAKE_GET_OPER_AY_16;
5973 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5975 FLAG_N = NFLAG_16(res);
5977 FLAG_V = VFLAG_CLEAR;
5978 FLAG_C = CFLAG_CLEAR;
5982 M68KMAKE_OP(move, 16, ai, d)
5984 uint res = MASK_OUT_ABOVE_16(DY);
5985 uint ea = EA_AX_AI_16();
5987 m68ki_write_16(ea, res);
5989 FLAG_N = NFLAG_16(res);
5991 FLAG_V = VFLAG_CLEAR;
5992 FLAG_C = CFLAG_CLEAR;
5996 M68KMAKE_OP(move, 16, ai, a)
5998 uint res = MASK_OUT_ABOVE_16(AY);
5999 uint ea = EA_AX_AI_16();
6001 m68ki_write_16(ea, res);
6003 FLAG_N = NFLAG_16(res);
6005 FLAG_V = VFLAG_CLEAR;
6006 FLAG_C = CFLAG_CLEAR;
6010 M68KMAKE_OP(move, 16, ai, .)
6012 uint res = M68KMAKE_GET_OPER_AY_16;
6013 uint ea = EA_AX_AI_16();
6015 m68ki_write_16(ea, res);
6017 FLAG_N = NFLAG_16(res);
6019 FLAG_V = VFLAG_CLEAR;
6020 FLAG_C = CFLAG_CLEAR;
6024 M68KMAKE_OP(move, 16, pi, d)
6026 uint res = MASK_OUT_ABOVE_16(DY);
6027 uint ea = EA_AX_PI_16();
6029 m68ki_write_16(ea, res);
6031 FLAG_N = NFLAG_16(res);
6033 FLAG_V = VFLAG_CLEAR;
6034 FLAG_C = CFLAG_CLEAR;
6038 M68KMAKE_OP(move, 16, pi, a)
6040 uint res = MASK_OUT_ABOVE_16(AY);
6041 uint ea = EA_AX_PI_16();
6043 m68ki_write_16(ea, res);
6045 FLAG_N = NFLAG_16(res);
6047 FLAG_V = VFLAG_CLEAR;
6048 FLAG_C = CFLAG_CLEAR;
6052 M68KMAKE_OP(move, 16, pi, .)
6054 uint res = M68KMAKE_GET_OPER_AY_16;
6055 uint ea = EA_AX_PI_16();
6057 m68ki_write_16(ea, res);
6059 FLAG_N = NFLAG_16(res);
6061 FLAG_V = VFLAG_CLEAR;
6062 FLAG_C = CFLAG_CLEAR;
6066 M68KMAKE_OP(move, 16, pd, d)
6068 uint res = MASK_OUT_ABOVE_16(DY);
6069 uint ea = EA_AX_PD_16();
6071 m68ki_write_16(ea, res);
6073 FLAG_N = NFLAG_16(res);
6075 FLAG_V = VFLAG_CLEAR;
6076 FLAG_C = CFLAG_CLEAR;
6080 M68KMAKE_OP(move, 16, pd, a)
6082 uint res = MASK_OUT_ABOVE_16(AY);
6083 uint ea = EA_AX_PD_16();
6085 m68ki_write_16(ea, res);
6087 FLAG_N = NFLAG_16(res);
6089 FLAG_V = VFLAG_CLEAR;
6090 FLAG_C = CFLAG_CLEAR;
6094 M68KMAKE_OP(move, 16, pd, .)
6096 uint res = M68KMAKE_GET_OPER_AY_16;
6097 uint ea = EA_AX_PD_16();
6099 m68ki_write_16(ea, res);
6101 FLAG_N = NFLAG_16(res);
6103 FLAG_V = VFLAG_CLEAR;
6104 FLAG_C = CFLAG_CLEAR;
6108 M68KMAKE_OP(move, 16, di, d)
6110 uint res = MASK_OUT_ABOVE_16(DY);
6111 uint ea = EA_AX_DI_16();
6113 m68ki_write_16(ea, res);
6115 FLAG_N = NFLAG_16(res);
6117 FLAG_V = VFLAG_CLEAR;
6118 FLAG_C = CFLAG_CLEAR;
6122 M68KMAKE_OP(move, 16, di, a)
6124 uint res = MASK_OUT_ABOVE_16(AY);
6125 uint ea = EA_AX_DI_16();
6127 m68ki_write_16(ea, res);
6129 FLAG_N = NFLAG_16(res);
6131 FLAG_V = VFLAG_CLEAR;
6132 FLAG_C = CFLAG_CLEAR;
6136 M68KMAKE_OP(move, 16, di, .)
6138 uint res = M68KMAKE_GET_OPER_AY_16;
6139 uint ea = EA_AX_DI_16();
6141 m68ki_write_16(ea, res);
6143 FLAG_N = NFLAG_16(res);
6145 FLAG_V = VFLAG_CLEAR;
6146 FLAG_C = CFLAG_CLEAR;
6150 M68KMAKE_OP(move, 16, ix, d)
6152 uint res = MASK_OUT_ABOVE_16(DY);
6153 uint ea = EA_AX_IX_16();
6155 m68ki_write_16(ea, res);
6157 FLAG_N = NFLAG_16(res);
6159 FLAG_V = VFLAG_CLEAR;
6160 FLAG_C = CFLAG_CLEAR;
6164 M68KMAKE_OP(move, 16, ix, a)
6166 uint res = MASK_OUT_ABOVE_16(AY);
6167 uint ea = EA_AX_IX_16();
6169 m68ki_write_16(ea, res);
6171 FLAG_N = NFLAG_16(res);
6173 FLAG_V = VFLAG_CLEAR;
6174 FLAG_C = CFLAG_CLEAR;
6178 M68KMAKE_OP(move, 16, ix, .)
6180 uint res = M68KMAKE_GET_OPER_AY_16;
6181 uint ea = EA_AX_IX_16();
6183 m68ki_write_16(ea, res);
6185 FLAG_N = NFLAG_16(res);
6187 FLAG_V = VFLAG_CLEAR;
6188 FLAG_C = CFLAG_CLEAR;
6192 M68KMAKE_OP(move, 16, aw, d)
6194 uint res = MASK_OUT_ABOVE_16(DY);
6195 uint ea = EA_AW_16();
6197 m68ki_write_16(ea, res);
6199 FLAG_N = NFLAG_16(res);
6201 FLAG_V = VFLAG_CLEAR;
6202 FLAG_C = CFLAG_CLEAR;
6206 M68KMAKE_OP(move, 16, aw, a)
6208 uint res = MASK_OUT_ABOVE_16(AY);
6209 uint ea = EA_AW_16();
6211 m68ki_write_16(ea, res);
6213 FLAG_N = NFLAG_16(res);
6215 FLAG_V = VFLAG_CLEAR;
6216 FLAG_C = CFLAG_CLEAR;
6220 M68KMAKE_OP(move, 16, aw, .)
6222 uint res = M68KMAKE_GET_OPER_AY_16;
6223 uint ea = EA_AW_16();
6225 m68ki_write_16(ea, res);
6227 FLAG_N = NFLAG_16(res);
6229 FLAG_V = VFLAG_CLEAR;
6230 FLAG_C = CFLAG_CLEAR;
6234 M68KMAKE_OP(move, 16, al, d)
6236 uint res = MASK_OUT_ABOVE_16(DY);
6237 uint ea = EA_AL_16();
6239 m68ki_write_16(ea, res);
6241 FLAG_N = NFLAG_16(res);
6243 FLAG_V = VFLAG_CLEAR;
6244 FLAG_C = CFLAG_CLEAR;
6248 M68KMAKE_OP(move, 16, al, a)
6250 uint res = MASK_OUT_ABOVE_16(AY);
6251 uint ea = EA_AL_16();
6253 m68ki_write_16(ea, res);
6255 FLAG_N = NFLAG_16(res);
6257 FLAG_V = VFLAG_CLEAR;
6258 FLAG_C = CFLAG_CLEAR;
6262 M68KMAKE_OP(move, 16, al, .)
6264 uint res = M68KMAKE_GET_OPER_AY_16;
6265 uint ea = EA_AL_16();
6267 m68ki_write_16(ea, res);
6269 FLAG_N = NFLAG_16(res);
6271 FLAG_V = VFLAG_CLEAR;
6272 FLAG_C = CFLAG_CLEAR;
6276 M68KMAKE_OP(move, 32, d, d)
6283 FLAG_N = NFLAG_32(res);
6285 FLAG_V = VFLAG_CLEAR;
6286 FLAG_C = CFLAG_CLEAR;
6290 M68KMAKE_OP(move, 32, d, a)
6297 FLAG_N = NFLAG_32(res);
6299 FLAG_V = VFLAG_CLEAR;
6300 FLAG_C = CFLAG_CLEAR;
6304 M68KMAKE_OP(move, 32, d, .)
6306 uint res = M68KMAKE_GET_OPER_AY_32;
6311 FLAG_N = NFLAG_32(res);
6313 FLAG_V = VFLAG_CLEAR;
6314 FLAG_C = CFLAG_CLEAR;
6318 M68KMAKE_OP(move, 32, ai, d)
6321 uint ea = EA_AX_AI_32();
6323 m68ki_write_32(ea, res);
6325 FLAG_N = NFLAG_32(res);
6327 FLAG_V = VFLAG_CLEAR;
6328 FLAG_C = CFLAG_CLEAR;
6332 M68KMAKE_OP(move, 32, ai, a)
6335 uint ea = EA_AX_AI_32();
6337 m68ki_write_32(ea, res);
6339 FLAG_N = NFLAG_32(res);
6341 FLAG_V = VFLAG_CLEAR;
6342 FLAG_C = CFLAG_CLEAR;
6346 M68KMAKE_OP(move, 32, ai, .)
6348 uint res = M68KMAKE_GET_OPER_AY_32;
6349 uint ea = EA_AX_AI_32();
6351 m68ki_write_32(ea, res);
6353 FLAG_N = NFLAG_32(res);
6355 FLAG_V = VFLAG_CLEAR;
6356 FLAG_C = CFLAG_CLEAR;
6360 M68KMAKE_OP(move, 32, pi, d)
6363 uint ea = EA_AX_PI_32();
6365 m68ki_write_32(ea, res);
6367 FLAG_N = NFLAG_32(res);
6369 FLAG_V = VFLAG_CLEAR;
6370 FLAG_C = CFLAG_CLEAR;
6374 M68KMAKE_OP(move, 32, pi, a)
6377 uint ea = EA_AX_PI_32();
6379 m68ki_write_32(ea, res);
6381 FLAG_N = NFLAG_32(res);
6383 FLAG_V = VFLAG_CLEAR;
6384 FLAG_C = CFLAG_CLEAR;
6388 M68KMAKE_OP(move, 32, pi, .)
6390 uint res = M68KMAKE_GET_OPER_AY_32;
6391 uint ea = EA_AX_PI_32();
6393 m68ki_write_32(ea, res);
6395 FLAG_N = NFLAG_32(res);
6397 FLAG_V = VFLAG_CLEAR;
6398 FLAG_C = CFLAG_CLEAR;
6402 M68KMAKE_OP(move, 32, pd, d)
6405 uint ea = EA_AX_PD_32();
6407 m68ki_write_16(ea+2, res & 0xFFFF );
6408 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6410 FLAG_N = NFLAG_32(res);
6412 FLAG_V = VFLAG_CLEAR;
6413 FLAG_C = CFLAG_CLEAR;
6417 M68KMAKE_OP(move, 32, pd, a)
6420 uint ea = EA_AX_PD_32();
6422 m68ki_write_16(ea+2, res & 0xFFFF );
6423 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6425 FLAG_N = NFLAG_32(res);
6427 FLAG_V = VFLAG_CLEAR;
6428 FLAG_C = CFLAG_CLEAR;
6432 M68KMAKE_OP(move, 32, pd, .)
6434 uint res = M68KMAKE_GET_OPER_AY_32;
6435 uint ea = EA_AX_PD_32();
6437 m68ki_write_16(ea+2, res & 0xFFFF );
6438 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6440 FLAG_N = NFLAG_32(res);
6442 FLAG_V = VFLAG_CLEAR;
6443 FLAG_C = CFLAG_CLEAR;
6447 M68KMAKE_OP(move, 32, di, d)
6450 uint ea = EA_AX_DI_32();
6452 m68ki_write_32(ea, res);
6454 FLAG_N = NFLAG_32(res);
6456 FLAG_V = VFLAG_CLEAR;
6457 FLAG_C = CFLAG_CLEAR;
6461 M68KMAKE_OP(move, 32, di, a)
6464 uint ea = EA_AX_DI_32();
6466 m68ki_write_32(ea, res);
6468 FLAG_N = NFLAG_32(res);
6470 FLAG_V = VFLAG_CLEAR;
6471 FLAG_C = CFLAG_CLEAR;
6475 M68KMAKE_OP(move, 32, di, .)
6477 uint res = M68KMAKE_GET_OPER_AY_32;
6478 uint ea = EA_AX_DI_32();
6480 m68ki_write_32(ea, res);
6482 FLAG_N = NFLAG_32(res);
6484 FLAG_V = VFLAG_CLEAR;
6485 FLAG_C = CFLAG_CLEAR;
6489 M68KMAKE_OP(move, 32, ix, d)
6492 uint ea = EA_AX_IX_32();
6494 m68ki_write_32(ea, res);
6496 FLAG_N = NFLAG_32(res);
6498 FLAG_V = VFLAG_CLEAR;
6499 FLAG_C = CFLAG_CLEAR;
6503 M68KMAKE_OP(move, 32, ix, a)
6506 uint ea = EA_AX_IX_32();
6508 m68ki_write_32(ea, res);
6510 FLAG_N = NFLAG_32(res);
6512 FLAG_V = VFLAG_CLEAR;
6513 FLAG_C = CFLAG_CLEAR;
6517 M68KMAKE_OP(move, 32, ix, .)
6519 uint res = M68KMAKE_GET_OPER_AY_32;
6520 uint ea = EA_AX_IX_32();
6522 m68ki_write_32(ea, res);
6524 FLAG_N = NFLAG_32(res);
6526 FLAG_V = VFLAG_CLEAR;
6527 FLAG_C = CFLAG_CLEAR;
6531 M68KMAKE_OP(move, 32, aw, d)
6534 uint ea = EA_AW_32();
6536 m68ki_write_32(ea, res);
6538 FLAG_N = NFLAG_32(res);
6540 FLAG_V = VFLAG_CLEAR;
6541 FLAG_C = CFLAG_CLEAR;
6545 M68KMAKE_OP(move, 32, aw, a)
6548 uint ea = EA_AW_32();
6550 m68ki_write_32(ea, res);
6552 FLAG_N = NFLAG_32(res);
6554 FLAG_V = VFLAG_CLEAR;
6555 FLAG_C = CFLAG_CLEAR;
6559 M68KMAKE_OP(move, 32, aw, .)
6561 uint res = M68KMAKE_GET_OPER_AY_32;
6562 uint ea = EA_AW_32();
6564 m68ki_write_32(ea, res);
6566 FLAG_N = NFLAG_32(res);
6568 FLAG_V = VFLAG_CLEAR;
6569 FLAG_C = CFLAG_CLEAR;
6573 M68KMAKE_OP(move, 32, al, d)
6576 uint ea = EA_AL_32();
6578 m68ki_write_32(ea, res);
6580 FLAG_N = NFLAG_32(res);
6582 FLAG_V = VFLAG_CLEAR;
6583 FLAG_C = CFLAG_CLEAR;
6587 M68KMAKE_OP(move, 32, al, a)
6590 uint ea = EA_AL_32();
6592 m68ki_write_32(ea, res);
6594 FLAG_N = NFLAG_32(res);
6596 FLAG_V = VFLAG_CLEAR;
6597 FLAG_C = CFLAG_CLEAR;
6601 M68KMAKE_OP(move, 32, al, .)
6603 uint res = M68KMAKE_GET_OPER_AY_32;
6604 uint ea = EA_AL_32();
6606 m68ki_write_32(ea, res);
6608 FLAG_N = NFLAG_32(res);
6610 FLAG_V = VFLAG_CLEAR;
6611 FLAG_C = CFLAG_CLEAR;
6615 M68KMAKE_OP(movea, 16, ., d)
6617 AX = MAKE_INT_16(DY);
6621 M68KMAKE_OP(movea, 16, ., a)
6623 AX = MAKE_INT_16(AY);
6627 M68KMAKE_OP(movea, 16, ., .)
6629 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
6633 M68KMAKE_OP(movea, 32, ., d)
6639 M68KMAKE_OP(movea, 32, ., a)
6645 M68KMAKE_OP(movea, 32, ., .)
6647 AX = M68KMAKE_GET_OPER_AY_32;
6651 M68KMAKE_OP(move, 16, frc, d)
6653 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6655 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
6658 m68ki_exception_illegal();
6662 M68KMAKE_OP(move, 16, frc, .)
6664 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6666 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
6669 m68ki_exception_illegal();
6673 M68KMAKE_OP(move, 16, toc, d)
6679 M68KMAKE_OP(move, 16, toc, .)
6681 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
6685 M68KMAKE_OP(move, 16, frs, d)
6687 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6689 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
6692 m68ki_exception_privilege_violation();
6696 M68KMAKE_OP(move, 16, frs, .)
6698 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6700 uint ea = M68KMAKE_GET_EA_AY_16;
6701 m68ki_write_16(ea, m68ki_get_sr());
6704 m68ki_exception_privilege_violation();
6708 M68KMAKE_OP(move, 16, tos, d)
6715 m68ki_exception_privilege_violation();
6719 M68KMAKE_OP(move, 16, tos, .)
6723 uint new_sr = M68KMAKE_GET_OPER_AY_16;
6724 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6725 m68ki_set_sr(new_sr);
6728 m68ki_exception_privilege_violation();
6732 M68KMAKE_OP(move, 32, fru, .)
6739 m68ki_exception_privilege_violation();
6743 M68KMAKE_OP(move, 32, tou, .)
6747 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6751 m68ki_exception_privilege_violation();
6755 M68KMAKE_OP(movec, 32, cr, .)
6757 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6761 uint word2 = OPER_I_16();
6763 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6764 switch (word2 & 0xfff)
6766 case 0x000: /* SFC */
6767 REG_DA[(word2 >> 12) & 15] = REG_SFC;
6769 case 0x001: /* DFC */
6770 REG_DA[(word2 >> 12) & 15] = REG_DFC;
6772 case 0x002: /* CACR */
6773 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6775 REG_DA[(word2 >> 12) & 15] = REG_CACR;
6779 case 0x800: /* USP */
6780 REG_DA[(word2 >> 12) & 15] = REG_USP;
6782 case 0x801: /* VBR */
6783 REG_DA[(word2 >> 12) & 15] = REG_VBR;
6785 case 0x802: /* CAAR */
6786 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6788 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
6791 m68ki_exception_illegal();
6793 case 0x803: /* MSP */
6794 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6796 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
6799 m68ki_exception_illegal();
6801 case 0x804: /* ISP */
6802 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6804 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
6807 m68ki_exception_illegal();
6809 case 0x003: /* TC */
6810 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6815 m68ki_exception_illegal();
6817 case 0x004: /* ITT0 */
6818 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6823 m68ki_exception_illegal();
6825 case 0x005: /* ITT1 */
6826 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6831 m68ki_exception_illegal();
6833 case 0x006: /* DTT0 */
6834 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6839 m68ki_exception_illegal();
6841 case 0x007: /* DTT1 */
6842 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6847 m68ki_exception_illegal();
6849 case 0x805: /* MMUSR */
6850 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6855 m68ki_exception_illegal();
6857 case 0x806: /* URP */
6858 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6863 m68ki_exception_illegal();
6865 case 0x807: /* SRP */
6866 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6871 m68ki_exception_illegal();
6874 m68ki_exception_illegal();
6878 m68ki_exception_privilege_violation();
6881 m68ki_exception_illegal();
6885 M68KMAKE_OP(movec, 32, rc, .)
6887 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6891 uint word2 = OPER_I_16();
6893 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6894 switch (word2 & 0xfff)
6896 case 0x000: /* SFC */
6897 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
6899 case 0x001: /* DFC */
6900 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
6902 case 0x002: /* CACR */
6903 /* Only EC020 and later have CACR */
6904 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6906 /* 68030 can write all bits except 5-7, 040 can write all */
6907 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6909 REG_CACR = REG_DA[(word2 >> 12) & 15];
6911 else if (CPU_TYPE_IS_030_PLUS(CPU_TYPE))
6913 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0xff1f;
6917 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
6921 m68ki_exception_illegal();
6923 case 0x800: /* USP */
6924 REG_USP = REG_DA[(word2 >> 12) & 15];
6926 case 0x801: /* VBR */
6927 REG_VBR = REG_DA[(word2 >> 12) & 15];
6929 case 0x802: /* CAAR */
6930 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6932 REG_CAAR = REG_DA[(word2 >> 12) & 15];
6935 m68ki_exception_illegal();
6937 case 0x803: /* MSP */
6938 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6940 /* we are in supervisor mode so just check for M flag */
6943 REG_MSP = REG_DA[(word2 >> 12) & 15];
6946 REG_SP = REG_DA[(word2 >> 12) & 15];
6949 m68ki_exception_illegal();
6951 case 0x804: /* ISP */
6952 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6956 REG_SP = REG_DA[(word2 >> 12) & 15];
6959 REG_ISP = REG_DA[(word2 >> 12) & 15];
6962 m68ki_exception_illegal();
6964 case 0x003: /* TC */
6965 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6970 m68ki_exception_illegal();
6972 case 0x004: /* ITT0 */
6973 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6978 m68ki_exception_illegal();
6980 case 0x005: /* ITT1 */
6981 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6986 m68ki_exception_illegal();
6988 case 0x006: /* DTT0 */
6989 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6994 m68ki_exception_illegal();
6996 case 0x007: /* DTT1 */
6997 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7002 m68ki_exception_illegal();
7004 case 0x805: /* MMUSR */
7005 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7010 m68ki_exception_illegal();
7012 case 0x806: /* URP */
7013 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7018 m68ki_exception_illegal();
7020 case 0x807: /* SRP */
7021 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7026 m68ki_exception_illegal();
7029 m68ki_exception_illegal();
7033 m68ki_exception_privilege_violation();
7036 m68ki_exception_illegal();
7040 M68KMAKE_OP(movem, 16, re, pd)
7043 uint register_list = OPER_I_16();
7048 if(register_list & (1 << i))
7051 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
7056 USE_CYCLES(count<<CYC_MOVEM_W);
7060 M68KMAKE_OP(movem, 16, re, .)
7063 uint register_list = OPER_I_16();
7064 uint ea = M68KMAKE_GET_EA_AY_16;
7068 if(register_list & (1 << i))
7070 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
7075 USE_CYCLES(count<<CYC_MOVEM_W);
7079 M68KMAKE_OP(movem, 32, re, pd)
7082 uint register_list = OPER_I_16();
7087 if(register_list & (1 << i))
7090 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
7091 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
7096 USE_CYCLES(count<<CYC_MOVEM_L);
7100 M68KMAKE_OP(movem, 32, re, .)
7103 uint register_list = OPER_I_16();
7104 uint ea = M68KMAKE_GET_EA_AY_32;
7108 if(register_list & (1 << i))
7110 m68ki_write_32(ea, REG_DA[i]);
7115 USE_CYCLES(count<<CYC_MOVEM_L);
7119 M68KMAKE_OP(movem, 16, er, pi)
7122 uint register_list = OPER_I_16();
7127 if(register_list & (1 << i))
7129 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7135 USE_CYCLES(count<<CYC_MOVEM_W);
7139 M68KMAKE_OP(movem, 16, er, pcdi)
7142 uint register_list = OPER_I_16();
7143 uint ea = EA_PCDI_16();
7147 if(register_list & (1 << i))
7149 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7154 USE_CYCLES(count<<CYC_MOVEM_W);
7158 M68KMAKE_OP(movem, 16, er, pcix)
7161 uint register_list = OPER_I_16();
7162 uint ea = EA_PCIX_16();
7166 if(register_list & (1 << i))
7168 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7173 USE_CYCLES(count<<CYC_MOVEM_W);
7177 M68KMAKE_OP(movem, 16, er, .)
7180 uint register_list = OPER_I_16();
7181 uint ea = M68KMAKE_GET_EA_AY_16;
7185 if(register_list & (1 << i))
7187 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7192 USE_CYCLES(count<<CYC_MOVEM_W);
7196 M68KMAKE_OP(movem, 32, er, pi)
7199 uint register_list = OPER_I_16();
7204 if(register_list & (1 << i))
7206 REG_DA[i] = m68ki_read_32(ea);
7212 USE_CYCLES(count<<CYC_MOVEM_L);
7216 M68KMAKE_OP(movem, 32, er, pcdi)
7219 uint register_list = OPER_I_16();
7220 uint ea = EA_PCDI_32();
7224 if(register_list & (1 << i))
7226 REG_DA[i] = m68ki_read_pcrel_32(ea);
7231 USE_CYCLES(count<<CYC_MOVEM_L);
7235 M68KMAKE_OP(movem, 32, er, pcix)
7238 uint register_list = OPER_I_16();
7239 uint ea = EA_PCIX_32();
7243 if(register_list & (1 << i))
7245 REG_DA[i] = m68ki_read_pcrel_32(ea);
7250 USE_CYCLES(count<<CYC_MOVEM_L);
7254 M68KMAKE_OP(movem, 32, er, .)
7257 uint register_list = OPER_I_16();
7258 uint ea = M68KMAKE_GET_EA_AY_32;
7262 if(register_list & (1 << i))
7264 REG_DA[i] = m68ki_read_32(ea);
7269 USE_CYCLES(count<<CYC_MOVEM_L);
7273 M68KMAKE_OP(movep, 16, re, .)
7275 uint ea = EA_AY_DI_16();
7278 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
7279 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7283 M68KMAKE_OP(movep, 32, re, .)
7285 uint ea = EA_AY_DI_32();
7288 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
7289 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
7290 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
7291 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7295 M68KMAKE_OP(movep, 16, er, .)
7297 uint ea = EA_AY_DI_16();
7300 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
7304 M68KMAKE_OP(movep, 32, er, .)
7306 uint ea = EA_AY_DI_32();
7308 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
7309 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
7313 M68KMAKE_OP(moves, 8, ., .)
7315 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7319 uint word2 = OPER_I_16();
7320 uint ea = M68KMAKE_GET_EA_AY_8;
7322 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7323 if(BIT_B(word2)) /* Register to memory */
7325 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
7328 if(BIT_F(word2)) /* Memory to address register */
7330 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
7331 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7335 /* Memory to data register */
7336 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
7337 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7341 m68ki_exception_privilege_violation();
7344 m68ki_exception_illegal();
7348 M68KMAKE_OP(moves, 16, ., .)
7350 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7354 uint word2 = OPER_I_16();
7355 uint ea = M68KMAKE_GET_EA_AY_16;
7357 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7358 if(BIT_B(word2)) /* Register to memory */
7360 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
7363 if(BIT_F(word2)) /* Memory to address register */
7365 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
7366 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7370 /* Memory to data register */
7371 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
7372 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7376 m68ki_exception_privilege_violation();
7379 m68ki_exception_illegal();
7383 M68KMAKE_OP(moves, 32, ., .)
7385 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7389 uint word2 = OPER_I_16();
7390 uint ea = M68KMAKE_GET_EA_AY_32;
7392 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7393 if(BIT_B(word2)) /* Register to memory */
7395 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
7396 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7400 /* Memory to register */
7401 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
7402 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7406 m68ki_exception_privilege_violation();
7409 m68ki_exception_illegal();
7413 M68KMAKE_OP(moveq, 32, ., .)
7415 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
7417 FLAG_N = NFLAG_32(res);
7419 FLAG_V = VFLAG_CLEAR;
7420 FLAG_C = CFLAG_CLEAR;
7424 M68KMAKE_OP(move16, 32, ., .)
7426 uint16 w2 = OPER_I_16();
7427 int ax = REG_IR & 7;
7428 int ay = (w2 >> 12) & 7;
7430 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
7431 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
7432 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
7433 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
7440 M68KMAKE_OP(muls, 16, ., d)
7443 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7448 FLAG_N = NFLAG_32(res);
7449 FLAG_V = VFLAG_CLEAR;
7450 FLAG_C = CFLAG_CLEAR;
7454 M68KMAKE_OP(muls, 16, ., .)
7457 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7462 FLAG_N = NFLAG_32(res);
7463 FLAG_V = VFLAG_CLEAR;
7464 FLAG_C = CFLAG_CLEAR;
7468 M68KMAKE_OP(mulu, 16, ., d)
7471 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
7476 FLAG_N = NFLAG_32(res);
7477 FLAG_V = VFLAG_CLEAR;
7478 FLAG_C = CFLAG_CLEAR;
7482 M68KMAKE_OP(mulu, 16, ., .)
7485 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
7490 FLAG_N = NFLAG_32(res);
7491 FLAG_V = VFLAG_CLEAR;
7492 FLAG_C = CFLAG_CLEAR;
7496 M68KMAKE_OP(mull, 32, ., d)
7500 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7502 uint word2 = OPER_I_16();
7504 uint64 dst = REG_D[(word2 >> 12) & 7];
7507 FLAG_C = CFLAG_CLEAR;
7509 if(BIT_B(word2)) /* signed */
7511 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7514 FLAG_Z = MASK_OUT_ABOVE_32(res);
7515 FLAG_N = NFLAG_32(res);
7516 FLAG_V = ((sint64)res != (sint32)res)<<7;
7517 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7520 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7521 FLAG_N = NFLAG_64(res);
7522 FLAG_V = VFLAG_CLEAR;
7523 REG_D[word2 & 7] = (res >> 32);
7524 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7531 FLAG_Z = MASK_OUT_ABOVE_32(res);
7532 FLAG_N = NFLAG_32(res);
7533 FLAG_V = (res > 0xffffffff)<<7;
7534 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7537 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7538 FLAG_N = NFLAG_64(res);
7539 FLAG_V = VFLAG_CLEAR;
7540 REG_D[word2 & 7] = (res >> 32);
7541 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7544 m68ki_exception_illegal();
7548 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7550 uint word2 = OPER_I_16();
7552 uint dst = REG_D[(word2 >> 12) & 7];
7553 uint neg = GET_MSB_32(src ^ dst);
7565 FLAG_C = CFLAG_CLEAR;
7567 if(BIT_B(word2)) /* signed */
7570 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7572 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7575 src1 = MASK_OUT_ABOVE_16(src);
7577 dst1 = MASK_OUT_ABOVE_16(dst);
7586 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7587 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7589 if(BIT_B(word2) && neg)
7591 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7592 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7597 REG_D[word2 & 7] = hi;
7598 REG_D[(word2 >> 12) & 7] = lo;
7599 FLAG_N = NFLAG_32(hi);
7601 FLAG_V = VFLAG_CLEAR;
7605 REG_D[(word2 >> 12) & 7] = lo;
7606 FLAG_N = NFLAG_32(lo);
7609 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7611 FLAG_V = (hi != 0) << 7;
7614 m68ki_exception_illegal();
7620 M68KMAKE_OP(mull, 32, ., .)
7624 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7626 uint word2 = OPER_I_16();
7627 uint64 src = M68KMAKE_GET_OPER_AY_32;
7628 uint64 dst = REG_D[(word2 >> 12) & 7];
7631 FLAG_C = CFLAG_CLEAR;
7633 if(BIT_B(word2)) /* signed */
7635 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7638 FLAG_Z = MASK_OUT_ABOVE_32(res);
7639 FLAG_N = NFLAG_32(res);
7640 FLAG_V = ((sint64)res != (sint32)res)<<7;
7641 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7644 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7645 FLAG_N = NFLAG_64(res);
7646 FLAG_V = VFLAG_CLEAR;
7647 REG_D[word2 & 7] = (res >> 32);
7648 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7655 FLAG_Z = MASK_OUT_ABOVE_32(res);
7656 FLAG_N = NFLAG_32(res);
7657 FLAG_V = (res > 0xffffffff)<<7;
7658 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7661 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7662 FLAG_N = NFLAG_64(res);
7663 FLAG_V = VFLAG_CLEAR;
7664 REG_D[word2 & 7] = (res >> 32);
7665 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7668 m68ki_exception_illegal();
7672 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7674 uint word2 = OPER_I_16();
7675 uint src = M68KMAKE_GET_OPER_AY_32;
7676 uint dst = REG_D[(word2 >> 12) & 7];
7677 uint neg = GET_MSB_32(src ^ dst);
7689 FLAG_C = CFLAG_CLEAR;
7691 if(BIT_B(word2)) /* signed */
7694 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7696 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7699 src1 = MASK_OUT_ABOVE_16(src);
7701 dst1 = MASK_OUT_ABOVE_16(dst);
7710 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7711 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7713 if(BIT_B(word2) && neg)
7715 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7716 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7721 REG_D[word2 & 7] = hi;
7722 REG_D[(word2 >> 12) & 7] = lo;
7723 FLAG_N = NFLAG_32(hi);
7725 FLAG_V = VFLAG_CLEAR;
7729 REG_D[(word2 >> 12) & 7] = lo;
7730 FLAG_N = NFLAG_32(lo);
7733 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7735 FLAG_V = (hi != 0) << 7;
7738 m68ki_exception_illegal();
7744 M68KMAKE_OP(nbcd, 8, ., d)
7748 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
7752 FLAG_V = ~res; /* Undefined V behavior */
7754 if((res & 0x0f) == 0xa)
7755 res = (res & 0xf0) + 0x10;
7757 res = MASK_OUT_ABOVE_8(res);
7759 FLAG_V &= res; /* Undefined V behavior part II */
7761 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7769 FLAG_V = VFLAG_CLEAR;
7770 FLAG_C = CFLAG_CLEAR;
7771 FLAG_X = XFLAG_CLEAR;
7773 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7777 M68KMAKE_OP(nbcd, 8, ., .)
7779 uint ea = M68KMAKE_GET_EA_AY_8;
7780 uint dst = m68ki_read_8(ea);
7781 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
7785 FLAG_V = ~res; /* Undefined V behavior */
7787 if((res & 0x0f) == 0xa)
7788 res = (res & 0xf0) + 0x10;
7790 res = MASK_OUT_ABOVE_8(res);
7792 FLAG_V &= res; /* Undefined V behavior part II */
7794 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
7802 FLAG_V = VFLAG_CLEAR;
7803 FLAG_C = CFLAG_CLEAR;
7804 FLAG_X = XFLAG_CLEAR;
7806 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7810 M68KMAKE_OP(neg, 8, ., d)
7813 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
7815 FLAG_N = NFLAG_8(res);
7816 FLAG_C = FLAG_X = CFLAG_8(res);
7817 FLAG_V = *r_dst & res;
7818 FLAG_Z = MASK_OUT_ABOVE_8(res);
7820 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
7824 M68KMAKE_OP(neg, 8, ., .)
7826 uint ea = M68KMAKE_GET_EA_AY_8;
7827 uint src = m68ki_read_8(ea);
7830 FLAG_N = NFLAG_8(res);
7831 FLAG_C = FLAG_X = CFLAG_8(res);
7833 FLAG_Z = MASK_OUT_ABOVE_8(res);
7835 m68ki_write_8(ea, FLAG_Z);
7839 M68KMAKE_OP(neg, 16, ., d)
7842 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
7844 FLAG_N = NFLAG_16(res);
7845 FLAG_C = FLAG_X = CFLAG_16(res);
7846 FLAG_V = (*r_dst & res)>>8;
7847 FLAG_Z = MASK_OUT_ABOVE_16(res);
7849 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
7853 M68KMAKE_OP(neg, 16, ., .)
7855 uint ea = M68KMAKE_GET_EA_AY_16;
7856 uint src = m68ki_read_16(ea);
7859 FLAG_N = NFLAG_16(res);
7860 FLAG_C = FLAG_X = CFLAG_16(res);
7861 FLAG_V = (src & res)>>8;
7862 FLAG_Z = MASK_OUT_ABOVE_16(res);
7864 m68ki_write_16(ea, FLAG_Z);
7868 M68KMAKE_OP(neg, 32, ., d)
7871 uint res = 0 - *r_dst;
7873 FLAG_N = NFLAG_32(res);
7874 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
7875 FLAG_V = (*r_dst & res)>>24;
7876 FLAG_Z = MASK_OUT_ABOVE_32(res);
7882 M68KMAKE_OP(neg, 32, ., .)
7884 uint ea = M68KMAKE_GET_EA_AY_32;
7885 uint src = m68ki_read_32(ea);
7888 FLAG_N = NFLAG_32(res);
7889 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
7890 FLAG_V = (src & res)>>24;
7891 FLAG_Z = MASK_OUT_ABOVE_32(res);
7893 m68ki_write_32(ea, FLAG_Z);
7897 M68KMAKE_OP(negx, 8, ., d)
7900 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
7902 FLAG_N = NFLAG_8(res);
7903 FLAG_X = FLAG_C = CFLAG_8(res);
7904 FLAG_V = *r_dst & res;
7906 res = MASK_OUT_ABOVE_8(res);
7909 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7913 M68KMAKE_OP(negx, 8, ., .)
7915 uint ea = M68KMAKE_GET_EA_AY_8;
7916 uint src = m68ki_read_8(ea);
7917 uint res = 0 - src - XFLAG_AS_1();
7919 FLAG_N = NFLAG_8(res);
7920 FLAG_X = FLAG_C = CFLAG_8(res);
7923 res = MASK_OUT_ABOVE_8(res);
7926 m68ki_write_8(ea, res);
7930 M68KMAKE_OP(negx, 16, ., d)
7933 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
7935 FLAG_N = NFLAG_16(res);
7936 FLAG_X = FLAG_C = CFLAG_16(res);
7937 FLAG_V = (*r_dst & res)>>8;
7939 res = MASK_OUT_ABOVE_16(res);
7942 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
7946 M68KMAKE_OP(negx, 16, ., .)
7948 uint ea = M68KMAKE_GET_EA_AY_16;
7949 uint src = m68ki_read_16(ea);
7950 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
7952 FLAG_N = NFLAG_16(res);
7953 FLAG_X = FLAG_C = CFLAG_16(res);
7954 FLAG_V = (src & res)>>8;
7956 res = MASK_OUT_ABOVE_16(res);
7959 m68ki_write_16(ea, res);
7963 M68KMAKE_OP(negx, 32, ., d)
7966 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
7968 FLAG_N = NFLAG_32(res);
7969 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
7970 FLAG_V = (*r_dst & res)>>24;
7972 res = MASK_OUT_ABOVE_32(res);
7979 M68KMAKE_OP(negx, 32, ., .)
7981 uint ea = M68KMAKE_GET_EA_AY_32;
7982 uint src = m68ki_read_32(ea);
7983 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
7985 FLAG_N = NFLAG_32(res);
7986 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
7987 FLAG_V = (src & res)>>24;
7989 res = MASK_OUT_ABOVE_32(res);
7992 m68ki_write_32(ea, res);
7996 M68KMAKE_OP(nop, 0, ., .)
7998 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8002 M68KMAKE_OP(not, 8, ., d)
8005 uint res = MASK_OUT_ABOVE_8(~*r_dst);
8007 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8009 FLAG_N = NFLAG_8(res);
8011 FLAG_C = CFLAG_CLEAR;
8012 FLAG_V = VFLAG_CLEAR;
8016 M68KMAKE_OP(not, 8, ., .)
8018 uint ea = M68KMAKE_GET_EA_AY_8;
8019 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
8021 m68ki_write_8(ea, res);
8023 FLAG_N = NFLAG_8(res);
8025 FLAG_C = CFLAG_CLEAR;
8026 FLAG_V = VFLAG_CLEAR;
8030 M68KMAKE_OP(not, 16, ., d)
8033 uint res = MASK_OUT_ABOVE_16(~*r_dst);
8035 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8037 FLAG_N = NFLAG_16(res);
8039 FLAG_C = CFLAG_CLEAR;
8040 FLAG_V = VFLAG_CLEAR;
8044 M68KMAKE_OP(not, 16, ., .)
8046 uint ea = M68KMAKE_GET_EA_AY_16;
8047 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
8049 m68ki_write_16(ea, res);
8051 FLAG_N = NFLAG_16(res);
8053 FLAG_C = CFLAG_CLEAR;
8054 FLAG_V = VFLAG_CLEAR;
8058 M68KMAKE_OP(not, 32, ., d)
8061 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
8063 FLAG_N = NFLAG_32(res);
8065 FLAG_C = CFLAG_CLEAR;
8066 FLAG_V = VFLAG_CLEAR;
8070 M68KMAKE_OP(not, 32, ., .)
8072 uint ea = M68KMAKE_GET_EA_AY_32;
8073 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
8075 m68ki_write_32(ea, res);
8077 FLAG_N = NFLAG_32(res);
8079 FLAG_C = CFLAG_CLEAR;
8080 FLAG_V = VFLAG_CLEAR;
8084 M68KMAKE_OP(or, 8, er, d)
8086 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
8088 FLAG_N = NFLAG_8(res);
8090 FLAG_C = CFLAG_CLEAR;
8091 FLAG_V = VFLAG_CLEAR;
8095 M68KMAKE_OP(or, 8, er, .)
8097 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
8099 FLAG_N = NFLAG_8(res);
8101 FLAG_C = CFLAG_CLEAR;
8102 FLAG_V = VFLAG_CLEAR;
8106 M68KMAKE_OP(or, 16, er, d)
8108 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
8110 FLAG_N = NFLAG_16(res);
8112 FLAG_C = CFLAG_CLEAR;
8113 FLAG_V = VFLAG_CLEAR;
8117 M68KMAKE_OP(or, 16, er, .)
8119 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
8121 FLAG_N = NFLAG_16(res);
8123 FLAG_C = CFLAG_CLEAR;
8124 FLAG_V = VFLAG_CLEAR;
8128 M68KMAKE_OP(or, 32, er, d)
8130 uint res = DX |= DY;
8132 FLAG_N = NFLAG_32(res);
8134 FLAG_C = CFLAG_CLEAR;
8135 FLAG_V = VFLAG_CLEAR;
8139 M68KMAKE_OP(or, 32, er, .)
8141 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
8143 FLAG_N = NFLAG_32(res);
8145 FLAG_C = CFLAG_CLEAR;
8146 FLAG_V = VFLAG_CLEAR;
8150 M68KMAKE_OP(or, 8, re, .)
8152 uint ea = M68KMAKE_GET_EA_AY_8;
8153 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
8155 m68ki_write_8(ea, res);
8157 FLAG_N = NFLAG_8(res);
8159 FLAG_C = CFLAG_CLEAR;
8160 FLAG_V = VFLAG_CLEAR;
8164 M68KMAKE_OP(or, 16, re, .)
8166 uint ea = M68KMAKE_GET_EA_AY_16;
8167 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
8169 m68ki_write_16(ea, res);
8171 FLAG_N = NFLAG_16(res);
8173 FLAG_C = CFLAG_CLEAR;
8174 FLAG_V = VFLAG_CLEAR;
8178 M68KMAKE_OP(or, 32, re, .)
8180 uint ea = M68KMAKE_GET_EA_AY_32;
8181 uint res = DX | m68ki_read_32(ea);
8183 m68ki_write_32(ea, res);
8185 FLAG_N = NFLAG_32(res);
8187 FLAG_C = CFLAG_CLEAR;
8188 FLAG_V = VFLAG_CLEAR;
8192 M68KMAKE_OP(ori, 8, ., d)
8194 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
8196 FLAG_N = NFLAG_8(res);
8198 FLAG_C = CFLAG_CLEAR;
8199 FLAG_V = VFLAG_CLEAR;
8203 M68KMAKE_OP(ori, 8, ., .)
8205 uint src = OPER_I_8();
8206 uint ea = M68KMAKE_GET_EA_AY_8;
8207 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
8209 m68ki_write_8(ea, res);
8211 FLAG_N = NFLAG_8(res);
8213 FLAG_C = CFLAG_CLEAR;
8214 FLAG_V = VFLAG_CLEAR;
8218 M68KMAKE_OP(ori, 16, ., d)
8220 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
8222 FLAG_N = NFLAG_16(res);
8224 FLAG_C = CFLAG_CLEAR;
8225 FLAG_V = VFLAG_CLEAR;
8229 M68KMAKE_OP(ori, 16, ., .)
8231 uint src = OPER_I_16();
8232 uint ea = M68KMAKE_GET_EA_AY_16;
8233 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
8235 m68ki_write_16(ea, res);
8237 FLAG_N = NFLAG_16(res);
8239 FLAG_C = CFLAG_CLEAR;
8240 FLAG_V = VFLAG_CLEAR;
8244 M68KMAKE_OP(ori, 32, ., d)
8246 uint res = DY |= OPER_I_32();
8248 FLAG_N = NFLAG_32(res);
8250 FLAG_C = CFLAG_CLEAR;
8251 FLAG_V = VFLAG_CLEAR;
8255 M68KMAKE_OP(ori, 32, ., .)
8257 uint src = OPER_I_32();
8258 uint ea = M68KMAKE_GET_EA_AY_32;
8259 uint res = src | m68ki_read_32(ea);
8261 m68ki_write_32(ea, res);
8263 FLAG_N = NFLAG_32(res);
8265 FLAG_C = CFLAG_CLEAR;
8266 FLAG_V = VFLAG_CLEAR;
8270 M68KMAKE_OP(ori, 16, toc, .)
8272 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8());
8276 M68KMAKE_OP(ori, 16, tos, .)
8280 uint src = OPER_I_16();
8281 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8282 m68ki_set_sr(m68ki_get_sr() | src);
8285 m68ki_exception_privilege_violation();
8289 M68KMAKE_OP(pack, 16, rr, .)
8291 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8293 /* Note: DX and DY are reversed in Motorola's docs */
8294 uint src = DY + OPER_I_16();
8297 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
8300 m68ki_exception_illegal();
8304 M68KMAKE_OP(pack, 16, mm, ax7)
8306 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8308 /* Note: AX and AY are reversed in Motorola's docs */
8309 uint ea_src = EA_AY_PD_8();
8310 uint src = m68ki_read_8(ea_src);
8311 ea_src = EA_AY_PD_8();
8312 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8314 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8317 m68ki_exception_illegal();
8321 M68KMAKE_OP(pack, 16, mm, ay7)
8323 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8325 /* Note: AX and AY are reversed in Motorola's docs */
8326 uint ea_src = EA_A7_PD_8();
8327 uint src = m68ki_read_8(ea_src);
8328 ea_src = EA_A7_PD_8();
8329 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8331 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8334 m68ki_exception_illegal();
8338 M68KMAKE_OP(pack, 16, mm, axy7)
8340 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8342 uint ea_src = EA_A7_PD_8();
8343 uint src = m68ki_read_8(ea_src);
8344 ea_src = EA_A7_PD_8();
8345 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8347 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8350 m68ki_exception_illegal();
8354 M68KMAKE_OP(pack, 16, mm, .)
8356 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8358 /* Note: AX and AY are reversed in Motorola's docs */
8359 uint ea_src = EA_AY_PD_8();
8360 uint src = m68ki_read_8(ea_src);
8361 ea_src = EA_AY_PD_8();
8362 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8364 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8367 m68ki_exception_illegal();
8371 M68KMAKE_OP(pea, 32, ., .)
8373 uint ea = M68KMAKE_GET_EA_AY_32;
8378 M68KMAKE_OP(pflush, 32, ., .)
8380 if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU))
8382 fprintf(stderr,"68040: unhandled PFLUSH\n");
8385 m68ki_exception_1111();
8388 M68KMAKE_OP(pmmu, 32, ., .)
8390 if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU))
8396 m68ki_exception_1111();
8400 M68KMAKE_OP(reset, 0, ., .)
8404 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
8405 USE_CYCLES(CYC_RESET);
8408 m68ki_exception_privilege_violation();
8412 M68KMAKE_OP(ror, 8, s, .)
8415 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8416 uint shift = orig_shift & 7;
8417 uint src = MASK_OUT_ABOVE_8(*r_dst);
8418 uint res = ROR_8(src, shift);
8421 USE_CYCLES(orig_shift<<CYC_SHIFT);
8423 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8425 FLAG_N = NFLAG_8(res);
8427 FLAG_C = src << (9-orig_shift);
8428 FLAG_V = VFLAG_CLEAR;
8432 M68KMAKE_OP(ror, 16, s, .)
8435 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8436 uint src = MASK_OUT_ABOVE_16(*r_dst);
8437 uint res = ROR_16(src, shift);
8440 USE_CYCLES(shift<<CYC_SHIFT);
8442 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8444 FLAG_N = NFLAG_16(res);
8446 FLAG_C = src << (9-shift);
8447 FLAG_V = VFLAG_CLEAR;
8451 M68KMAKE_OP(ror, 32, s, .)
8454 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8455 uint64 src = *r_dst;
8456 uint res = ROR_32(src, shift);
8459 USE_CYCLES(shift<<CYC_SHIFT);
8463 FLAG_N = NFLAG_32(res);
8465 FLAG_C = src << (9-shift);
8466 FLAG_V = VFLAG_CLEAR;
8470 M68KMAKE_OP(ror, 8, r, .)
8473 uint orig_shift = DX & 0x3f;
8474 uint shift = orig_shift & 7;
8475 uint src = MASK_OUT_ABOVE_8(*r_dst);
8476 uint res = ROR_8(src, shift);
8480 USE_CYCLES(orig_shift<<CYC_SHIFT);
8482 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8483 FLAG_C = src << (8-((shift-1)&7));
8484 FLAG_N = NFLAG_8(res);
8486 FLAG_V = VFLAG_CLEAR;
8490 FLAG_C = CFLAG_CLEAR;
8491 FLAG_N = NFLAG_8(src);
8493 FLAG_V = VFLAG_CLEAR;
8497 M68KMAKE_OP(ror, 16, r, .)
8500 uint orig_shift = DX & 0x3f;
8501 uint shift = orig_shift & 15;
8502 uint src = MASK_OUT_ABOVE_16(*r_dst);
8503 uint res = ROR_16(src, shift);
8507 USE_CYCLES(orig_shift<<CYC_SHIFT);
8509 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8510 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
8511 FLAG_N = NFLAG_16(res);
8513 FLAG_V = VFLAG_CLEAR;
8517 FLAG_C = CFLAG_CLEAR;
8518 FLAG_N = NFLAG_16(src);
8520 FLAG_V = VFLAG_CLEAR;
8524 M68KMAKE_OP(ror, 32, r, .)
8527 uint orig_shift = DX & 0x3f;
8528 uint shift = orig_shift & 31;
8529 uint64 src = *r_dst;
8530 uint res = ROR_32(src, shift);
8534 USE_CYCLES(orig_shift<<CYC_SHIFT);
8537 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
8538 FLAG_N = NFLAG_32(res);
8540 FLAG_V = VFLAG_CLEAR;
8544 FLAG_C = CFLAG_CLEAR;
8545 FLAG_N = NFLAG_32(src);
8547 FLAG_V = VFLAG_CLEAR;
8551 M68KMAKE_OP(ror, 16, ., .)
8553 uint ea = M68KMAKE_GET_EA_AY_16;
8554 uint src = m68ki_read_16(ea);
8555 uint res = ROR_16(src, 1);
8557 m68ki_write_16(ea, res);
8559 FLAG_N = NFLAG_16(res);
8562 FLAG_V = VFLAG_CLEAR;
8566 M68KMAKE_OP(rol, 8, s, .)
8569 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8570 uint shift = orig_shift & 7;
8571 uint src = MASK_OUT_ABOVE_8(*r_dst);
8572 uint res = ROL_8(src, shift);
8575 USE_CYCLES(orig_shift<<CYC_SHIFT);
8577 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8579 FLAG_N = NFLAG_8(res);
8581 FLAG_C = src << orig_shift;
8582 FLAG_V = VFLAG_CLEAR;
8586 M68KMAKE_OP(rol, 16, s, .)
8589 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8590 uint src = MASK_OUT_ABOVE_16(*r_dst);
8591 uint res = ROL_16(src, shift);
8594 USE_CYCLES(shift<<CYC_SHIFT);
8596 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8598 FLAG_N = NFLAG_16(res);
8600 FLAG_C = src >> (8-shift);
8601 FLAG_V = VFLAG_CLEAR;
8605 M68KMAKE_OP(rol, 32, s, .)
8608 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8609 uint64 src = *r_dst;
8610 uint res = ROL_32(src, shift);
8613 USE_CYCLES(shift<<CYC_SHIFT);
8617 FLAG_N = NFLAG_32(res);
8619 FLAG_C = src >> (24-shift);
8620 FLAG_V = VFLAG_CLEAR;
8624 M68KMAKE_OP(rol, 8, r, .)
8627 uint orig_shift = DX & 0x3f;
8628 uint shift = orig_shift & 7;
8629 uint src = MASK_OUT_ABOVE_8(*r_dst);
8630 uint res = ROL_8(src, shift);
8634 USE_CYCLES(orig_shift<<CYC_SHIFT);
8638 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8639 FLAG_C = src << shift;
8640 FLAG_N = NFLAG_8(res);
8642 FLAG_V = VFLAG_CLEAR;
8645 FLAG_C = (src & 1)<<8;
8646 FLAG_N = NFLAG_8(src);
8648 FLAG_V = VFLAG_CLEAR;
8652 FLAG_C = CFLAG_CLEAR;
8653 FLAG_N = NFLAG_8(src);
8655 FLAG_V = VFLAG_CLEAR;
8659 M68KMAKE_OP(rol, 16, r, .)
8662 uint orig_shift = DX & 0x3f;
8663 uint shift = orig_shift & 15;
8664 uint src = MASK_OUT_ABOVE_16(*r_dst);
8665 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
8669 USE_CYCLES(orig_shift<<CYC_SHIFT);
8673 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8674 FLAG_C = (src << shift) >> 8;
8675 FLAG_N = NFLAG_16(res);
8677 FLAG_V = VFLAG_CLEAR;
8680 FLAG_C = (src & 1)<<8;
8681 FLAG_N = NFLAG_16(src);
8683 FLAG_V = VFLAG_CLEAR;
8687 FLAG_C = CFLAG_CLEAR;
8688 FLAG_N = NFLAG_16(src);
8690 FLAG_V = VFLAG_CLEAR;
8694 M68KMAKE_OP(rol, 32, r, .)
8697 uint orig_shift = DX & 0x3f;
8698 uint shift = orig_shift & 31;
8699 uint64 src = *r_dst;
8700 uint res = ROL_32(src, shift);
8704 USE_CYCLES(orig_shift<<CYC_SHIFT);
8708 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
8709 FLAG_N = NFLAG_32(res);
8711 FLAG_V = VFLAG_CLEAR;
8715 FLAG_C = CFLAG_CLEAR;
8716 FLAG_N = NFLAG_32(src);
8718 FLAG_V = VFLAG_CLEAR;
8722 M68KMAKE_OP(rol, 16, ., .)
8724 uint ea = M68KMAKE_GET_EA_AY_16;
8725 uint src = m68ki_read_16(ea);
8726 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
8728 m68ki_write_16(ea, res);
8730 FLAG_N = NFLAG_16(res);
8733 FLAG_V = VFLAG_CLEAR;
8737 M68KMAKE_OP(roxr, 8, s, .)
8740 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8741 uint src = MASK_OUT_ABOVE_8(*r_dst);
8742 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8745 USE_CYCLES(shift<<CYC_SHIFT);
8747 FLAG_C = FLAG_X = res;
8748 res = MASK_OUT_ABOVE_8(res);
8750 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8752 FLAG_N = NFLAG_8(res);
8754 FLAG_V = VFLAG_CLEAR;
8758 M68KMAKE_OP(roxr, 16, s, .)
8761 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8762 uint src = MASK_OUT_ABOVE_16(*r_dst);
8763 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8766 USE_CYCLES(shift<<CYC_SHIFT);
8768 FLAG_C = FLAG_X = res >> 8;
8769 res = MASK_OUT_ABOVE_16(res);
8771 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8773 FLAG_N = NFLAG_16(res);
8775 FLAG_V = VFLAG_CLEAR;
8779 M68KMAKE_OP(roxr, 32, s, .)
8784 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8785 uint64 src = *r_dst;
8786 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8789 USE_CYCLES(shift<<CYC_SHIFT);
8791 res = ROR_33_64(res, shift);
8793 FLAG_C = FLAG_X = res >> 24;
8794 res = MASK_OUT_ABOVE_32(res);
8798 FLAG_N = NFLAG_32(res);
8800 FLAG_V = VFLAG_CLEAR;
8805 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8807 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8808 uint new_x_flag = src & (1 << (shift - 1));
8811 USE_CYCLES(shift<<CYC_SHIFT);
8815 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
8816 FLAG_N = NFLAG_32(res);
8818 FLAG_V = VFLAG_CLEAR;
8824 M68KMAKE_OP(roxr, 8, r, .)
8827 uint orig_shift = DX & 0x3f;
8831 uint shift = orig_shift % 9;
8832 uint src = MASK_OUT_ABOVE_8(*r_dst);
8833 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8835 USE_CYCLES(orig_shift<<CYC_SHIFT);
8837 FLAG_C = FLAG_X = res;
8838 res = MASK_OUT_ABOVE_8(res);
8840 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8841 FLAG_N = NFLAG_8(res);
8843 FLAG_V = VFLAG_CLEAR;
8848 FLAG_N = NFLAG_8(*r_dst);
8849 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
8850 FLAG_V = VFLAG_CLEAR;
8854 M68KMAKE_OP(roxr, 16, r, .)
8857 uint orig_shift = DX & 0x3f;
8861 uint shift = orig_shift % 17;
8862 uint src = MASK_OUT_ABOVE_16(*r_dst);
8863 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8865 USE_CYCLES(orig_shift<<CYC_SHIFT);
8867 FLAG_C = FLAG_X = res >> 8;
8868 res = MASK_OUT_ABOVE_16(res);
8870 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8871 FLAG_N = NFLAG_16(res);
8873 FLAG_V = VFLAG_CLEAR;
8878 FLAG_N = NFLAG_16(*r_dst);
8879 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
8880 FLAG_V = VFLAG_CLEAR;
8884 M68KMAKE_OP(roxr, 32, r, .)
8889 uint orig_shift = DX & 0x3f;
8893 uint shift = orig_shift % 33;
8894 uint64 src = *r_dst;
8895 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8897 res = ROR_33_64(res, shift);
8899 USE_CYCLES(orig_shift<<CYC_SHIFT);
8901 FLAG_C = FLAG_X = res >> 24;
8902 res = MASK_OUT_ABOVE_32(res);
8905 FLAG_N = NFLAG_32(res);
8907 FLAG_V = VFLAG_CLEAR;
8912 FLAG_N = NFLAG_32(*r_dst);
8914 FLAG_V = VFLAG_CLEAR;
8919 uint orig_shift = DX & 0x3f;
8920 uint shift = orig_shift % 33;
8922 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8923 uint new_x_flag = src & (1 << (shift - 1));
8926 USE_CYCLES(orig_shift<<CYC_SHIFT);
8931 FLAG_X = (new_x_flag != 0)<<8;
8936 FLAG_N = NFLAG_32(res);
8938 FLAG_V = VFLAG_CLEAR;
8944 M68KMAKE_OP(roxr, 16, ., .)
8946 uint ea = M68KMAKE_GET_EA_AY_16;
8947 uint src = m68ki_read_16(ea);
8948 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
8950 FLAG_C = FLAG_X = res >> 8;
8951 res = MASK_OUT_ABOVE_16(res);
8953 m68ki_write_16(ea, res);
8955 FLAG_N = NFLAG_16(res);
8957 FLAG_V = VFLAG_CLEAR;
8961 M68KMAKE_OP(roxl, 8, s, .)
8964 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8965 uint src = MASK_OUT_ABOVE_8(*r_dst);
8966 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
8969 USE_CYCLES(shift<<CYC_SHIFT);
8971 FLAG_C = FLAG_X = res;
8972 res = MASK_OUT_ABOVE_8(res);
8974 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8976 FLAG_N = NFLAG_8(res);
8978 FLAG_V = VFLAG_CLEAR;
8982 M68KMAKE_OP(roxl, 16, s, .)
8985 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8986 uint src = MASK_OUT_ABOVE_16(*r_dst);
8987 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
8990 USE_CYCLES(shift<<CYC_SHIFT);
8992 FLAG_C = FLAG_X = res >> 8;
8993 res = MASK_OUT_ABOVE_16(res);
8995 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8997 FLAG_N = NFLAG_16(res);
8999 FLAG_V = VFLAG_CLEAR;
9003 M68KMAKE_OP(roxl, 32, s, .)
9008 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9009 uint64 src = *r_dst;
9010 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9013 USE_CYCLES(shift<<CYC_SHIFT);
9015 res = ROL_33_64(res, shift);
9017 FLAG_C = FLAG_X = res >> 24;
9018 res = MASK_OUT_ABOVE_32(res);
9022 FLAG_N = NFLAG_32(res);
9024 FLAG_V = VFLAG_CLEAR;
9029 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9031 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9032 uint new_x_flag = src & (1 << (32 - shift));
9035 USE_CYCLES(shift<<CYC_SHIFT);
9039 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
9040 FLAG_N = NFLAG_32(res);
9042 FLAG_V = VFLAG_CLEAR;
9048 M68KMAKE_OP(roxl, 8, r, .)
9051 uint orig_shift = DX & 0x3f;
9056 uint shift = orig_shift % 9;
9057 uint src = MASK_OUT_ABOVE_8(*r_dst);
9058 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9060 USE_CYCLES(orig_shift<<CYC_SHIFT);
9062 FLAG_C = FLAG_X = res;
9063 res = MASK_OUT_ABOVE_8(res);
9065 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9066 FLAG_N = NFLAG_8(res);
9068 FLAG_V = VFLAG_CLEAR;
9073 FLAG_N = NFLAG_8(*r_dst);
9074 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
9075 FLAG_V = VFLAG_CLEAR;
9079 M68KMAKE_OP(roxl, 16, r, .)
9082 uint orig_shift = DX & 0x3f;
9086 uint shift = orig_shift % 17;
9087 uint src = MASK_OUT_ABOVE_16(*r_dst);
9088 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9090 USE_CYCLES(orig_shift<<CYC_SHIFT);
9092 FLAG_C = FLAG_X = res >> 8;
9093 res = MASK_OUT_ABOVE_16(res);
9095 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9096 FLAG_N = NFLAG_16(res);
9098 FLAG_V = VFLAG_CLEAR;
9103 FLAG_N = NFLAG_16(*r_dst);
9104 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
9105 FLAG_V = VFLAG_CLEAR;
9109 M68KMAKE_OP(roxl, 32, r, .)
9114 uint orig_shift = DX & 0x3f;
9118 uint shift = orig_shift % 33;
9119 uint64 src = *r_dst;
9120 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9122 res = ROL_33_64(res, shift);
9124 USE_CYCLES(orig_shift<<CYC_SHIFT);
9126 FLAG_C = FLAG_X = res >> 24;
9127 res = MASK_OUT_ABOVE_32(res);
9130 FLAG_N = NFLAG_32(res);
9132 FLAG_V = VFLAG_CLEAR;
9137 FLAG_N = NFLAG_32(*r_dst);
9139 FLAG_V = VFLAG_CLEAR;
9144 uint orig_shift = DX & 0x3f;
9145 uint shift = orig_shift % 33;
9147 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9148 uint new_x_flag = src & (1 << (32 - shift));
9151 USE_CYCLES(orig_shift<<CYC_SHIFT);
9156 FLAG_X = (new_x_flag != 0)<<8;
9161 FLAG_N = NFLAG_32(res);
9163 FLAG_V = VFLAG_CLEAR;
9169 M68KMAKE_OP(roxl, 16, ., .)
9171 uint ea = M68KMAKE_GET_EA_AY_16;
9172 uint src = m68ki_read_16(ea);
9173 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
9175 FLAG_C = FLAG_X = res >> 8;
9176 res = MASK_OUT_ABOVE_16(res);
9178 m68ki_write_16(ea, res);
9180 FLAG_N = NFLAG_16(res);
9182 FLAG_V = VFLAG_CLEAR;
9186 M68KMAKE_OP(rtd, 32, ., .)
9188 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
9190 uint new_pc = m68ki_pull_32();
9192 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9193 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
9197 m68ki_exception_illegal();
9201 M68KMAKE_OP(rte, 32, ., .)
9209 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
9210 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9212 if(CPU_TYPE_IS_000(CPU_TYPE))
9214 new_sr = m68ki_pull_16();
9215 new_pc = m68ki_pull_32();
9217 m68ki_set_sr(new_sr);
9219 CPU_INSTR_MODE = INSTRUCTION_YES;
9220 CPU_RUN_MODE = RUN_MODE_NORMAL;
9225 if(CPU_TYPE_IS_010(CPU_TYPE))
9227 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9228 if(format_word == 0)
9230 new_sr = m68ki_pull_16();
9231 new_pc = m68ki_pull_32();
9232 m68ki_fake_pull_16(); /* format word */
9234 m68ki_set_sr(new_sr);
9235 CPU_INSTR_MODE = INSTRUCTION_YES;
9236 CPU_RUN_MODE = RUN_MODE_NORMAL;
9238 } else if (format_word == 8) {
9239 /* Format 8 stack frame -- 68010 only. 29 word bus/address error */
9240 new_sr = m68ki_pull_16();
9241 new_pc = m68ki_pull_32();
9242 m68ki_fake_pull_16(); /* format word */
9243 m68ki_fake_pull_16(); /* special status word */
9244 m68ki_fake_pull_32(); /* fault address */
9245 m68ki_fake_pull_16(); /* unused/reserved */
9246 m68ki_fake_pull_16(); /* data output buffer */
9247 m68ki_fake_pull_16(); /* unused/reserved */
9248 m68ki_fake_pull_16(); /* data input buffer */
9249 m68ki_fake_pull_16(); /* unused/reserved */
9250 m68ki_fake_pull_16(); /* instruction input buffer */
9251 m68ki_fake_pull_32(); /* internal information, 16 words */
9252 m68ki_fake_pull_32(); /* (actually, we use 8 DWORDs) */
9253 m68ki_fake_pull_32();
9254 m68ki_fake_pull_32();
9255 m68ki_fake_pull_32();
9256 m68ki_fake_pull_32();
9257 m68ki_fake_pull_32();
9258 m68ki_fake_pull_32();
9260 m68ki_set_sr(new_sr);
9261 CPU_INSTR_MODE = INSTRUCTION_YES;
9262 CPU_RUN_MODE = RUN_MODE_NORMAL;
9265 CPU_INSTR_MODE = INSTRUCTION_YES;
9266 CPU_RUN_MODE = RUN_MODE_NORMAL;
9267 /* Not handling other exception types (9) */
9268 m68ki_exception_format_error();
9272 /* Otherwise it's 020 */
9274 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9277 case 0: /* Normal */
9278 new_sr = m68ki_pull_16();
9279 new_pc = m68ki_pull_32();
9280 m68ki_fake_pull_16(); /* format word */
9282 m68ki_set_sr(new_sr);
9283 CPU_INSTR_MODE = INSTRUCTION_YES;
9284 CPU_RUN_MODE = RUN_MODE_NORMAL;
9286 case 1: /* Throwaway */
9287 new_sr = m68ki_pull_16();
9288 m68ki_fake_pull_32(); /* program counter */
9289 m68ki_fake_pull_16(); /* format word */
9290 m68ki_set_sr_noint(new_sr);
9293 new_sr = m68ki_pull_16();
9294 new_pc = m68ki_pull_32();
9295 m68ki_fake_pull_16(); /* format word */
9296 m68ki_fake_pull_32(); /* address */
9298 m68ki_set_sr(new_sr);
9299 CPU_INSTR_MODE = INSTRUCTION_YES;
9300 CPU_RUN_MODE = RUN_MODE_NORMAL;
9303 /* Not handling long or short bus fault */
9304 CPU_INSTR_MODE = INSTRUCTION_YES;
9305 CPU_RUN_MODE = RUN_MODE_NORMAL;
9306 m68ki_exception_format_error();
9309 m68ki_exception_privilege_violation();
9313 M68KMAKE_OP(rtm, 32, ., .)
9315 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
9317 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9318 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
9319 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
9320 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
9323 m68ki_exception_illegal();
9327 M68KMAKE_OP(rtr, 32, ., .)
9329 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9330 m68ki_set_ccr(m68ki_pull_16());
9331 m68ki_jump(m68ki_pull_32());
9335 M68KMAKE_OP(rts, 32, ., .)
9337 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9338 m68ki_jump(m68ki_pull_32());
9342 M68KMAKE_OP(sbcd, 8, rr, .)
9347 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9349 FLAG_V = ~res; /* Undefined V behavior */
9353 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9354 FLAG_X = FLAG_C = (res > 0x99) << 8;
9358 res = MASK_OUT_ABOVE_8(res);
9360 FLAG_V &= res; /* Undefined V behavior part II */
9361 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9364 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9368 M68KMAKE_OP(sbcd, 8, mm, ax7)
9370 uint src = OPER_AY_PD_8();
9371 uint ea = EA_A7_PD_8();
9372 uint dst = m68ki_read_8(ea);
9373 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9375 FLAG_V = ~res; /* Undefined V behavior */
9379 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9380 FLAG_X = FLAG_C = (res > 0x99) << 8;
9384 res = MASK_OUT_ABOVE_8(res);
9386 FLAG_V &= res; /* Undefined V behavior part II */
9387 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9390 m68ki_write_8(ea, res);
9394 M68KMAKE_OP(sbcd, 8, mm, ay7)
9396 uint src = OPER_A7_PD_8();
9397 uint ea = EA_AX_PD_8();
9398 uint dst = m68ki_read_8(ea);
9399 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9401 FLAG_V = ~res; /* Undefined V behavior */
9405 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9406 FLAG_X = FLAG_C = (res > 0x99) << 8;
9410 res = MASK_OUT_ABOVE_8(res);
9412 FLAG_V &= res; /* Undefined V behavior part II */
9413 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9416 m68ki_write_8(ea, res);
9420 M68KMAKE_OP(sbcd, 8, mm, axy7)
9422 uint src = OPER_A7_PD_8();
9423 uint ea = EA_A7_PD_8();
9424 uint dst = m68ki_read_8(ea);
9425 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9427 FLAG_V = ~res; /* Undefined V behavior */
9431 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9432 FLAG_X = FLAG_C = (res > 0x99) << 8;
9436 res = MASK_OUT_ABOVE_8(res);
9438 FLAG_V &= res; /* Undefined V behavior part II */
9439 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9442 m68ki_write_8(ea, res);
9446 M68KMAKE_OP(sbcd, 8, mm, .)
9448 uint src = OPER_AY_PD_8();
9449 uint ea = EA_AX_PD_8();
9450 uint dst = m68ki_read_8(ea);
9451 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9453 FLAG_V = ~res; /* Undefined V behavior */
9457 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9458 FLAG_X = FLAG_C = (res > 0x99) << 8;
9462 res = MASK_OUT_ABOVE_8(res);
9464 FLAG_V &= res; /* Undefined V behavior part II */
9465 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9468 m68ki_write_8(ea, res);
9472 M68KMAKE_OP(st, 8, ., d)
9478 M68KMAKE_OP(st, 8, ., .)
9480 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
9484 M68KMAKE_OP(sf, 8, ., d)
9490 M68KMAKE_OP(sf, 8, ., .)
9492 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
9496 M68KMAKE_OP(scc, 8, ., d)
9501 USE_CYCLES(CYC_SCC_R_TRUE);
9508 M68KMAKE_OP(scc, 8, ., .)
9510 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
9514 M68KMAKE_OP(stop, 0, ., .)
9518 uint new_sr = OPER_I_16();
9519 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9520 CPU_STOPPED |= STOP_LEVEL_STOP;
9521 m68ki_set_sr(new_sr);
9522 if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR])
9523 m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR];
9528 m68ki_exception_privilege_violation();
9532 M68KMAKE_OP(sub, 8, er, d)
9535 uint src = MASK_OUT_ABOVE_8(DY);
9536 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9537 uint res = dst - src;
9539 FLAG_N = NFLAG_8(res);
9540 FLAG_X = FLAG_C = CFLAG_8(res);
9541 FLAG_V = VFLAG_SUB_8(src, dst, res);
9542 FLAG_Z = MASK_OUT_ABOVE_8(res);
9544 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9548 M68KMAKE_OP(sub, 8, er, .)
9551 uint src = M68KMAKE_GET_OPER_AY_8;
9552 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9553 uint res = dst - src;
9555 FLAG_N = NFLAG_8(res);
9556 FLAG_X = FLAG_C = CFLAG_8(res);
9557 FLAG_V = VFLAG_SUB_8(src, dst, res);
9558 FLAG_Z = MASK_OUT_ABOVE_8(res);
9560 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9564 M68KMAKE_OP(sub, 16, er, d)
9567 uint src = MASK_OUT_ABOVE_16(DY);
9568 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9569 uint res = dst - src;
9571 FLAG_N = NFLAG_16(res);
9572 FLAG_X = FLAG_C = CFLAG_16(res);
9573 FLAG_V = VFLAG_SUB_16(src, dst, res);
9574 FLAG_Z = MASK_OUT_ABOVE_16(res);
9576 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9580 M68KMAKE_OP(sub, 16, er, a)
9583 uint src = MASK_OUT_ABOVE_16(AY);
9584 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9585 uint res = dst - src;
9587 FLAG_N = NFLAG_16(res);
9588 FLAG_X = FLAG_C = CFLAG_16(res);
9589 FLAG_V = VFLAG_SUB_16(src, dst, res);
9590 FLAG_Z = MASK_OUT_ABOVE_16(res);
9592 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9596 M68KMAKE_OP(sub, 16, er, .)
9599 uint src = M68KMAKE_GET_OPER_AY_16;
9600 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9601 uint res = dst - src;
9603 FLAG_N = NFLAG_16(res);
9604 FLAG_X = FLAG_C = CFLAG_16(res);
9605 FLAG_V = VFLAG_SUB_16(src, dst, res);
9606 FLAG_Z = MASK_OUT_ABOVE_16(res);
9608 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9612 M68KMAKE_OP(sub, 32, er, d)
9617 uint res = dst - src;
9619 FLAG_N = NFLAG_32(res);
9620 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9621 FLAG_V = VFLAG_SUB_32(src, dst, res);
9622 FLAG_Z = MASK_OUT_ABOVE_32(res);
9628 M68KMAKE_OP(sub, 32, er, a)
9633 uint res = dst - src;
9635 FLAG_N = NFLAG_32(res);
9636 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9637 FLAG_V = VFLAG_SUB_32(src, dst, res);
9638 FLAG_Z = MASK_OUT_ABOVE_32(res);
9644 M68KMAKE_OP(sub, 32, er, .)
9647 uint src = M68KMAKE_GET_OPER_AY_32;
9649 uint res = dst - src;
9651 FLAG_N = NFLAG_32(res);
9652 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9653 FLAG_V = VFLAG_SUB_32(src, dst, res);
9654 FLAG_Z = MASK_OUT_ABOVE_32(res);
9660 M68KMAKE_OP(sub, 8, re, .)
9662 uint ea = M68KMAKE_GET_EA_AY_8;
9663 uint src = MASK_OUT_ABOVE_8(DX);
9664 uint dst = m68ki_read_8(ea);
9665 uint res = dst - src;
9667 FLAG_N = NFLAG_8(res);
9668 FLAG_Z = MASK_OUT_ABOVE_8(res);
9669 FLAG_X = FLAG_C = CFLAG_8(res);
9670 FLAG_V = VFLAG_SUB_8(src, dst, res);
9672 m68ki_write_8(ea, FLAG_Z);
9676 M68KMAKE_OP(sub, 16, re, .)
9678 uint ea = M68KMAKE_GET_EA_AY_16;
9679 uint src = MASK_OUT_ABOVE_16(DX);
9680 uint dst = m68ki_read_16(ea);
9681 uint res = dst - src;
9683 FLAG_N = NFLAG_16(res);
9684 FLAG_Z = MASK_OUT_ABOVE_16(res);
9685 FLAG_X = FLAG_C = CFLAG_16(res);
9686 FLAG_V = VFLAG_SUB_16(src, dst, res);
9688 m68ki_write_16(ea, FLAG_Z);
9692 M68KMAKE_OP(sub, 32, re, .)
9694 uint ea = M68KMAKE_GET_EA_AY_32;
9696 uint dst = m68ki_read_32(ea);
9697 uint res = dst - src;
9699 FLAG_N = NFLAG_32(res);
9700 FLAG_Z = MASK_OUT_ABOVE_32(res);
9701 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9702 FLAG_V = VFLAG_SUB_32(src, dst, res);
9704 m68ki_write_32(ea, FLAG_Z);
9708 M68KMAKE_OP(suba, 16, ., d)
9712 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
9716 M68KMAKE_OP(suba, 16, ., a)
9720 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
9724 M68KMAKE_OP(suba, 16, ., .)
9727 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
9729 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9733 M68KMAKE_OP(suba, 32, ., d)
9737 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
9741 M68KMAKE_OP(suba, 32, ., a)
9745 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
9749 M68KMAKE_OP(suba, 32, ., .)
9751 uint src = M68KMAKE_GET_OPER_AY_32;
9754 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9758 M68KMAKE_OP(subi, 8, ., d)
9761 uint src = OPER_I_8();
9762 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9763 uint res = dst - src;
9765 FLAG_N = NFLAG_8(res);
9766 FLAG_Z = MASK_OUT_ABOVE_8(res);
9767 FLAG_X = FLAG_C = CFLAG_8(res);
9768 FLAG_V = VFLAG_SUB_8(src, dst, res);
9770 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9774 M68KMAKE_OP(subi, 8, ., .)
9776 uint src = OPER_I_8();
9777 uint ea = M68KMAKE_GET_EA_AY_8;
9778 uint dst = m68ki_read_8(ea);
9779 uint res = dst - src;
9781 FLAG_N = NFLAG_8(res);
9782 FLAG_Z = MASK_OUT_ABOVE_8(res);
9783 FLAG_X = FLAG_C = CFLAG_8(res);
9784 FLAG_V = VFLAG_SUB_8(src, dst, res);
9786 m68ki_write_8(ea, FLAG_Z);
9790 M68KMAKE_OP(subi, 16, ., d)
9793 uint src = OPER_I_16();
9794 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9795 uint res = dst - src;
9797 FLAG_N = NFLAG_16(res);
9798 FLAG_Z = MASK_OUT_ABOVE_16(res);
9799 FLAG_X = FLAG_C = CFLAG_16(res);
9800 FLAG_V = VFLAG_SUB_16(src, dst, res);
9802 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9806 M68KMAKE_OP(subi, 16, ., .)
9808 uint src = OPER_I_16();
9809 uint ea = M68KMAKE_GET_EA_AY_16;
9810 uint dst = m68ki_read_16(ea);
9811 uint res = dst - src;
9813 FLAG_N = NFLAG_16(res);
9814 FLAG_Z = MASK_OUT_ABOVE_16(res);
9815 FLAG_X = FLAG_C = CFLAG_16(res);
9816 FLAG_V = VFLAG_SUB_16(src, dst, res);
9818 m68ki_write_16(ea, FLAG_Z);
9822 M68KMAKE_OP(subi, 32, ., d)
9825 uint src = OPER_I_32();
9827 uint res = dst - src;
9829 FLAG_N = NFLAG_32(res);
9830 FLAG_Z = MASK_OUT_ABOVE_32(res);
9831 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9832 FLAG_V = VFLAG_SUB_32(src, dst, res);
9838 M68KMAKE_OP(subi, 32, ., .)
9840 uint src = OPER_I_32();
9841 uint ea = M68KMAKE_GET_EA_AY_32;
9842 uint dst = m68ki_read_32(ea);
9843 uint res = dst - src;
9845 FLAG_N = NFLAG_32(res);
9846 FLAG_Z = MASK_OUT_ABOVE_32(res);
9847 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9848 FLAG_V = VFLAG_SUB_32(src, dst, res);
9850 m68ki_write_32(ea, FLAG_Z);
9854 M68KMAKE_OP(subq, 8, ., d)
9857 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9858 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9859 uint res = dst - src;
9861 FLAG_N = NFLAG_8(res);
9862 FLAG_Z = MASK_OUT_ABOVE_8(res);
9863 FLAG_X = FLAG_C = CFLAG_8(res);
9864 FLAG_V = VFLAG_SUB_8(src, dst, res);
9866 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9870 M68KMAKE_OP(subq, 8, ., .)
9872 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9873 uint ea = M68KMAKE_GET_EA_AY_8;
9874 uint dst = m68ki_read_8(ea);
9875 uint res = dst - src;
9877 FLAG_N = NFLAG_8(res);
9878 FLAG_Z = MASK_OUT_ABOVE_8(res);
9879 FLAG_X = FLAG_C = CFLAG_8(res);
9880 FLAG_V = VFLAG_SUB_8(src, dst, res);
9882 m68ki_write_8(ea, FLAG_Z);
9886 M68KMAKE_OP(subq, 16, ., d)
9889 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9890 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9891 uint res = dst - src;
9893 FLAG_N = NFLAG_16(res);
9894 FLAG_Z = MASK_OUT_ABOVE_16(res);
9895 FLAG_X = FLAG_C = CFLAG_16(res);
9896 FLAG_V = VFLAG_SUB_16(src, dst, res);
9898 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9902 M68KMAKE_OP(subq, 16, ., a)
9906 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9910 M68KMAKE_OP(subq, 16, ., .)
9912 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9913 uint ea = M68KMAKE_GET_EA_AY_16;
9914 uint dst = m68ki_read_16(ea);
9915 uint res = dst - src;
9917 FLAG_N = NFLAG_16(res);
9918 FLAG_Z = MASK_OUT_ABOVE_16(res);
9919 FLAG_X = FLAG_C = CFLAG_16(res);
9920 FLAG_V = VFLAG_SUB_16(src, dst, res);
9922 m68ki_write_16(ea, FLAG_Z);
9926 M68KMAKE_OP(subq, 32, ., d)
9929 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9931 uint res = dst - src;
9933 FLAG_N = NFLAG_32(res);
9934 FLAG_Z = MASK_OUT_ABOVE_32(res);
9935 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9936 FLAG_V = VFLAG_SUB_32(src, dst, res);
9942 M68KMAKE_OP(subq, 32, ., a)
9946 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9950 M68KMAKE_OP(subq, 32, ., .)
9952 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9953 uint ea = M68KMAKE_GET_EA_AY_32;
9954 uint dst = m68ki_read_32(ea);
9955 uint res = dst - src;
9957 FLAG_N = NFLAG_32(res);
9958 FLAG_Z = MASK_OUT_ABOVE_32(res);
9959 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9960 FLAG_V = VFLAG_SUB_32(src, dst, res);
9962 m68ki_write_32(ea, FLAG_Z);
9966 M68KMAKE_OP(subx, 8, rr, .)
9969 uint src = MASK_OUT_ABOVE_8(DY);
9970 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9971 uint res = dst - src - XFLAG_AS_1();
9973 FLAG_N = NFLAG_8(res);
9974 FLAG_X = FLAG_C = CFLAG_8(res);
9975 FLAG_V = VFLAG_SUB_8(src, dst, res);
9977 res = MASK_OUT_ABOVE_8(res);
9980 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9984 M68KMAKE_OP(subx, 16, rr, .)
9987 uint src = MASK_OUT_ABOVE_16(DY);
9988 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9989 uint res = dst - src - XFLAG_AS_1();
9991 FLAG_N = NFLAG_16(res);
9992 FLAG_X = FLAG_C = CFLAG_16(res);
9993 FLAG_V = VFLAG_SUB_16(src, dst, res);
9995 res = MASK_OUT_ABOVE_16(res);
9998 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
10002 M68KMAKE_OP(subx, 32, rr, .)
10007 uint res = dst - src - XFLAG_AS_1();
10009 FLAG_N = NFLAG_32(res);
10010 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10011 FLAG_V = VFLAG_SUB_32(src, dst, res);
10013 res = MASK_OUT_ABOVE_32(res);
10020 M68KMAKE_OP(subx, 8, mm, ax7)
10022 uint src = OPER_AY_PD_8();
10023 uint ea = EA_A7_PD_8();
10024 uint dst = m68ki_read_8(ea);
10025 uint res = dst - src - XFLAG_AS_1();
10027 FLAG_N = NFLAG_8(res);
10028 FLAG_X = FLAG_C = CFLAG_8(res);
10029 FLAG_V = VFLAG_SUB_8(src, dst, res);
10031 res = MASK_OUT_ABOVE_8(res);
10034 m68ki_write_8(ea, res);
10038 M68KMAKE_OP(subx, 8, mm, ay7)
10040 uint src = OPER_A7_PD_8();
10041 uint ea = EA_AX_PD_8();
10042 uint dst = m68ki_read_8(ea);
10043 uint res = dst - src - XFLAG_AS_1();
10045 FLAG_N = NFLAG_8(res);
10046 FLAG_X = FLAG_C = CFLAG_8(res);
10047 FLAG_V = VFLAG_SUB_8(src, dst, res);
10049 res = MASK_OUT_ABOVE_8(res);
10052 m68ki_write_8(ea, res);
10056 M68KMAKE_OP(subx, 8, mm, axy7)
10058 uint src = OPER_A7_PD_8();
10059 uint ea = EA_A7_PD_8();
10060 uint dst = m68ki_read_8(ea);
10061 uint res = dst - src - XFLAG_AS_1();
10063 FLAG_N = NFLAG_8(res);
10064 FLAG_X = FLAG_C = CFLAG_8(res);
10065 FLAG_V = VFLAG_SUB_8(src, dst, res);
10067 res = MASK_OUT_ABOVE_8(res);
10070 m68ki_write_8(ea, res);
10074 M68KMAKE_OP(subx, 8, mm, .)
10076 uint src = OPER_AY_PD_8();
10077 uint ea = EA_AX_PD_8();
10078 uint dst = m68ki_read_8(ea);
10079 uint res = dst - src - XFLAG_AS_1();
10081 FLAG_N = NFLAG_8(res);
10082 FLAG_X = FLAG_C = CFLAG_8(res);
10083 FLAG_V = VFLAG_SUB_8(src, dst, res);
10085 res = MASK_OUT_ABOVE_8(res);
10088 m68ki_write_8(ea, res);
10092 M68KMAKE_OP(subx, 16, mm, .)
10094 uint src = OPER_AY_PD_16();
10095 uint ea = EA_AX_PD_16();
10096 uint dst = m68ki_read_16(ea);
10097 uint res = dst - src - XFLAG_AS_1();
10099 FLAG_N = NFLAG_16(res);
10100 FLAG_X = FLAG_C = CFLAG_16(res);
10101 FLAG_V = VFLAG_SUB_16(src, dst, res);
10103 res = MASK_OUT_ABOVE_16(res);
10106 m68ki_write_16(ea, res);
10110 M68KMAKE_OP(subx, 32, mm, .)
10112 uint src = OPER_AY_PD_32();
10113 uint ea = EA_AX_PD_32();
10114 uint dst = m68ki_read_32(ea);
10115 uint res = dst - src - XFLAG_AS_1();
10117 FLAG_N = NFLAG_32(res);
10118 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10119 FLAG_V = VFLAG_SUB_32(src, dst, res);
10121 res = MASK_OUT_ABOVE_32(res);
10124 m68ki_write_32(ea, res);
10128 M68KMAKE_OP(swap, 32, ., .)
10132 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
10133 *r_dst = (*r_dst>>16) | FLAG_Z;
10136 FLAG_N = NFLAG_32(*r_dst);
10137 FLAG_C = CFLAG_CLEAR;
10138 FLAG_V = VFLAG_CLEAR;
10142 M68KMAKE_OP(tas, 8, ., d)
10146 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
10147 FLAG_N = NFLAG_8(*r_dst);
10148 FLAG_V = VFLAG_CLEAR;
10149 FLAG_C = CFLAG_CLEAR;
10154 M68KMAKE_OP(tas, 8, ., .)
10156 uint ea = M68KMAKE_GET_EA_AY_8;
10157 uint dst = m68ki_read_8(ea);
10158 uint allow_writeback;
10161 FLAG_N = NFLAG_8(dst);
10162 FLAG_V = VFLAG_CLEAR;
10163 FLAG_C = CFLAG_CLEAR;
10165 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
10166 disabled in order to function properly. Some Amiga software may also rely
10167 on this, but only when accessing specific addresses so additional functionality
10169 allow_writeback = m68ki_tas_callback();
10171 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
10175 M68KMAKE_OP(trap, 0, ., .)
10177 /* Trap#n stacks exception frame type 0 */
10178 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
10182 M68KMAKE_OP(trapt, 0, ., .)
10184 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10186 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10189 m68ki_exception_illegal();
10193 M68KMAKE_OP(trapt, 16, ., .)
10195 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10197 REG_PC += 2; // JFF else stackframe & return addresses are incorrect
10198 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10201 m68ki_exception_illegal();
10205 M68KMAKE_OP(trapt, 32, ., .)
10207 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10209 REG_PC += 4; // JFF else stackframe & return addresses are incorrect
10210 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10213 m68ki_exception_illegal();
10217 M68KMAKE_OP(trapf, 0, ., .)
10219 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10223 m68ki_exception_illegal();
10227 M68KMAKE_OP(trapf, 16, ., .)
10229 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10234 m68ki_exception_illegal();
10238 M68KMAKE_OP(trapf, 32, ., .)
10240 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10245 m68ki_exception_illegal();
10249 M68KMAKE_OP(trapcc, 0, ., .)
10251 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10254 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10257 m68ki_exception_illegal();
10261 M68KMAKE_OP(trapcc, 16, ., .)
10263 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10265 REG_PC += 2; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10268 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10274 m68ki_exception_illegal();
10278 M68KMAKE_OP(trapcc, 32, ., .)
10280 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10282 REG_PC += 4; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10285 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10290 m68ki_exception_illegal();
10294 M68KMAKE_OP(trapv, 0, ., .)
10300 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10304 M68KMAKE_OP(tst, 8, ., d)
10306 uint res = MASK_OUT_ABOVE_8(DY);
10308 FLAG_N = NFLAG_8(res);
10310 FLAG_V = VFLAG_CLEAR;
10311 FLAG_C = CFLAG_CLEAR;
10315 M68KMAKE_OP(tst, 8, ., .)
10317 uint res = M68KMAKE_GET_OPER_AY_8;
10319 FLAG_N = NFLAG_8(res);
10321 FLAG_V = VFLAG_CLEAR;
10322 FLAG_C = CFLAG_CLEAR;
10326 M68KMAKE_OP(tst, 8, ., pcdi)
10328 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10330 uint res = OPER_PCDI_8();
10332 FLAG_N = NFLAG_8(res);
10334 FLAG_V = VFLAG_CLEAR;
10335 FLAG_C = CFLAG_CLEAR;
10338 m68ki_exception_illegal();
10342 M68KMAKE_OP(tst, 8, ., pcix)
10344 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10346 uint res = OPER_PCIX_8();
10348 FLAG_N = NFLAG_8(res);
10350 FLAG_V = VFLAG_CLEAR;
10351 FLAG_C = CFLAG_CLEAR;
10354 m68ki_exception_illegal();
10358 M68KMAKE_OP(tst, 8, ., i)
10360 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10362 uint res = OPER_I_8();
10364 FLAG_N = NFLAG_8(res);
10366 FLAG_V = VFLAG_CLEAR;
10367 FLAG_C = CFLAG_CLEAR;
10370 m68ki_exception_illegal();
10374 M68KMAKE_OP(tst, 16, ., d)
10376 uint res = MASK_OUT_ABOVE_16(DY);
10378 FLAG_N = NFLAG_16(res);
10380 FLAG_V = VFLAG_CLEAR;
10381 FLAG_C = CFLAG_CLEAR;
10385 M68KMAKE_OP(tst, 16, ., a)
10387 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10389 uint res = MAKE_INT_16(AY);
10391 FLAG_N = NFLAG_16(res);
10393 FLAG_V = VFLAG_CLEAR;
10394 FLAG_C = CFLAG_CLEAR;
10397 m68ki_exception_illegal();
10401 M68KMAKE_OP(tst, 16, ., .)
10403 uint res = M68KMAKE_GET_OPER_AY_16;
10405 FLAG_N = NFLAG_16(res);
10407 FLAG_V = VFLAG_CLEAR;
10408 FLAG_C = CFLAG_CLEAR;
10412 M68KMAKE_OP(tst, 16, ., pcdi)
10414 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10416 uint res = OPER_PCDI_16();
10418 FLAG_N = NFLAG_16(res);
10420 FLAG_V = VFLAG_CLEAR;
10421 FLAG_C = CFLAG_CLEAR;
10424 m68ki_exception_illegal();
10428 M68KMAKE_OP(tst, 16, ., pcix)
10430 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10432 uint res = OPER_PCIX_16();
10434 FLAG_N = NFLAG_16(res);
10436 FLAG_V = VFLAG_CLEAR;
10437 FLAG_C = CFLAG_CLEAR;
10440 m68ki_exception_illegal();
10444 M68KMAKE_OP(tst, 16, ., i)
10446 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10448 uint res = OPER_I_16();
10450 FLAG_N = NFLAG_16(res);
10452 FLAG_V = VFLAG_CLEAR;
10453 FLAG_C = CFLAG_CLEAR;
10456 m68ki_exception_illegal();
10460 M68KMAKE_OP(tst, 32, ., d)
10464 FLAG_N = NFLAG_32(res);
10466 FLAG_V = VFLAG_CLEAR;
10467 FLAG_C = CFLAG_CLEAR;
10471 M68KMAKE_OP(tst, 32, ., a)
10473 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10477 FLAG_N = NFLAG_32(res);
10479 FLAG_V = VFLAG_CLEAR;
10480 FLAG_C = CFLAG_CLEAR;
10483 m68ki_exception_illegal();
10487 M68KMAKE_OP(tst, 32, ., .)
10489 uint res = M68KMAKE_GET_OPER_AY_32;
10491 FLAG_N = NFLAG_32(res);
10493 FLAG_V = VFLAG_CLEAR;
10494 FLAG_C = CFLAG_CLEAR;
10498 M68KMAKE_OP(tst, 32, ., pcdi)
10500 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10502 uint res = OPER_PCDI_32();
10504 FLAG_N = NFLAG_32(res);
10506 FLAG_V = VFLAG_CLEAR;
10507 FLAG_C = CFLAG_CLEAR;
10510 m68ki_exception_illegal();
10514 M68KMAKE_OP(tst, 32, ., pcix)
10516 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10518 uint res = OPER_PCIX_32();
10520 FLAG_N = NFLAG_32(res);
10522 FLAG_V = VFLAG_CLEAR;
10523 FLAG_C = CFLAG_CLEAR;
10526 m68ki_exception_illegal();
10530 M68KMAKE_OP(tst, 32, ., i)
10532 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10534 uint res = OPER_I_32();
10536 FLAG_N = NFLAG_32(res);
10538 FLAG_V = VFLAG_CLEAR;
10539 FLAG_C = CFLAG_CLEAR;
10542 m68ki_exception_illegal();
10546 M68KMAKE_OP(unlk, 32, ., a7)
10548 REG_A[7] = m68ki_read_32(REG_A[7]);
10552 M68KMAKE_OP(unlk, 32, ., .)
10557 *r_dst = m68ki_pull_32();
10561 M68KMAKE_OP(unpk, 16, rr, .)
10563 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10565 /* Note: DX and DY are reversed in Motorola's docs */
10569 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
10572 m68ki_exception_illegal();
10576 M68KMAKE_OP(unpk, 16, mm, ax7)
10578 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10580 /* Note: AX and AY are reversed in Motorola's docs */
10581 uint src = OPER_AY_PD_8();
10584 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10585 ea_dst = EA_A7_PD_8();
10586 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10587 ea_dst = EA_A7_PD_8();
10588 m68ki_write_8(ea_dst, src & 0xff);
10591 m68ki_exception_illegal();
10595 M68KMAKE_OP(unpk, 16, mm, ay7)
10597 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10599 /* Note: AX and AY are reversed in Motorola's docs */
10600 uint src = OPER_A7_PD_8();
10603 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10604 ea_dst = EA_AX_PD_8();
10605 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10606 ea_dst = EA_AX_PD_8();
10607 m68ki_write_8(ea_dst, src & 0xff);
10610 m68ki_exception_illegal();
10614 M68KMAKE_OP(unpk, 16, mm, axy7)
10616 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10618 uint src = OPER_A7_PD_8();
10621 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10622 ea_dst = EA_A7_PD_8();
10623 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10624 ea_dst = EA_A7_PD_8();
10625 m68ki_write_8(ea_dst, src & 0xff);
10628 m68ki_exception_illegal();
10632 M68KMAKE_OP(unpk, 16, mm, .)
10634 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10636 /* Note: AX and AY are reversed in Motorola's docs */
10637 uint src = OPER_AY_PD_8();
10640 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10641 ea_dst = EA_AX_PD_8();
10642 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10643 ea_dst = EA_AX_PD_8();
10644 m68ki_write_8(ea_dst, src & 0xff);
10647 m68ki_exception_illegal();
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projects / pistorm / blob