6 /* ======================================================================== */
7 /* ========================= LICENSING & COPYRIGHT ======================== */
8 /* ======================================================================== */
13 * A portable Motorola M680x0 processor emulation engine.
14 * Copyright Karl Stenerud. All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a copy
17 * of this software and associated documentation files (the "Software"), to deal
18 * in the Software without restriction, including without limitation the rights
19 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
20 * copies of the Software, and to permit persons to whom the Software is
21 * furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice shall be included in
24 * all copies or substantial portions of the Software.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
28 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
29 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
30 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
31 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 /* Special thanks to Bart Trzynadlowski for his insight into the
36 * undocumented features of this chip:
38 * http://dynarec.com/~bart/files/68knotes.txt
42 /* Input file for m68kmake
43 * -----------------------
45 * All sections begin with 80 X's in a row followed by an end-of-line
47 * After this, m68kmake will expect to find one of the following section
49 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
50 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
51 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
52 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
53 * M68KMAKE_TABLE_BODY - the table itself
54 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
55 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
56 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
58 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
59 * M68KMAKE_TABLE_BODY must be second last in the file.
61 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
62 * primitives themselves. Each opcode handler begins with:
63 * M68KMAKE_OP(A, B, C, D)
65 * where A is the opcode handler name, B is the size of the operation,
66 * C denotes any special processing mode, and D denotes a specific
68 * For C and D where nothing is specified, use "."
71 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
72 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
73 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
75 * All opcode handler primitives end with a closing curly brace "}" at column 1
77 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
78 * and do not put a closing curly brace at column 1 unless it is
79 * marking the end of the handler!
81 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
82 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
83 * opcode handlers to handle variations in the opcode handler.
84 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
85 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
86 * be interpreted on instructions where the corresponding table entry
87 * specifies multiple effective addressing modes.
89 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
91 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
92 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
93 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
96 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
97 M68KMAKE_PROTOTYPE_HEADER
99 #ifndef M68KOPS__HEADER
100 #define M68KOPS__HEADER
102 /* ======================================================================== */
103 /* ============================ OPCODE HANDLERS =========================== */
104 /* ======================================================================== */
108 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
109 M68KMAKE_PROTOTYPE_FOOTER
112 /* Build the opcode handler table */
113 void m68ki_build_opcode_table(void);
115 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
116 extern unsigned char m68ki_cycles[][0x10000];
119 /* ======================================================================== */
120 /* ============================== END OF FILE ============================= */
121 /* ======================================================================== */
123 #endif /* M68KOPS__HEADER */
127 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
128 M68KMAKE_TABLE_HEADER
130 /* ======================================================================== */
131 /* ========================= OPCODE TABLE BUILDER ========================= */
132 /* ======================================================================== */
137 #define NUM_CPU_TYPES 5
139 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
140 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
142 /* This is used to generate the opcode handler jump table */
145 void (*opcode_handler)(void); /* handler function */
146 unsigned int mask; /* mask on opcode */
147 unsigned int match; /* what to match after masking */
148 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
149 } opcode_handler_struct;
152 /* Opcode handler table */
153 static const opcode_handler_struct m68k_opcode_handler_table[] =
155 /* function mask match 000 010 020 040 */
159 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
160 M68KMAKE_TABLE_FOOTER
162 {0, 0, 0, {0, 0, 0, 0, 0}}
166 /* Build the opcode handler jump table */
167 void m68ki_build_opcode_table(void)
169 const opcode_handler_struct *ostruct;
176 for(i = 0; i < 0x10000; i++)
178 /* default to illegal */
179 m68ki_instruction_jump_table[i] = m68k_op_illegal;
180 for(k=0;k<NUM_CPU_TYPES;k++)
181 m68ki_cycles[k][i] = 0;
184 ostruct = m68k_opcode_handler_table;
185 while(ostruct->mask != 0xff00)
187 for(i = 0;i < 0x10000;i++)
189 if((i & ostruct->mask) == ostruct->match)
191 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
192 for(k=0;k<NUM_CPU_TYPES;k++)
193 m68ki_cycles[k][i] = ostruct->cycles[k];
198 while(ostruct->mask == 0xff00)
200 for(i = 0;i <= 0xff;i++)
202 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
203 for(k=0;k<NUM_CPU_TYPES;k++)
204 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
208 while(ostruct->mask == 0xf1f8)
214 instr = ostruct->match | (i << 9) | j;
215 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
216 for(k=0;k<NUM_CPU_TYPES;k++)
217 m68ki_cycles[k][instr] = ostruct->cycles[k];
218 // For all shift operations with known shift distance (encoded in instruction word)
219 if((instr & 0xf000) == 0xe000 && (!(instr & 0x20)))
221 // On the 68000 and 68010 shift distance affect execution time.
222 // Add the cycle cost of shifting; 2 times the shift distance
223 cycle_cost = ((((i-1)&7)+1)<<1);
224 m68ki_cycles[0][instr] += cycle_cost;
225 m68ki_cycles[1][instr] += cycle_cost;
226 // On the 68020 shift distance does not affect execution time
227 m68ki_cycles[2][instr] += 0;
233 while(ostruct->mask == 0xfff0)
235 for(i = 0;i <= 0x0f;i++)
237 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
238 for(k=0;k<NUM_CPU_TYPES;k++)
239 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
243 while(ostruct->mask == 0xf1ff)
245 for(i = 0;i <= 0x07;i++)
247 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
248 for(k=0;k<NUM_CPU_TYPES;k++)
249 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
253 while(ostruct->mask == 0xfff8)
255 for(i = 0;i <= 0x07;i++)
257 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
258 for(k=0;k<NUM_CPU_TYPES;k++)
259 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
263 while(ostruct->mask == 0xffff)
265 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
266 for(k=0;k<NUM_CPU_TYPES;k++)
267 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
273 /* ======================================================================== */
274 /* ============================== END OF FILE ============================= */
275 /* ======================================================================== */
279 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
280 M68KMAKE_OPCODE_HANDLER_HEADER
284 extern void m68040_fpu_op0(void);
285 extern void m68040_fpu_op1(void);
286 extern void m68851_mmu_ops();
287 extern void m68881_ftrap();
289 /* ======================================================================== */
290 /* ========================= INSTRUCTION HANDLERS ========================= */
291 /* ======================================================================== */
295 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
296 M68KMAKE_OPCODE_HANDLER_FOOTER
298 /* ======================================================================== */
299 /* ============================== END OF FILE ============================= */
300 /* ======================================================================== */
304 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
307 The following table is arranged as follows:
309 name: Opcode mnemonic
313 spec proc: Special processing mode:
317 rr: register to register
319 er: effective address to register
320 re: register to effective address
321 dd: data register to data register
322 da: data register to address register
323 aa: address register to address register
324 cr: control register to register
325 rc: register to control register
326 toc: to condition code register
327 tos: to status register
328 tou: to user stack pointer
329 frc: from condition code register
330 frs: from status register
331 fru: from user stack pointer
332 * for move.x, the special processing mode is a specific
333 destination effective addressing mode.
335 spec ea: Specific effective addressing mode:
340 ai: address register indirect
341 pi: address register indirect with postincrement
342 pd: address register indirect with predecrement
343 di: address register indirect with displacement
344 ix: address register indirect with index
345 aw: absolute word address
346 al: absolute long address
347 pcdi: program counter relative with displacement
348 pcix: program counter relative with index
349 a7: register specified in instruction is A7
350 ax7: register field X of instruction is A7
351 ay7: register field Y of instruction is A7
352 axy7: register fields X and Y of instruction are A7
354 bit pattern: Pattern to recognize this opcode. "." means don't care.
356 allowed ea: List of allowed addressing modes:
358 A: address register indirect
359 +: ARI (address register indirect) with postincrement
360 -: ARI with predecrement
361 D: ARI with displacement
363 W: absolute word address
364 L: absolute long address
365 d: program counter indirect with displacement
366 x: program counter indirect with index
368 mode: CPU operating mode for each cpu type. U = user or supervisor,
369 S = supervisor only, "." = opcode not present.
371 cpu cycles: Base number of cycles required to execute this opcode on the
373 Use "." if CPU does not have this opcode.
377 spec spec allowed ea mode cpu cycles
378 name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 000 010 020 030 040 comments
379 ====== ==== ==== ==== ================ ========== = = = = = === === === === === =============
381 1010 0 . . 1010............ .......... U U U U U 4 4 4 4 4
382 1111 0 . . 1111............ .......... U U U U U 4 4 4 4 4
383 040fpu0 32 . . 11110010........ .......... . . . . U . . . . 0
384 040fpu1 32 . . 11110011........ .......... . . . . U . . . . 0
385 abcd 8 rr . 1100...100000... .......... U U U U U 6 6 4 4 4
386 abcd 8 mm ax7 1100111100001... .......... U U U U U 18 18 16 16 16
387 abcd 8 mm ay7 1100...100001111 .......... U U U U U 18 18 16 16 16
388 abcd 8 mm axy7 1100111100001111 .......... U U U U U 18 18 16 16 16
389 abcd 8 mm . 1100...100001... .......... U U U U U 18 18 16 16 16
390 add 8 er d 1101...000000... .......... U U U U U 4 4 2 2 2
391 add 8 er . 1101...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
392 add 16 er d 1101...001000... .......... U U U U U 4 4 2 2 2
393 add 16 er a 1101...001001... .......... U U U U U 4 4 2 2 2
394 add 16 er . 1101...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
395 add 32 er d 1101...010000... .......... U U U U U 6 6 2 2 2
396 add 32 er a 1101...010001... .......... U U U U U 6 6 2 2 2
397 add 32 er . 1101...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
398 add 8 re . 1101...100...... A+-DXWL... U U U U U 8 8 4 4 4
399 add 16 re . 1101...101...... A+-DXWL... U U U U U 8 8 4 4 4
400 add 32 re . 1101...110...... A+-DXWL... U U U U U 12 12 4 4 4
401 adda 16 . d 1101...011000... .......... U U U U U 8 8 2 2 2
402 adda 16 . a 1101...011001... .......... U U U U U 8 8 2 2 2
403 adda 16 . . 1101...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
404 adda 32 . d 1101...111000... .......... U U U U U 6 6 2 2 2
405 adda 32 . a 1101...111001... .......... U U U U U 6 6 2 2 2
406 adda 32 . . 1101...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
407 addi 8 . d 0000011000000... .......... U U U U U 8 8 2 2 2
408 addi 8 . . 0000011000...... A+-DXWL... U U U U U 12 12 4 4 4
409 addi 16 . d 0000011001000... .......... U U U U U 8 8 2 2 2
410 addi 16 . . 0000011001...... A+-DXWL... U U U U U 12 12 4 4 4
411 addi 32 . d 0000011010000... .......... U U U U U 16 14 2 2 2
412 addi 32 . . 0000011010...... A+-DXWL... U U U U U 20 20 4 4 4
413 addq 8 . d 0101...000000... .......... U U U U U 4 4 2 2 2
414 addq 8 . . 0101...000...... A+-DXWL... U U U U U 8 8 4 4 4
415 addq 16 . d 0101...001000... .......... U U U U U 4 4 2 2 2
416 addq 16 . a 0101...001001... .......... U U U U U 4 4 2 2 2
417 addq 16 . . 0101...001...... A+-DXWL... U U U U U 8 8 4 4 4
418 addq 32 . d 0101...010000... .......... U U U U U 8 8 2 2 2
419 addq 32 . a 0101...010001... .......... U U U U U 8 8 2 2 2
420 addq 32 . . 0101...010...... A+-DXWL... U U U U U 12 12 4 4 4
421 addx 8 rr . 1101...100000... .......... U U U U U 4 4 2 2 2
422 addx 16 rr . 1101...101000... .......... U U U U U 4 4 2 2 2
423 addx 32 rr . 1101...110000... .......... U U U U U 8 6 2 2 2
424 addx 8 mm ax7 1101111100001... .......... U U U U U 18 18 12 12 12
425 addx 8 mm ay7 1101...100001111 .......... U U U U U 18 18 12 12 12
426 addx 8 mm axy7 1101111100001111 .......... U U U U U 18 18 12 12 12
427 addx 8 mm . 1101...100001... .......... U U U U U 18 18 12 12 12
428 addx 16 mm . 1101...101001... .......... U U U U U 18 18 12 12 12
429 addx 32 mm . 1101...110001... .......... U U U U U 30 30 12 12 12
430 and 8 er d 1100...000000... .......... U U U U U 4 4 2 2 2
431 and 8 er . 1100...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
432 and 16 er d 1100...001000... .......... U U U U U 4 4 2 2 2
433 and 16 er . 1100...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
434 and 32 er d 1100...010000... .......... U U U U U 6 6 2 2 2
435 and 32 er . 1100...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
436 and 8 re . 1100...100...... A+-DXWL... U U U U U 8 8 4 4 4
437 and 16 re . 1100...101...... A+-DXWL... U U U U U 8 8 4 4 4
438 and 32 re . 1100...110...... A+-DXWL... U U U U U 12 12 4 4 4
439 andi 16 toc . 0000001000111100 .......... U U U U U 20 16 12 12 12
440 andi 16 tos . 0000001001111100 .......... S S S S S 20 16 12 12 12
441 andi 8 . d 0000001000000... .......... U U U U U 8 8 2 2 2
442 andi 8 . . 0000001000...... A+-DXWL... U U U U U 12 12 4 4 4
443 andi 16 . d 0000001001000... .......... U U U U U 8 8 2 2 2
444 andi 16 . . 0000001001...... A+-DXWL... U U U U U 12 12 4 4 4
445 andi 32 . d 0000001010000... .......... U U U U U 14 14 2 2 2
446 andi 32 . . 0000001010...... A+-DXWL... U U U U U 20 20 4 4 4
447 asr 8 s . 1110...000000... .......... U U U U U 6 6 6 6 6
448 asr 16 s . 1110...001000... .......... U U U U U 6 6 6 6 6
449 asr 32 s . 1110...010000... .......... U U U U U 8 8 6 6 6
450 asr 8 r . 1110...000100... .......... U U U U U 6 6 6 6 6
451 asr 16 r . 1110...001100... .......... U U U U U 6 6 6 6 6
452 asr 32 r . 1110...010100... .......... U U U U U 8 8 6 6 6
453 asr 16 . . 1110000011...... A+-DXWL... U U U U U 8 8 5 5 5
454 asl 8 s . 1110...100000... .......... U U U U U 6 6 8 8 8
455 asl 16 s . 1110...101000... .......... U U U U U 6 6 8 8 8
456 asl 32 s . 1110...110000... .......... U U U U U 8 8 8 8 8
457 asl 8 r . 1110...100100... .......... U U U U U 6 6 8 8 8
458 asl 16 r . 1110...101100... .......... U U U U U 6 6 8 8 8
459 asl 32 r . 1110...110100... .......... U U U U U 8 8 8 8 8
460 asl 16 . . 1110000111...... A+-DXWL... U U U U U 8 8 6 6 6
461 bcc 8 . . 0110............ .......... U U U U U 10 10 6 6 6
462 bcc 16 . . 0110....00000000 .......... U U U U U 10 10 6 6 6
463 bcc 32 . . 0110....11111111 .......... U U U U U 10 10 6 6 6
464 bchg 8 r . 0000...101...... A+-DXWL... U U U U U 8 8 4 4 4
465 bchg 32 r d 0000...101000... .......... U U U U U 8 8 4 4 4
466 bchg 8 s . 0000100001...... A+-DXWL... U U U U U 12 12 4 4 4
467 bchg 32 s d 0000100001000... .......... U U U U U 12 12 4 4 4
468 bclr 8 r . 0000...110...... A+-DXWL... U U U U U 8 10 4 4 4
469 bclr 32 r d 0000...110000... .......... U U U U U 10 10 4 4 4
470 bclr 8 s . 0000100010...... A+-DXWL... U U U U U 12 12 4 4 4
471 bclr 32 s d 0000100010000... .......... U U U U U 14 14 4 4 4
472 bfchg 32 . d 1110101011000... .......... . . U U U . . 12 12 12 timing not quite correct
473 bfchg 32 . . 1110101011...... A..DXWL... . . U U U . . 20 20 20
474 bfclr 32 . d 1110110011000... .......... . . U U U . . 12 12 12
475 bfclr 32 . . 1110110011...... A..DXWL... . . U U U . . 20 20 20
476 bfexts 32 . d 1110101111000... .......... . . U U U . . 8 8 8
477 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U . . 15 15 15
478 bfextu 32 . d 1110100111000... .......... . . U U U . . 8 8 8
479 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U . . 15 15 15
480 bfffo 32 . d 1110110111000... .......... . . U U U . . 18 18 18
481 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U . . 28 28 28
482 bfins 32 . d 1110111111000... .......... . . U U U . . 10 10 10
483 bfins 32 . . 1110111111...... A..DXWL... . . U U U . . 17 17 17
484 bfset 32 . d 1110111011000... .......... . . U U U . . 12 12 12
485 bfset 32 . . 1110111011...... A..DXWL... . . U U U . . 20 20 20
486 bftst 32 . d 1110100011000... .......... . . U U U . . 6 6 6
487 bftst 32 . . 1110100011...... A..DXWLdx. . . U U U . . 13 13 13
488 bkpt 0 . . 0100100001001... .......... . U U U U . 10 10 10 10
489 bra 8 . . 01100000........ .......... U U U U U 10 10 10 10 10
490 bra 16 . . 0110000000000000 .......... U U U U U 10 10 10 10 10
491 bra 32 . . 0110000011111111 .......... U U U U U 10 10 10 10 10
492 bset 32 r d 0000...111000... .......... U U U U U 8 8 4 4 4
493 bset 8 r . 0000...111...... A+-DXWL... U U U U U 8 8 4 4 4
494 bset 8 s . 0000100011...... A+-DXWL... U U U U U 12 12 4 4 4
495 bset 32 s d 0000100011000... .......... U U U U U 12 12 4 4 4
496 bsr 8 . . 01100001........ .......... U U U U U 18 18 7 7 7
497 bsr 16 . . 0110000100000000 .......... U U U U U 18 18 7 7 7
498 bsr 32 . . 0110000111111111 .......... U U U U U 18 18 7 7 7
499 btst 8 r . 0000...100...... A+-DXWLdxI U U U U U 4 4 4 4 4
500 btst 32 r d 0000...100000... .......... U U U U U 6 6 4 4 4
501 btst 8 s . 0000100000...... A+-DXWLdx. U U U U U 8 8 4 4 4
502 btst 32 s d 0000100000000... .......... U U U U U 10 10 4 4 4
503 callm 32 . . 0000011011...... A..DXWLdx. . . U U U . . 60 60 60 not properly emulated
504 cas 8 . . 0000101011...... A+-DXWL... . . U U U . . 12 12 12
505 cas 16 . . 0000110011...... A+-DXWL... . . U U U . . 12 12 12
506 cas 32 . . 0000111011...... A+-DXWL... . . U U U . . 12 12 12
507 cas2 16 . . 0000110011111100 .......... . . U U U . . 12 12 12
508 cas2 32 . . 0000111011111100 .......... . . U U U . . 12 12 12
509 chk 16 . d 0100...110000... .......... U U U U U 10 8 8 8 8
510 chk 16 . . 0100...110...... A+-DXWLdxI U U U U U 10 8 8 8 8
511 chk 32 . d 0100...100000... .......... . . U U U . . 8 8 8
512 chk 32 . . 0100...100...... A+-DXWLdxI . . U U U . . 8 8 8
513 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U . . 23 23 23
514 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U . . 23 23 23
515 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U . . 18 18 18
516 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U . . 23 23 23
517 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U . . 23 23 23
518 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U . . 18 18 18
519 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U . . 23 23 23
520 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U . . 23 23 23
521 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U . . 18 18 18
522 clr 8 . d 0100001000000... .......... U U U U U 4 4 2 2 2
523 clr 8 . . 0100001000...... A+-DXWL... U U U U U 8 4 4 4 4
524 clr 16 . d 0100001001000... .......... U U U U U 4 4 2 2 2
525 clr 16 . . 0100001001...... A+-DXWL... U U U U U 8 4 4 4 4
526 clr 32 . d 0100001010000... .......... U U U U U 6 6 2 2 2
527 clr 32 . . 0100001010...... A+-DXWL... U U U U U 12 6 4 4 4
528 cmp 8 . d 1011...000000... .......... U U U U U 4 4 2 2 2
529 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
530 cmp 16 . d 1011...001000... .......... U U U U U 4 4 2 2 2
531 cmp 16 . a 1011...001001... .......... U U U U U 4 4 2 2 2
532 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
533 cmp 32 . d 1011...010000... .......... U U U U U 6 6 2 2 2
534 cmp 32 . a 1011...010001... .......... U U U U U 6 6 2 2 2
535 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
536 cmpa 16 . d 1011...011000... .......... U U U U U 6 6 4 4 4
537 cmpa 16 . a 1011...011001... .......... U U U U U 6 6 4 4 4
538 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U 6 6 4 4 4
539 cmpa 32 . d 1011...111000... .......... U U U U U 6 6 4 4 4
540 cmpa 32 . a 1011...111001... .......... U U U U U 6 6 4 4 4
541 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U 6 6 4 4 4
542 cmpi 8 . d 0000110000000... .......... U U U U U 8 8 2 2 2
543 cmpi 8 . . 0000110000...... A+-DXWL... U U U U U 8 8 2 2 2
544 cmpi 8 . pcdi 0000110000111010 .......... . . U U U . . 7 7 7
545 cmpi 8 . pcix 0000110000111011 .......... . . U U U . . 9 9 9
546 cmpi 16 . d 0000110001000... .......... U U U U U 8 8 2 2 2
547 cmpi 16 . . 0000110001...... A+-DXWL... U U U U U 8 8 2 2 2
548 cmpi 16 . pcdi 0000110001111010 .......... . . U U U . . 7 7 7
549 cmpi 16 . pcix 0000110001111011 .......... . . U U U . . 9 9 9
550 cmpi 32 . d 0000110010000... .......... U U U U U 14 12 2 2 2
551 cmpi 32 . . 0000110010...... A+-DXWL... U U U U U 12 12 2 2 2
552 cmpi 32 . pcdi 0000110010111010 .......... . . U U U . . 7 7 7
553 cmpi 32 . pcix 0000110010111011 .......... . . U U U . . 9 9 9
554 cmpm 8 . ax7 1011111100001... .......... U U U U U 12 12 9 9 9
555 cmpm 8 . ay7 1011...100001111 .......... U U U U U 12 12 9 9 9
556 cmpm 8 . axy7 1011111100001111 .......... U U U U U 12 12 9 9 9
557 cmpm 8 . . 1011...100001... .......... U U U U U 12 12 9 9 9
558 cmpm 16 . . 1011...101001... .......... U U U U U 12 12 9 9 9
559 cmpm 32 . . 1011...110001... .......... U U U U U 20 20 9 9 9
560 cpbcc 32 . . 1111...01....... .......... . . U U . . . 4 4 . unemulated
561 cpdbcc 32 . . 1111...001001... .......... . . U U . . . 4 4 . unemulated
562 cpgen 32 . . 1111...000...... .......... . . U U . . . 4 4 . unemulated
563 cpscc 32 . . 1111...001...... .......... . . U U . . . 4 4 . unemulated
564 cptrapcc 32 . . 1111...001111... .......... . . U U . . . 4 4 . unemulated
565 ftrapcc 32 . . 1111001001111... .......... . . U U . . . 4 4 .
566 dbt 16 . . 0101000011001... .......... U U U U U 12 12 6 6 6
567 dbf 16 . . 0101000111001... .......... U U U U U 12 12 6 6 6
568 dbcc 16 . . 0101....11001... .......... U U U U U 12 12 6 6 6
569 divs 16 . d 1000...111000... .......... U U U U U 158 122 56 56 56
570 divs 16 . . 1000...111...... A+-DXWLdxI U U U U U 158 122 56 56 56
571 divu 16 . d 1000...011000... .......... U U U U U 140 108 44 44 44
572 divu 16 . . 1000...011...... A+-DXWLdxI U U U U U 140 108 44 44 44
573 divl 32 . d 0100110001000... .......... . . U U U . . 84 84 84
574 divl 32 . . 0100110001...... A+-DXWLdxI . . U U U . . 84 84 84
575 eor 8 . d 1011...100000... .......... U U U U U 4 4 2 2 2
576 eor 8 . . 1011...100...... A+-DXWL... U U U U U 8 8 4 4 4
577 eor 16 . d 1011...101000... .......... U U U U U 4 4 2 2 2
578 eor 16 . . 1011...101...... A+-DXWL... U U U U U 8 8 4 4 4
579 eor 32 . d 1011...110000... .......... U U U U U 8 6 2 2 2
580 eor 32 . . 1011...110...... A+-DXWL... U U U U U 12 12 4 4 4
581 eori 16 toc . 0000101000111100 .......... U U U U U 20 16 12 12 12
582 eori 16 tos . 0000101001111100 .......... S S S S S 20 16 12 12 12
583 eori 8 . d 0000101000000... .......... U U U U U 8 8 2 2 2
584 eori 8 . . 0000101000...... A+-DXWL... U U U U U 12 12 4 4 4
585 eori 16 . d 0000101001000... .......... U U U U U 8 8 2 2 2
586 eori 16 . . 0000101001...... A+-DXWL... U U U U U 12 12 4 4 4
587 eori 32 . d 0000101010000... .......... U U U U U 16 14 2 2 2
588 eori 32 . . 0000101010...... A+-DXWL... U U U U U 20 20 4 4 4
589 exg 32 dd . 1100...101000... .......... U U U U U 6 6 2 2 2
590 exg 32 aa . 1100...101001... .......... U U U U U 6 6 2 2 2
591 exg 32 da . 1100...110001... .......... U U U U U 6 6 2 2 2
592 ext 16 . . 0100100010000... .......... U U U U U 4 4 4 4 4
593 ext 32 . . 0100100011000... .......... U U U U U 4 4 4 4 4
594 extb 32 . . 0100100111000... .......... . . U U U . . 4 4 4
595 illegal 0 . . 0100101011111100 .......... U U U U U 4 4 4 4 4
596 jmp 32 . . 0100111011...... A..DXWLdx. U U U U U 4 4 0 0 0
597 jsr 32 . . 0100111010...... A..DXWLdx. U U U U U 12 12 0 0 0
598 lea 32 . . 0100...111...... A..DXWLdx. U U U U U 0 0 2 2 2
599 link 16 . a7 0100111001010111 .......... U U U U U 16 16 5 5 5
600 link 16 . . 0100111001010... .......... U U U U U 16 16 5 5 5
601 link 32 . a7 0100100000001111 .......... . . U U U . . 6 6 6
602 link 32 . . 0100100000001... .......... . . U U U . . 6 6 6
603 lsr 8 s . 1110...000001... .......... U U U U U 6 6 4 4 4
604 lsr 16 s . 1110...001001... .......... U U U U U 6 6 4 4 4
605 lsr 32 s . 1110...010001... .......... U U U U U 8 8 4 4 4
606 lsr 8 r . 1110...000101... .......... U U U U U 6 6 6 6 6
607 lsr 16 r . 1110...001101... .......... U U U U U 6 6 6 6 6
608 lsr 32 r . 1110...010101... .......... U U U U U 8 8 6 6 6
609 lsr 16 . . 1110001011...... A+-DXWL... U U U U U 8 8 5 5 5
610 lsl 8 s . 1110...100001... .......... U U U U U 6 6 4 4 4
611 lsl 16 s . 1110...101001... .......... U U U U U 6 6 4 4 4
612 lsl 32 s . 1110...110001... .......... U U U U U 8 8 4 4 4
613 lsl 8 r . 1110...100101... .......... U U U U U 6 6 6 6 6
614 lsl 16 r . 1110...101101... .......... U U U U U 6 6 6 6 6
615 lsl 32 r . 1110...110101... .......... U U U U U 8 8 6 6 6
616 lsl 16 . . 1110001111...... A+-DXWL... U U U U U 8 8 5 5 5
617 move 8 d d 0001...000000... .......... U U U U U 4 4 2 2 2
618 move 8 d . 0001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
619 move 8 ai d 0001...010000... .......... U U U U U 8 8 4 4 4
620 move 8 ai . 0001...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
621 move 8 pi d 0001...011000... .......... U U U U U 8 8 4 4 4
622 move 8 pi . 0001...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
623 move 8 pi7 d 0001111011000... .......... U U U U U 8 8 4 4 4
624 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U 8 8 4 4 4
625 move 8 pd d 0001...100000... .......... U U U U U 8 8 5 5 5
626 move 8 pd . 0001...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
627 move 8 pd7 d 0001111100000... .......... U U U U U 8 8 5 5 5
628 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U 8 8 5 5 5
629 move 8 di d 0001...101000... .......... U U U U U 12 12 5 5 5
630 move 8 di . 0001...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
631 move 8 ix d 0001...110000... .......... U U U U U 14 14 7 7 7
632 move 8 ix . 0001...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
633 move 8 aw d 0001000111000... .......... U U U U U 12 12 4 4 4
634 move 8 aw . 0001000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
635 move 8 al d 0001001111000... .......... U U U U U 16 16 6 6 6
636 move 8 al . 0001001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
637 move 16 d d 0011...000000... .......... U U U U U 4 4 2 2 2
638 move 16 d a 0011...000001... .......... U U U U U 4 4 2 2 2
639 move 16 d . 0011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
640 move 16 ai d 0011...010000... .......... U U U U U 8 8 4 4 4
641 move 16 ai a 0011...010001... .......... U U U U U 8 8 4 4 4
642 move 16 ai . 0011...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
643 move 16 pi d 0011...011000... .......... U U U U U 8 8 4 4 4
644 move 16 pi a 0011...011001... .......... U U U U U 8 8 4 4 4
645 move 16 pi . 0011...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
646 move 16 pd d 0011...100000... .......... U U U U U 8 8 5 5 5
647 move 16 pd a 0011...100001... .......... U U U U U 8 8 5 5 5
648 move 16 pd . 0011...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
649 move 16 di d 0011...101000... .......... U U U U U 12 12 5 5 5
650 move 16 di a 0011...101001... .......... U U U U U 12 12 5 5 5
651 move 16 di . 0011...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
652 move 16 ix d 0011...110000... .......... U U U U U 14 14 7 7 7
653 move 16 ix a 0011...110001... .......... U U U U U 14 14 7 7 7
654 move 16 ix . 0011...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
655 move 16 aw d 0011000111000... .......... U U U U U 12 12 4 4 4
656 move 16 aw a 0011000111001... .......... U U U U U 12 12 4 4 4
657 move 16 aw . 0011000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
658 move 16 al d 0011001111000... .......... U U U U U 16 16 6 6 6
659 move 16 al a 0011001111001... .......... U U U U U 16 16 6 6 6
660 move 16 al . 0011001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
661 move 32 d d 0010...000000... .......... U U U U U 4 4 2 2 2
662 move 32 d a 0010...000001... .......... U U U U U 4 4 2 2 2
663 move 32 d . 0010...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
664 move 32 ai d 0010...010000... .......... U U U U U 12 12 4 4 4
665 move 32 ai a 0010...010001... .......... U U U U U 12 12 4 4 4
666 move 32 ai . 0010...010...... A+-DXWLdxI U U U U U 12 12 4 4 4
667 move 32 pi d 0010...011000... .......... U U U U U 12 12 4 4 4
668 move 32 pi a 0010...011001... .......... U U U U U 12 12 4 4 4
669 move 32 pi . 0010...011...... A+-DXWLdxI U U U U U 12 12 4 4 4
670 move 32 pd d 0010...100000... .......... U U U U U 12 14 5 5 5
671 move 32 pd a 0010...100001... .......... U U U U U 12 14 5 5 5
672 move 32 pd . 0010...100...... A+-DXWLdxI U U U U U 12 14 5 5 5
673 move 32 di d 0010...101000... .......... U U U U U 16 16 5 5 5
674 move 32 di a 0010...101001... .......... U U U U U 16 16 5 5 5
675 move 32 di . 0010...101...... A+-DXWLdxI U U U U U 16 16 5 5 5
676 move 32 ix d 0010...110000... .......... U U U U U 18 18 7 7 7
677 move 32 ix a 0010...110001... .......... U U U U U 18 18 7 7 7
678 move 32 ix . 0010...110...... A+-DXWLdxI U U U U U 18 18 7 7 7
679 move 32 aw d 0010000111000... .......... U U U U U 16 16 4 4 4
680 move 32 aw a 0010000111001... .......... U U U U U 16 16 4 4 4
681 move 32 aw . 0010000111...... A+-DXWLdxI U U U U U 16 16 4 4 4
682 move 32 al d 0010001111000... .......... U U U U U 20 20 6 6 6
683 move 32 al a 0010001111001... .......... U U U U U 20 20 6 6 6
684 move 32 al . 0010001111...... A+-DXWLdxI U U U U U 20 20 6 6 6
685 movea 16 . d 0011...001000... .......... U U U U U 4 4 2 2 2
686 movea 16 . a 0011...001001... .......... U U U U U 4 4 2 2 2
687 movea 16 . . 0011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
688 movea 32 . d 0010...001000... .......... U U U U U 4 4 2 2 2
689 movea 32 . a 0010...001001... .......... U U U U U 4 4 2 2 2
690 movea 32 . . 0010...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
691 move 16 frc d 0100001011000... .......... . U U U U . 4 4 4 4
692 move 16 frc . 0100001011...... A+-DXWL... . U U U U . 8 4 4 4
693 move 16 toc d 0100010011000... .......... U U U U U 12 12 4 4 4
694 move 16 toc . 0100010011...... A+-DXWLdxI U U U U U 12 12 4 4 4
695 move 16 frs d 0100000011000... .......... U S S S S 6 4 8 8 8 U only for 000
696 move 16 frs . 0100000011...... A+-DXWL... U S S S S 8 8 8 8 8 U only for 000
697 move 16 tos d 0100011011000... .......... S S S S S 12 12 8 8 8
698 move 16 tos . 0100011011...... A+-DXWLdxI S S S S S 12 12 8 8 8
699 move 32 fru . 0100111001101... .......... S S S S S 4 6 2 2 2
700 move 32 tou . 0100111001100... .......... S S S S S 4 6 2 2 2
701 movec 32 cr . 0100111001111010 .......... . S S S S . 12 6 6 6
702 movec 32 rc . 0100111001111011 .......... . S S S S . 10 12 12 12
703 movem 16 re pd 0100100010100... .......... U U U U U 8 8 4 4 4
704 movem 16 re . 0100100010...... A..DXWL... U U U U U 8 8 4 4 4
705 movem 32 re pd 0100100011100... .......... U U U U U 8 8 4 4 4
706 movem 32 re . 0100100011...... A..DXWL... U U U U U 8 8 4 4 4
707 movem 16 er pi 0100110010011... .......... U U U U U 12 12 8 8 8
708 movem 16 er pcdi 0100110010111010 .......... U U U U U 16 16 9 9 9
709 movem 16 er pcix 0100110010111011 .......... U U U U U 18 18 11 11 11
710 movem 16 er . 0100110010...... A..DXWL... U U U U U 12 12 8 8 8
711 movem 32 er pi 0100110011011... .......... U U U U U 12 12 8 8 8
712 movem 32 er pcdi 0100110011111010 .......... U U U U U 16 16 9 9 9
713 movem 32 er pcix 0100110011111011 .......... U U U U U 18 18 11 11 11
714 movem 32 er . 0100110011...... A..DXWL... U U U U U 12 12 8 8 8
715 movep 16 er . 0000...100001... .......... U U U U U 16 16 12 12 12
716 movep 32 er . 0000...101001... .......... U U U U U 24 24 18 18 18
717 movep 16 re . 0000...110001... .......... U U U U U 16 16 11 11 11
718 movep 32 re . 0000...111001... .......... U U U U U 24 24 17 17 17
719 moveq 32 . . 0111...0........ .......... U U U U U 4 4 2 2 2
720 moves 8 . . 0000111000...... A+-DXWL... . S S S S . 14 5 5 5
721 moves 16 . . 0000111001...... A+-DXWL... . S S S S . 14 5 5 5
722 moves 32 . . 0000111010...... A+-DXWL... . S S S S . 16 5 5 5
723 move16 32 . . 1111011000100... .......... . . . . U . . . . 4 TODO: correct timing
724 muls 16 . d 1100...111000... .......... U U U U U 54 32 27 27 27
725 muls 16 . . 1100...111...... A+-DXWLdxI U U U U U 54 32 27 27 27
726 mulu 16 . d 1100...011000... .......... U U U U U 54 30 27 27 27
727 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U 54 30 27 27 27
728 mull 32 . d 0100110000000... .......... . . U U U . . 43 43 43
729 mull 32 . . 0100110000...... A+-DXWLdxI . . U U U . . 43 43 43
730 nbcd 8 . d 0100100000000... .......... U U U U U 6 6 6 6 6
731 nbcd 8 . . 0100100000...... A+-DXWL... U U U U U 8 8 6 6 6
732 neg 8 . d 0100010000000... .......... U U U U U 4 4 2 2 2
733 neg 8 . . 0100010000...... A+-DXWL... U U U U U 8 8 4 4 4
734 neg 16 . d 0100010001000... .......... U U U U U 4 4 2 2 2
735 neg 16 . . 0100010001...... A+-DXWL... U U U U U 8 8 4 4 4
736 neg 32 . d 0100010010000... .......... U U U U U 6 6 2 2 2
737 neg 32 . . 0100010010...... A+-DXWL... U U U U U 12 12 4 4 4
738 negx 8 . d 0100000000000... .......... U U U U U 4 4 2 2 2
739 negx 8 . . 0100000000...... A+-DXWL... U U U U U 8 8 4 4 4
740 negx 16 . d 0100000001000... .......... U U U U U 4 4 2 2 2
741 negx 16 . . 0100000001...... A+-DXWL... U U U U U 8 8 4 4 4
742 negx 32 . d 0100000010000... .......... U U U U U 6 6 2 2 2
743 negx 32 . . 0100000010...... A+-DXWL... U U U U U 12 12 4 4 4
744 nop 0 . . 0100111001110001 .......... U U U U U 4 4 2 2 2
745 not 8 . d 0100011000000... .......... U U U U U 4 4 2 2 2
746 not 8 . . 0100011000...... A+-DXWL... U U U U U 8 8 4 4 4
747 not 16 . d 0100011001000... .......... U U U U U 4 4 2 2 2
748 not 16 . . 0100011001...... A+-DXWL... U U U U U 8 8 4 4 4
749 not 32 . d 0100011010000... .......... U U U U U 6 6 2 2 2
750 not 32 . . 0100011010...... A+-DXWL... U U U U U 12 12 4 4 4
751 or 8 er d 1000...000000... .......... U U U U U 4 4 2 2 2
752 or 8 er . 1000...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
753 or 16 er d 1000...001000... .......... U U U U U 4 4 2 2 2
754 or 16 er . 1000...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
755 or 32 er d 1000...010000... .......... U U U U U 6 6 2 2 2
756 or 32 er . 1000...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
757 or 8 re . 1000...100...... A+-DXWL... U U U U U 8 8 4 4 4
758 or 16 re . 1000...101...... A+-DXWL... U U U U U 8 8 4 4 4
759 or 32 re . 1000...110...... A+-DXWL... U U U U U 12 12 4 4 4
760 ori 16 toc . 0000000000111100 .......... U U U U U 20 16 12 12 12
761 ori 16 tos . 0000000001111100 .......... S S S S S 20 16 12 12 12
762 ori 8 . d 0000000000000... .......... U U U U U 8 8 2 2 2
763 ori 8 . . 0000000000...... A+-DXWL... U U U U U 12 12 4 4 4
764 ori 16 . d 0000000001000... .......... U U U U U 8 8 2 2 2
765 ori 16 . . 0000000001...... A+-DXWL... U U U U U 12 12 4 4 4
766 ori 32 . d 0000000010000... .......... U U U U U 16 14 2 2 2
767 ori 32 . . 0000000010...... A+-DXWL... U U U U U 20 20 4 4 4
768 pack 16 rr . 1000...101000... .......... . . U U U . . 6 6 6
769 pack 16 mm ax7 1000111101001... .......... . . U U U . . 13 13 13
770 pack 16 mm ay7 1000...101001111 .......... . . U U U . . 13 13 13
771 pack 16 mm axy7 1000111101001111 .......... . . U U U . . 13 13 13
772 pack 16 mm . 1000...101001... .......... . . U U U . . 13 13 13
773 pea 32 . . 0100100001...... A..DXWLdx. U U U U U 6 6 5 5 5
774 pflusha 32 . . 1111010100011... .......... . . . . S . . . . 4 TODO: correct timing
775 pflushan 32 . . 1111010100010... .......... . . . . S . . . . 4 TODO: correct timing
776 pmmu 32 . . 1111000......... .......... . . S S S . . 8 8 8
777 reset 0 . . 0100111001110000 .......... S S S S S 0 0 0 0 0
778 ror 8 s . 1110...000011... .......... U U U U U 6 6 8 8 8
779 ror 16 s . 1110...001011... .......... U U U U U 6 6 8 8 8
780 ror 32 s . 1110...010011... .......... U U U U U 8 8 8 8 8
781 ror 8 r . 1110...000111... .......... U U U U U 6 6 8 8 8
782 ror 16 r . 1110...001111... .......... U U U U U 6 6 8 8 8
783 ror 32 r . 1110...010111... .......... U U U U U 8 8 8 8 8
784 ror 16 . . 1110011011...... A+-DXWL... U U U U U 8 8 7 7 7
785 rol 8 s . 1110...100011... .......... U U U U U 6 6 8 8 8
786 rol 16 s . 1110...101011... .......... U U U U U 6 6 8 8 8
787 rol 32 s . 1110...110011... .......... U U U U U 8 8 8 8 8
788 rol 8 r . 1110...100111... .......... U U U U U 6 6 8 8 8
789 rol 16 r . 1110...101111... .......... U U U U U 6 6 8 8 8
790 rol 32 r . 1110...110111... .......... U U U U U 8 8 8 8 8
791 rol 16 . . 1110011111...... A+-DXWL... U U U U U 8 8 7 7 7
792 roxr 8 s . 1110...000010... .......... U U U U U 6 6 12 12 12
793 roxr 16 s . 1110...001010... .......... U U U U U 6 6 12 12 12
794 roxr 32 s . 1110...010010... .......... U U U U U 8 8 12 12 12
795 roxr 8 r . 1110...000110... .......... U U U U U 6 6 12 12 12
796 roxr 16 r . 1110...001110... .......... U U U U U 6 6 12 12 12
797 roxr 32 r . 1110...010110... .......... U U U U U 8 8 12 12 12
798 roxr 16 . . 1110010011...... A+-DXWL... U U U U U 8 8 5 5 5
799 roxl 8 s . 1110...100010... .......... U U U U U 6 6 12 12 12
800 roxl 16 s . 1110...101010... .......... U U U U U 6 6 12 12 12
801 roxl 32 s . 1110...110010... .......... U U U U U 8 8 12 12 12
802 roxl 8 r . 1110...100110... .......... U U U U U 6 6 12 12 12
803 roxl 16 r . 1110...101110... .......... U U U U U 6 6 12 12 12
804 roxl 32 r . 1110...110110... .......... U U U U U 8 8 12 12 12
805 roxl 16 . . 1110010111...... A+-DXWL... U U U U U 8 8 5 5 5
806 rtd 32 . . 0100111001110100 .......... . U U U U . 16 10 10 10
807 rte 32 . . 0100111001110011 .......... S S S S S 20 24 20 20 20 bus fault not emulated
808 rtm 32 . . 000001101100.... .......... . . U U U . . 19 19 19 not properly emulated
809 rtr 32 . . 0100111001110111 .......... U U U U U 20 20 14 14 14
810 rts 32 . . 0100111001110101 .......... U U U U U 16 16 10 10 10
811 sbcd 8 rr . 1000...100000... .......... U U U U U 6 6 4 4 4
812 sbcd 8 mm ax7 1000111100001... .......... U U U U U 18 18 16 16 16
813 sbcd 8 mm ay7 1000...100001111 .......... U U U U U 18 18 16 16 16
814 sbcd 8 mm axy7 1000111100001111 .......... U U U U U 18 18 16 16 16
815 sbcd 8 mm . 1000...100001... .......... U U U U U 18 18 16 16 16
816 st 8 . d 0101000011000... .......... U U U U U 6 4 4 4 4
817 st 8 . . 0101000011...... A+-DXWL... U U U U U 8 8 6 6 6
818 sf 8 . d 0101000111000... .......... U U U U U 4 4 4 4 4
819 sf 8 . . 0101000111...... A+-DXWL... U U U U U 8 8 6 6 6
820 scc 8 . d 0101....11000... .......... U U U U U 4 4 4 4 4
821 scc 8 . . 0101....11...... A+-DXWL... U U U U U 8 8 6 6 6
822 stop 0 . . 0100111001110010 .......... S S S S S 4 4 8 8 8
823 sub 8 er d 1001...000000... .......... U U U U U 4 4 2 2 2
824 sub 8 er . 1001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
825 sub 16 er d 1001...001000... .......... U U U U U 4 4 2 2 2
826 sub 16 er a 1001...001001... .......... U U U U U 4 4 2 2 2
827 sub 16 er . 1001...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
828 sub 32 er d 1001...010000... .......... U U U U U 6 6 2 2 2
829 sub 32 er a 1001...010001... .......... U U U U U 6 6 2 2 2
830 sub 32 er . 1001...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
831 sub 8 re . 1001...100...... A+-DXWL... U U U U U 8 8 4 4 4
832 sub 16 re . 1001...101...... A+-DXWL... U U U U U 8 8 4 4 4
833 sub 32 re . 1001...110...... A+-DXWL... U U U U U 12 12 4 4 4
834 suba 16 . d 1001...011000... .......... U U U U U 8 8 2 2 2
835 suba 16 . a 1001...011001... .......... U U U U U 8 8 2 2 2
836 suba 16 . . 1001...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
837 suba 32 . d 1001...111000... .......... U U U U U 6 6 2 2 2
838 suba 32 . a 1001...111001... .......... U U U U U 6 6 2 2 2
839 suba 32 . . 1001...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
840 subi 8 . d 0000010000000... .......... U U U U U 8 8 2 2 2
841 subi 8 . . 0000010000...... A+-DXWL... U U U U U 12 12 4 4 4
842 subi 16 . d 0000010001000... .......... U U U U U 8 8 2 2 2
843 subi 16 . . 0000010001...... A+-DXWL... U U U U U 12 12 4 4 4
844 subi 32 . d 0000010010000... .......... U U U U U 16 14 2 2 2
845 subi 32 . . 0000010010...... A+-DXWL... U U U U U 20 20 4 4 4
846 subq 8 . d 0101...100000... .......... U U U U U 4 4 2 2 2
847 subq 8 . . 0101...100...... A+-DXWL... U U U U U 8 8 4 4 4
848 subq 16 . d 0101...101000... .......... U U U U U 4 4 2 2 2
849 subq 16 . a 0101...101001... .......... U U U U U 8 4 2 2 2
850 subq 16 . . 0101...101...... A+-DXWL... U U U U U 8 8 4 4 4
851 subq 32 . d 0101...110000... .......... U U U U U 8 8 2 2 2
852 subq 32 . a 0101...110001... .......... U U U U U 8 8 2 2 2
853 subq 32 . . 0101...110...... A+-DXWL... U U U U U 12 12 4 4 4
854 subx 8 rr . 1001...100000... .......... U U U U U 4 4 2 2 2
855 subx 16 rr . 1001...101000... .......... U U U U U 4 4 2 2 2
856 subx 32 rr . 1001...110000... .......... U U U U U 8 6 2 2 2
857 subx 8 mm ax7 1001111100001... .......... U U U U U 18 18 12 12 12
858 subx 8 mm ay7 1001...100001111 .......... U U U U U 18 18 12 12 12
859 subx 8 mm axy7 1001111100001111 .......... U U U U U 18 18 12 12 12
860 subx 8 mm . 1001...100001... .......... U U U U U 18 18 12 12 12
861 subx 16 mm . 1001...101001... .......... U U U U U 18 18 12 12 12
862 subx 32 mm . 1001...110001... .......... U U U U U 30 30 12 12 12
863 swap 32 . . 0100100001000... .......... U U U U U 4 4 4 4 4
864 tas 8 . d 0100101011000... .......... U U U U U 4 4 4 4 4
865 tas 8 . . 0100101011...... A+-DXWL... U U U U U 14 14 12 12 12
866 trap 0 . . 010011100100.... .......... U U U U U 4 4 4 4 4
867 trapt 0 . . 0101000011111100 .......... . . U U U . . 4 4 4
868 trapt 16 . . 0101000011111010 .......... . . U U U . . 6 6 6
869 trapt 32 . . 0101000011111011 .......... . . U U U . . 8 8 8
870 trapf 0 . . 0101000111111100 .......... . . U U U . . 4 4 4
871 trapf 16 . . 0101000111111010 .......... . . U U U . . 6 6 6
872 trapf 32 . . 0101000111111011 .......... . . U U U . . 8 8 8
873 trapcc 0 . . 0101....11111100 .......... . . U U U . . 4 4 4
874 trapcc 16 . . 0101....11111010 .......... . . U U U . . 6 6 6
875 trapcc 32 . . 0101....11111011 .......... . . U U U . . 8 8 8
876 trapv 0 . . 0100111001110110 .......... U U U U U 4 4 4 4 4
877 tst 8 . d 0100101000000... .......... U U U U U 4 4 2 2 2
878 tst 8 . . 0100101000...... A+-DXWL... U U U U U 4 4 2 2 2
879 tst 8 . pcdi 0100101000111010 .......... . . U U U . . 7 7 7
880 tst 8 . pcix 0100101000111011 .......... . . U U U . . 9 9 9
881 tst 8 . i 0100101000111100 .......... . . U U U . . 6 6 6
882 tst 16 . d 0100101001000... .......... U U U U U 4 4 2 2 2
883 tst 16 . a 0100101001001... .......... . . U U U . . 2 2 2
884 tst 16 . . 0100101001...... A+-DXWL... U U U U U 4 4 2 2 2
885 tst 16 . pcdi 0100101001111010 .......... . . U U U . . 7 7 7
886 tst 16 . pcix 0100101001111011 .......... . . U U U . . 9 9 9
887 tst 16 . i 0100101001111100 .......... . . U U U . . 6 6 6
888 tst 32 . d 0100101010000... .......... U U U U U 4 4 2 2 2
889 tst 32 . a 0100101010001... .......... . . U U U . . 2 2 2
890 tst 32 . . 0100101010...... A+-DXWL... U U U U U 4 4 2 2 2
891 tst 32 . pcdi 0100101010111010 .......... . . U U U . . 7 7 7
892 tst 32 . pcix 0100101010111011 .......... . . U U U . . 9 9 9
893 tst 32 . i 0100101010111100 .......... . . U U U . . 6 6 6
894 unlk 32 . a7 0100111001011111 .......... U U U U U 12 12 6 6 6
895 unlk 32 . . 0100111001011... .......... U U U U U 12 12 6 6 6
896 unpk 16 rr . 1000...110000... .......... . . U U U . . 8 8 8
897 unpk 16 mm ax7 1000111110001... .......... . . U U U . . 13 13 13
898 unpk 16 mm ay7 1000...110001111 .......... . . U U U . . 13 13 13
899 unpk 16 mm axy7 1000111110001111 .......... . . U U U . . 13 13 13
900 unpk 16 mm . 1000...110001... .......... . . U U U . . 13 13 13
904 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
905 M68KMAKE_OPCODE_HANDLER_BODY
907 M68KMAKE_OP(1010, 0, ., .)
909 m68ki_exception_1010();
913 M68KMAKE_OP(1111, 0, ., .)
915 m68ki_exception_1111();
919 M68KMAKE_OP(040fpu0, 32, ., .)
921 // printf("FPU 040fpu0 HAS_FPU=%d\n",!!HAS_FPU);
927 m68ki_exception_1111();
931 M68KMAKE_OP(040fpu1, 32, ., .)
933 // printf("FPU 040fpu1 HAS_FPU=%d\n",!!HAS_FPU);
939 m68ki_exception_1111();
944 M68KMAKE_OP(abcd, 8, rr, .)
949 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
951 FLAG_V = ~res; /* Undefined V behavior */
955 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
956 FLAG_X = FLAG_C = (res > 0x99) << 8;
960 FLAG_V &= res; /* Undefined V behavior part II */
961 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
963 res = MASK_OUT_ABOVE_8(res);
966 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
970 M68KMAKE_OP(abcd, 8, mm, ax7)
972 uint src = OPER_AY_PD_8();
973 uint ea = EA_A7_PD_8();
974 uint dst = m68ki_read_8(ea);
975 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
977 FLAG_V = ~res; /* Undefined V behavior */
981 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
982 FLAG_X = FLAG_C = (res > 0x99) << 8;
986 FLAG_V &= res; /* Undefined V behavior part II */
987 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
989 res = MASK_OUT_ABOVE_8(res);
992 m68ki_write_8(ea, res);
996 M68KMAKE_OP(abcd, 8, mm, ay7)
998 uint src = OPER_A7_PD_8();
999 uint ea = EA_AX_PD_8();
1000 uint dst = m68ki_read_8(ea);
1001 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1003 FLAG_V = ~res; /* Undefined V behavior */
1007 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1008 FLAG_X = FLAG_C = (res > 0x99) << 8;
1012 FLAG_V &= res; /* Undefined V behavior part II */
1013 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1015 res = MASK_OUT_ABOVE_8(res);
1018 m68ki_write_8(ea, res);
1022 M68KMAKE_OP(abcd, 8, mm, axy7)
1024 uint src = OPER_A7_PD_8();
1025 uint ea = EA_A7_PD_8();
1026 uint dst = m68ki_read_8(ea);
1027 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1029 FLAG_V = ~res; /* Undefined V behavior */
1033 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1034 FLAG_X = FLAG_C = (res > 0x99) << 8;
1038 FLAG_V &= res; /* Undefined V behavior part II */
1039 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1041 res = MASK_OUT_ABOVE_8(res);
1044 m68ki_write_8(ea, res);
1048 M68KMAKE_OP(abcd, 8, mm, .)
1050 uint src = OPER_AY_PD_8();
1051 uint ea = EA_AX_PD_8();
1052 uint dst = m68ki_read_8(ea);
1053 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1055 FLAG_V = ~res; /* Undefined V behavior */
1059 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1060 FLAG_X = FLAG_C = (res > 0x99) << 8;
1064 FLAG_V &= res; /* Undefined V behavior part II */
1065 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1067 res = MASK_OUT_ABOVE_8(res);
1070 m68ki_write_8(ea, res);
1074 M68KMAKE_OP(add, 8, er, d)
1077 uint src = MASK_OUT_ABOVE_8(DY);
1078 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1079 uint res = src + dst;
1081 FLAG_N = NFLAG_8(res);
1082 FLAG_V = VFLAG_ADD_8(src, dst, res);
1083 FLAG_X = FLAG_C = CFLAG_8(res);
1084 FLAG_Z = MASK_OUT_ABOVE_8(res);
1086 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1090 M68KMAKE_OP(add, 8, er, .)
1093 uint src = M68KMAKE_GET_OPER_AY_8;
1094 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1095 uint res = src + dst;
1097 FLAG_N = NFLAG_8(res);
1098 FLAG_V = VFLAG_ADD_8(src, dst, res);
1099 FLAG_X = FLAG_C = CFLAG_8(res);
1100 FLAG_Z = MASK_OUT_ABOVE_8(res);
1102 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1106 M68KMAKE_OP(add, 16, er, d)
1109 uint src = MASK_OUT_ABOVE_16(DY);
1110 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1111 uint res = src + dst;
1113 FLAG_N = NFLAG_16(res);
1114 FLAG_V = VFLAG_ADD_16(src, dst, res);
1115 FLAG_X = FLAG_C = CFLAG_16(res);
1116 FLAG_Z = MASK_OUT_ABOVE_16(res);
1118 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1122 M68KMAKE_OP(add, 16, er, a)
1125 uint src = MASK_OUT_ABOVE_16(AY);
1126 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1127 uint res = src + dst;
1129 FLAG_N = NFLAG_16(res);
1130 FLAG_V = VFLAG_ADD_16(src, dst, res);
1131 FLAG_X = FLAG_C = CFLAG_16(res);
1132 FLAG_Z = MASK_OUT_ABOVE_16(res);
1134 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1138 M68KMAKE_OP(add, 16, er, .)
1141 uint src = M68KMAKE_GET_OPER_AY_16;
1142 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1143 uint res = src + dst;
1145 FLAG_N = NFLAG_16(res);
1146 FLAG_V = VFLAG_ADD_16(src, dst, res);
1147 FLAG_X = FLAG_C = CFLAG_16(res);
1148 FLAG_Z = MASK_OUT_ABOVE_16(res);
1150 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1154 M68KMAKE_OP(add, 32, er, d)
1159 uint res = src + dst;
1161 FLAG_N = NFLAG_32(res);
1162 FLAG_V = VFLAG_ADD_32(src, dst, res);
1163 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1164 FLAG_Z = MASK_OUT_ABOVE_32(res);
1170 M68KMAKE_OP(add, 32, er, a)
1175 uint res = src + dst;
1177 FLAG_N = NFLAG_32(res);
1178 FLAG_V = VFLAG_ADD_32(src, dst, res);
1179 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1180 FLAG_Z = MASK_OUT_ABOVE_32(res);
1186 M68KMAKE_OP(add, 32, er, .)
1189 uint src = M68KMAKE_GET_OPER_AY_32;
1191 uint res = src + dst;
1193 FLAG_N = NFLAG_32(res);
1194 FLAG_V = VFLAG_ADD_32(src, dst, res);
1195 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1196 FLAG_Z = MASK_OUT_ABOVE_32(res);
1202 M68KMAKE_OP(add, 8, re, .)
1204 uint ea = M68KMAKE_GET_EA_AY_8;
1205 uint src = MASK_OUT_ABOVE_8(DX);
1206 uint dst = m68ki_read_8(ea);
1207 uint res = src + dst;
1209 FLAG_N = NFLAG_8(res);
1210 FLAG_V = VFLAG_ADD_8(src, dst, res);
1211 FLAG_X = FLAG_C = CFLAG_8(res);
1212 FLAG_Z = MASK_OUT_ABOVE_8(res);
1214 m68ki_write_8(ea, FLAG_Z);
1218 M68KMAKE_OP(add, 16, re, .)
1220 uint ea = M68KMAKE_GET_EA_AY_16;
1221 uint src = MASK_OUT_ABOVE_16(DX);
1222 uint dst = m68ki_read_16(ea);
1223 uint res = src + dst;
1225 FLAG_N = NFLAG_16(res);
1226 FLAG_V = VFLAG_ADD_16(src, dst, res);
1227 FLAG_X = FLAG_C = CFLAG_16(res);
1228 FLAG_Z = MASK_OUT_ABOVE_16(res);
1230 m68ki_write_16(ea, FLAG_Z);
1234 M68KMAKE_OP(add, 32, re, .)
1236 uint ea = M68KMAKE_GET_EA_AY_32;
1238 uint dst = m68ki_read_32(ea);
1239 uint res = src + dst;
1241 FLAG_N = NFLAG_32(res);
1242 FLAG_V = VFLAG_ADD_32(src, dst, res);
1243 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1244 FLAG_Z = MASK_OUT_ABOVE_32(res);
1246 m68ki_write_32(ea, FLAG_Z);
1250 M68KMAKE_OP(adda, 16, ., d)
1254 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
1258 M68KMAKE_OP(adda, 16, ., a)
1262 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
1266 M68KMAKE_OP(adda, 16, ., .)
1269 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
1271 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1275 M68KMAKE_OP(adda, 32, ., d)
1279 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
1283 M68KMAKE_OP(adda, 32, ., a)
1287 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
1291 M68KMAKE_OP(adda, 32, ., .)
1293 uint src = M68KMAKE_GET_OPER_AY_32;
1296 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1300 M68KMAKE_OP(addi, 8, ., d)
1303 uint src = OPER_I_8();
1304 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1305 uint res = src + dst;
1307 FLAG_N = NFLAG_8(res);
1308 FLAG_V = VFLAG_ADD_8(src, dst, res);
1309 FLAG_X = FLAG_C = CFLAG_8(res);
1310 FLAG_Z = MASK_OUT_ABOVE_8(res);
1312 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1316 M68KMAKE_OP(addi, 8, ., .)
1318 uint src = OPER_I_8();
1319 uint ea = M68KMAKE_GET_EA_AY_8;
1320 uint dst = m68ki_read_8(ea);
1321 uint res = src + dst;
1323 FLAG_N = NFLAG_8(res);
1324 FLAG_V = VFLAG_ADD_8(src, dst, res);
1325 FLAG_X = FLAG_C = CFLAG_8(res);
1326 FLAG_Z = MASK_OUT_ABOVE_8(res);
1328 m68ki_write_8(ea, FLAG_Z);
1332 M68KMAKE_OP(addi, 16, ., d)
1335 uint src = OPER_I_16();
1336 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1337 uint res = src + dst;
1339 FLAG_N = NFLAG_16(res);
1340 FLAG_V = VFLAG_ADD_16(src, dst, res);
1341 FLAG_X = FLAG_C = CFLAG_16(res);
1342 FLAG_Z = MASK_OUT_ABOVE_16(res);
1344 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1348 M68KMAKE_OP(addi, 16, ., .)
1350 uint src = OPER_I_16();
1351 uint ea = M68KMAKE_GET_EA_AY_16;
1352 uint dst = m68ki_read_16(ea);
1353 uint res = src + dst;
1355 FLAG_N = NFLAG_16(res);
1356 FLAG_V = VFLAG_ADD_16(src, dst, res);
1357 FLAG_X = FLAG_C = CFLAG_16(res);
1358 FLAG_Z = MASK_OUT_ABOVE_16(res);
1360 m68ki_write_16(ea, FLAG_Z);
1364 M68KMAKE_OP(addi, 32, ., d)
1367 uint src = OPER_I_32();
1369 uint res = src + dst;
1371 FLAG_N = NFLAG_32(res);
1372 FLAG_V = VFLAG_ADD_32(src, dst, res);
1373 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1374 FLAG_Z = MASK_OUT_ABOVE_32(res);
1380 M68KMAKE_OP(addi, 32, ., .)
1382 uint src = OPER_I_32();
1383 uint ea = M68KMAKE_GET_EA_AY_32;
1384 uint dst = m68ki_read_32(ea);
1385 uint res = src + dst;
1387 FLAG_N = NFLAG_32(res);
1388 FLAG_V = VFLAG_ADD_32(src, dst, res);
1389 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1390 FLAG_Z = MASK_OUT_ABOVE_32(res);
1392 m68ki_write_32(ea, FLAG_Z);
1396 M68KMAKE_OP(addq, 8, ., d)
1399 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1400 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1401 uint res = src + dst;
1403 FLAG_N = NFLAG_8(res);
1404 FLAG_V = VFLAG_ADD_8(src, dst, res);
1405 FLAG_X = FLAG_C = CFLAG_8(res);
1406 FLAG_Z = MASK_OUT_ABOVE_8(res);
1408 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1412 M68KMAKE_OP(addq, 8, ., .)
1414 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1415 uint ea = M68KMAKE_GET_EA_AY_8;
1416 uint dst = m68ki_read_8(ea);
1417 uint res = src + dst;
1419 FLAG_N = NFLAG_8(res);
1420 FLAG_V = VFLAG_ADD_8(src, dst, res);
1421 FLAG_X = FLAG_C = CFLAG_8(res);
1422 FLAG_Z = MASK_OUT_ABOVE_8(res);
1424 m68ki_write_8(ea, FLAG_Z);
1428 M68KMAKE_OP(addq, 16, ., d)
1431 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1432 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1433 uint res = src + dst;
1435 FLAG_N = NFLAG_16(res);
1436 FLAG_V = VFLAG_ADD_16(src, dst, res);
1437 FLAG_X = FLAG_C = CFLAG_16(res);
1438 FLAG_Z = MASK_OUT_ABOVE_16(res);
1440 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1444 M68KMAKE_OP(addq, 16, ., a)
1448 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1452 M68KMAKE_OP(addq, 16, ., .)
1454 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1455 uint ea = M68KMAKE_GET_EA_AY_16;
1456 uint dst = m68ki_read_16(ea);
1457 uint res = src + dst;
1459 FLAG_N = NFLAG_16(res);
1460 FLAG_V = VFLAG_ADD_16(src, dst, res);
1461 FLAG_X = FLAG_C = CFLAG_16(res);
1462 FLAG_Z = MASK_OUT_ABOVE_16(res);
1464 m68ki_write_16(ea, FLAG_Z);
1468 M68KMAKE_OP(addq, 32, ., d)
1471 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1473 uint res = src + dst;
1475 FLAG_N = NFLAG_32(res);
1476 FLAG_V = VFLAG_ADD_32(src, dst, res);
1477 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1478 FLAG_Z = MASK_OUT_ABOVE_32(res);
1484 M68KMAKE_OP(addq, 32, ., a)
1488 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1492 M68KMAKE_OP(addq, 32, ., .)
1494 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1495 uint ea = M68KMAKE_GET_EA_AY_32;
1496 uint dst = m68ki_read_32(ea);
1497 uint res = src + dst;
1500 FLAG_N = NFLAG_32(res);
1501 FLAG_V = VFLAG_ADD_32(src, dst, res);
1502 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1503 FLAG_Z = MASK_OUT_ABOVE_32(res);
1505 m68ki_write_32(ea, FLAG_Z);
1509 M68KMAKE_OP(addx, 8, rr, .)
1512 uint src = MASK_OUT_ABOVE_8(DY);
1513 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1514 uint res = src + dst + XFLAG_AS_1();
1516 FLAG_N = NFLAG_8(res);
1517 FLAG_V = VFLAG_ADD_8(src, dst, res);
1518 FLAG_X = FLAG_C = CFLAG_8(res);
1520 res = MASK_OUT_ABOVE_8(res);
1523 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1527 M68KMAKE_OP(addx, 16, rr, .)
1530 uint src = MASK_OUT_ABOVE_16(DY);
1531 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1532 uint res = src + dst + XFLAG_AS_1();
1534 FLAG_N = NFLAG_16(res);
1535 FLAG_V = VFLAG_ADD_16(src, dst, res);
1536 FLAG_X = FLAG_C = CFLAG_16(res);
1538 res = MASK_OUT_ABOVE_16(res);
1541 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1545 M68KMAKE_OP(addx, 32, rr, .)
1550 uint res = src + dst + XFLAG_AS_1();
1552 FLAG_N = NFLAG_32(res);
1553 FLAG_V = VFLAG_ADD_32(src, dst, res);
1554 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1556 res = MASK_OUT_ABOVE_32(res);
1563 M68KMAKE_OP(addx, 8, mm, ax7)
1565 uint src = OPER_AY_PD_8();
1566 uint ea = EA_A7_PD_8();
1567 uint dst = m68ki_read_8(ea);
1568 uint res = src + dst + XFLAG_AS_1();
1570 FLAG_N = NFLAG_8(res);
1571 FLAG_V = VFLAG_ADD_8(src, dst, res);
1572 FLAG_X = FLAG_C = CFLAG_8(res);
1574 res = MASK_OUT_ABOVE_8(res);
1577 m68ki_write_8(ea, res);
1581 M68KMAKE_OP(addx, 8, mm, ay7)
1583 uint src = OPER_A7_PD_8();
1584 uint ea = EA_AX_PD_8();
1585 uint dst = m68ki_read_8(ea);
1586 uint res = src + dst + XFLAG_AS_1();
1588 FLAG_N = NFLAG_8(res);
1589 FLAG_V = VFLAG_ADD_8(src, dst, res);
1590 FLAG_X = FLAG_C = CFLAG_8(res);
1592 res = MASK_OUT_ABOVE_8(res);
1595 m68ki_write_8(ea, res);
1599 M68KMAKE_OP(addx, 8, mm, axy7)
1601 uint src = OPER_A7_PD_8();
1602 uint ea = EA_A7_PD_8();
1603 uint dst = m68ki_read_8(ea);
1604 uint res = src + dst + XFLAG_AS_1();
1606 FLAG_N = NFLAG_8(res);
1607 FLAG_V = VFLAG_ADD_8(src, dst, res);
1608 FLAG_X = FLAG_C = CFLAG_8(res);
1610 res = MASK_OUT_ABOVE_8(res);
1613 m68ki_write_8(ea, res);
1617 M68KMAKE_OP(addx, 8, mm, .)
1619 uint src = OPER_AY_PD_8();
1620 uint ea = EA_AX_PD_8();
1621 uint dst = m68ki_read_8(ea);
1622 uint res = src + dst + XFLAG_AS_1();
1624 FLAG_N = NFLAG_8(res);
1625 FLAG_V = VFLAG_ADD_8(src, dst, res);
1626 FLAG_X = FLAG_C = CFLAG_8(res);
1628 res = MASK_OUT_ABOVE_8(res);
1631 m68ki_write_8(ea, res);
1635 M68KMAKE_OP(addx, 16, mm, .)
1637 uint src = OPER_AY_PD_16();
1638 uint ea = EA_AX_PD_16();
1639 uint dst = m68ki_read_16(ea);
1640 uint res = src + dst + XFLAG_AS_1();
1642 FLAG_N = NFLAG_16(res);
1643 FLAG_V = VFLAG_ADD_16(src, dst, res);
1644 FLAG_X = FLAG_C = CFLAG_16(res);
1646 res = MASK_OUT_ABOVE_16(res);
1649 m68ki_write_16(ea, res);
1653 M68KMAKE_OP(addx, 32, mm, .)
1655 uint src = OPER_AY_PD_32();
1656 uint ea = EA_AX_PD_32();
1657 uint dst = m68ki_read_32(ea);
1658 uint res = src + dst + XFLAG_AS_1();
1660 FLAG_N = NFLAG_32(res);
1661 FLAG_V = VFLAG_ADD_32(src, dst, res);
1662 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1664 res = MASK_OUT_ABOVE_32(res);
1667 m68ki_write_32(ea, res);
1671 M68KMAKE_OP(and, 8, er, d)
1673 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
1675 FLAG_N = NFLAG_8(FLAG_Z);
1676 FLAG_C = CFLAG_CLEAR;
1677 FLAG_V = VFLAG_CLEAR;
1681 M68KMAKE_OP(and, 8, er, .)
1683 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
1685 FLAG_N = NFLAG_8(FLAG_Z);
1686 FLAG_C = CFLAG_CLEAR;
1687 FLAG_V = VFLAG_CLEAR;
1691 M68KMAKE_OP(and, 16, er, d)
1693 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
1695 FLAG_N = NFLAG_16(FLAG_Z);
1696 FLAG_C = CFLAG_CLEAR;
1697 FLAG_V = VFLAG_CLEAR;
1701 M68KMAKE_OP(and, 16, er, .)
1703 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
1705 FLAG_N = NFLAG_16(FLAG_Z);
1706 FLAG_C = CFLAG_CLEAR;
1707 FLAG_V = VFLAG_CLEAR;
1711 M68KMAKE_OP(and, 32, er, d)
1715 FLAG_N = NFLAG_32(FLAG_Z);
1716 FLAG_C = CFLAG_CLEAR;
1717 FLAG_V = VFLAG_CLEAR;
1721 M68KMAKE_OP(and, 32, er, .)
1723 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
1725 FLAG_N = NFLAG_32(FLAG_Z);
1726 FLAG_C = CFLAG_CLEAR;
1727 FLAG_V = VFLAG_CLEAR;
1731 M68KMAKE_OP(and, 8, re, .)
1733 uint ea = M68KMAKE_GET_EA_AY_8;
1734 uint res = DX & m68ki_read_8(ea);
1736 FLAG_N = NFLAG_8(res);
1737 FLAG_C = CFLAG_CLEAR;
1738 FLAG_V = VFLAG_CLEAR;
1739 FLAG_Z = MASK_OUT_ABOVE_8(res);
1741 m68ki_write_8(ea, FLAG_Z);
1745 M68KMAKE_OP(and, 16, re, .)
1747 uint ea = M68KMAKE_GET_EA_AY_16;
1748 uint res = DX & m68ki_read_16(ea);
1750 FLAG_N = NFLAG_16(res);
1751 FLAG_C = CFLAG_CLEAR;
1752 FLAG_V = VFLAG_CLEAR;
1753 FLAG_Z = MASK_OUT_ABOVE_16(res);
1755 m68ki_write_16(ea, FLAG_Z);
1759 M68KMAKE_OP(and, 32, re, .)
1761 uint ea = M68KMAKE_GET_EA_AY_32;
1762 uint res = DX & m68ki_read_32(ea);
1764 FLAG_N = NFLAG_32(res);
1766 FLAG_C = CFLAG_CLEAR;
1767 FLAG_V = VFLAG_CLEAR;
1769 m68ki_write_32(ea, res);
1773 M68KMAKE_OP(andi, 8, ., d)
1775 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
1777 FLAG_N = NFLAG_8(FLAG_Z);
1778 FLAG_C = CFLAG_CLEAR;
1779 FLAG_V = VFLAG_CLEAR;
1783 M68KMAKE_OP(andi, 8, ., .)
1785 uint src = OPER_I_8();
1786 uint ea = M68KMAKE_GET_EA_AY_8;
1787 uint res = src & m68ki_read_8(ea);
1789 FLAG_N = NFLAG_8(res);
1791 FLAG_C = CFLAG_CLEAR;
1792 FLAG_V = VFLAG_CLEAR;
1794 m68ki_write_8(ea, res);
1798 M68KMAKE_OP(andi, 16, ., d)
1800 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
1802 FLAG_N = NFLAG_16(FLAG_Z);
1803 FLAG_C = CFLAG_CLEAR;
1804 FLAG_V = VFLAG_CLEAR;
1808 M68KMAKE_OP(andi, 16, ., .)
1810 uint src = OPER_I_16();
1811 uint ea = M68KMAKE_GET_EA_AY_16;
1812 uint res = src & m68ki_read_16(ea);
1814 FLAG_N = NFLAG_16(res);
1816 FLAG_C = CFLAG_CLEAR;
1817 FLAG_V = VFLAG_CLEAR;
1819 m68ki_write_16(ea, res);
1823 M68KMAKE_OP(andi, 32, ., d)
1825 FLAG_Z = DY &= (OPER_I_32());
1827 FLAG_N = NFLAG_32(FLAG_Z);
1828 FLAG_C = CFLAG_CLEAR;
1829 FLAG_V = VFLAG_CLEAR;
1833 M68KMAKE_OP(andi, 32, ., .)
1835 uint src = OPER_I_32();
1836 uint ea = M68KMAKE_GET_EA_AY_32;
1837 uint res = src & m68ki_read_32(ea);
1839 FLAG_N = NFLAG_32(res);
1841 FLAG_C = CFLAG_CLEAR;
1842 FLAG_V = VFLAG_CLEAR;
1844 m68ki_write_32(ea, res);
1848 M68KMAKE_OP(andi, 16, toc, .)
1850 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8());
1854 M68KMAKE_OP(andi, 16, tos, .)
1858 uint src = OPER_I_16();
1859 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
1860 m68ki_set_sr(m68ki_get_sr() & src);
1863 m68ki_exception_privilege_violation();
1867 M68KMAKE_OP(asr, 8, s, .)
1870 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1871 uint src = MASK_OUT_ABOVE_8(*r_dst);
1872 uint res = src >> shift;
1875 USE_CYCLES(shift<<CYC_SHIFT);
1878 res |= m68ki_shift_8_table[shift];
1880 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1882 FLAG_N = NFLAG_8(res);
1884 FLAG_V = VFLAG_CLEAR;
1885 FLAG_X = FLAG_C = src << (9-shift);
1889 M68KMAKE_OP(asr, 16, s, .)
1892 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1893 uint src = MASK_OUT_ABOVE_16(*r_dst);
1894 uint res = src >> shift;
1897 USE_CYCLES(shift<<CYC_SHIFT);
1900 res |= m68ki_shift_16_table[shift];
1902 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1904 FLAG_N = NFLAG_16(res);
1906 FLAG_V = VFLAG_CLEAR;
1907 FLAG_X = FLAG_C = src << (9-shift);
1911 M68KMAKE_OP(asr, 32, s, .)
1914 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1916 uint res = src >> shift;
1919 USE_CYCLES(shift<<CYC_SHIFT);
1922 res |= m68ki_shift_32_table[shift];
1926 FLAG_N = NFLAG_32(res);
1928 FLAG_V = VFLAG_CLEAR;
1929 FLAG_X = FLAG_C = src << (9-shift);
1933 M68KMAKE_OP(asr, 8, r, .)
1936 uint shift = DX & 0x3f;
1937 uint src = MASK_OUT_ABOVE_8(*r_dst);
1938 uint res = src >> shift;
1942 USE_CYCLES(shift<<CYC_SHIFT);
1947 res |= m68ki_shift_8_table[shift];
1949 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1951 FLAG_X = FLAG_C = src << (9-shift);
1952 FLAG_N = NFLAG_8(res);
1954 FLAG_V = VFLAG_CLEAR;
1964 FLAG_Z = ZFLAG_CLEAR;
1965 FLAG_V = VFLAG_CLEAR;
1969 *r_dst &= 0xffffff00;
1970 FLAG_C = CFLAG_CLEAR;
1971 FLAG_X = XFLAG_CLEAR;
1972 FLAG_N = NFLAG_CLEAR;
1974 FLAG_V = VFLAG_CLEAR;
1978 FLAG_C = CFLAG_CLEAR;
1979 FLAG_N = NFLAG_8(src);
1981 FLAG_V = VFLAG_CLEAR;
1985 M68KMAKE_OP(asr, 16, r, .)
1988 uint shift = DX & 0x3f;
1989 uint src = MASK_OUT_ABOVE_16(*r_dst);
1990 uint res = src >> shift;
1994 USE_CYCLES(shift<<CYC_SHIFT);
1999 res |= m68ki_shift_16_table[shift];
2001 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2003 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2004 FLAG_N = NFLAG_16(res);
2006 FLAG_V = VFLAG_CLEAR;
2016 FLAG_Z = ZFLAG_CLEAR;
2017 FLAG_V = VFLAG_CLEAR;
2021 *r_dst &= 0xffff0000;
2022 FLAG_C = CFLAG_CLEAR;
2023 FLAG_X = XFLAG_CLEAR;
2024 FLAG_N = NFLAG_CLEAR;
2026 FLAG_V = VFLAG_CLEAR;
2030 FLAG_C = CFLAG_CLEAR;
2031 FLAG_N = NFLAG_16(src);
2033 FLAG_V = VFLAG_CLEAR;
2037 M68KMAKE_OP(asr, 32, r, .)
2040 uint shift = DX & 0x3f;
2042 uint res = src >> shift;
2046 USE_CYCLES(shift<<CYC_SHIFT);
2051 res |= m68ki_shift_32_table[shift];
2055 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2056 FLAG_N = NFLAG_32(res);
2058 FLAG_V = VFLAG_CLEAR;
2064 *r_dst = 0xffffffff;
2068 FLAG_Z = ZFLAG_CLEAR;
2069 FLAG_V = VFLAG_CLEAR;
2074 FLAG_C = CFLAG_CLEAR;
2075 FLAG_X = XFLAG_CLEAR;
2076 FLAG_N = NFLAG_CLEAR;
2078 FLAG_V = VFLAG_CLEAR;
2082 FLAG_C = CFLAG_CLEAR;
2083 FLAG_N = NFLAG_32(src);
2085 FLAG_V = VFLAG_CLEAR;
2089 M68KMAKE_OP(asr, 16, ., .)
2091 uint ea = M68KMAKE_GET_EA_AY_16;
2092 uint src = m68ki_read_16(ea);
2093 uint res = src >> 1;
2098 m68ki_write_16(ea, res);
2100 FLAG_N = NFLAG_16(res);
2102 FLAG_V = VFLAG_CLEAR;
2103 FLAG_C = FLAG_X = src << 8;
2107 M68KMAKE_OP(asl, 8, s, .)
2110 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2111 uint src = MASK_OUT_ABOVE_8(*r_dst);
2112 uint res = MASK_OUT_ABOVE_8(src << shift);
2115 USE_CYCLES(shift<<CYC_SHIFT);
2117 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2119 FLAG_X = FLAG_C = src << shift;
2120 FLAG_N = NFLAG_8(res);
2122 src &= m68ki_shift_8_table[shift + 1];
2123 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
2127 M68KMAKE_OP(asl, 16, s, .)
2130 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2131 uint src = MASK_OUT_ABOVE_16(*r_dst);
2132 uint res = MASK_OUT_ABOVE_16(src << shift);
2135 USE_CYCLES(shift<<CYC_SHIFT);
2137 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2139 FLAG_N = NFLAG_16(res);
2141 FLAG_X = FLAG_C = src >> (8-shift);
2142 src &= m68ki_shift_16_table[shift + 1];
2143 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2147 M68KMAKE_OP(asl, 32, s, .)
2150 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2152 uint res = MASK_OUT_ABOVE_32(src << shift);
2155 USE_CYCLES(shift<<CYC_SHIFT);
2159 FLAG_N = NFLAG_32(res);
2161 FLAG_X = FLAG_C = src >> (24-shift);
2162 src &= m68ki_shift_32_table[shift + 1];
2163 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2167 M68KMAKE_OP(asl, 8, r, .)
2170 uint shift = DX & 0x3f;
2171 uint src = MASK_OUT_ABOVE_8(*r_dst);
2172 uint res = MASK_OUT_ABOVE_8(src << shift);
2176 USE_CYCLES(shift<<CYC_SHIFT);
2180 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2181 FLAG_X = FLAG_C = src << shift;
2182 FLAG_N = NFLAG_8(res);
2184 src &= m68ki_shift_8_table[shift + 1];
2185 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
2189 *r_dst &= 0xffffff00;
2190 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
2191 FLAG_N = NFLAG_CLEAR;
2193 FLAG_V = (!(src == 0))<<7;
2197 FLAG_C = CFLAG_CLEAR;
2198 FLAG_N = NFLAG_8(src);
2200 FLAG_V = VFLAG_CLEAR;
2204 M68KMAKE_OP(asl, 16, r, .)
2207 uint shift = DX & 0x3f;
2208 uint src = MASK_OUT_ABOVE_16(*r_dst);
2209 uint res = MASK_OUT_ABOVE_16(src << shift);
2213 USE_CYCLES(shift<<CYC_SHIFT);
2217 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2218 FLAG_X = FLAG_C = (src << shift) >> 8;
2219 FLAG_N = NFLAG_16(res);
2221 src &= m68ki_shift_16_table[shift + 1];
2222 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2226 *r_dst &= 0xffff0000;
2227 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
2228 FLAG_N = NFLAG_CLEAR;
2230 FLAG_V = (!(src == 0))<<7;
2234 FLAG_C = CFLAG_CLEAR;
2235 FLAG_N = NFLAG_16(src);
2237 FLAG_V = VFLAG_CLEAR;
2241 M68KMAKE_OP(asl, 32, r, .)
2244 uint shift = DX & 0x3f;
2246 uint res = MASK_OUT_ABOVE_32(src << shift);
2250 USE_CYCLES(shift<<CYC_SHIFT);
2255 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
2256 FLAG_N = NFLAG_32(res);
2258 src &= m68ki_shift_32_table[shift + 1];
2259 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2264 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
2265 FLAG_N = NFLAG_CLEAR;
2267 FLAG_V = (!(src == 0))<<7;
2271 FLAG_C = CFLAG_CLEAR;
2272 FLAG_N = NFLAG_32(src);
2274 FLAG_V = VFLAG_CLEAR;
2278 M68KMAKE_OP(asl, 16, ., .)
2280 uint ea = M68KMAKE_GET_EA_AY_16;
2281 uint src = m68ki_read_16(ea);
2282 uint res = MASK_OUT_ABOVE_16(src << 1);
2284 m68ki_write_16(ea, res);
2286 FLAG_N = NFLAG_16(res);
2288 FLAG_X = FLAG_C = src >> 7;
2290 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
2294 M68KMAKE_OP(bcc, 8, ., .)
2298 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2299 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2302 USE_CYCLES(CYC_BCC_NOTAKE_B);
2306 M68KMAKE_OP(bcc, 16, ., .)
2310 uint offset = OPER_I_16();
2312 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2313 m68ki_branch_16(offset);
2317 USE_CYCLES(CYC_BCC_NOTAKE_W);
2321 M68KMAKE_OP(bcc, 32, ., .)
2323 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2327 uint offset = OPER_I_32();
2329 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2330 m68ki_branch_32(offset);
2340 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2341 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2344 USE_CYCLES(CYC_BCC_NOTAKE_B);
2349 M68KMAKE_OP(bchg, 32, r, d)
2352 uint mask = 1 << (DX & 0x1f);
2354 FLAG_Z = *r_dst & mask;
2359 M68KMAKE_OP(bchg, 8, r, .)
2361 uint ea = M68KMAKE_GET_EA_AY_8;
2362 uint src = m68ki_read_8(ea);
2363 uint mask = 1 << (DX & 7);
2365 FLAG_Z = src & mask;
2366 m68ki_write_8(ea, src ^ mask);
2370 M68KMAKE_OP(bchg, 32, s, d)
2373 uint mask = 1 << (OPER_I_8() & 0x1f);
2375 FLAG_Z = *r_dst & mask;
2380 M68KMAKE_OP(bchg, 8, s, .)
2382 uint mask = 1 << (OPER_I_8() & 7);
2383 uint ea = M68KMAKE_GET_EA_AY_8;
2384 uint src = m68ki_read_8(ea);
2386 FLAG_Z = src & mask;
2387 m68ki_write_8(ea, src ^ mask);
2391 M68KMAKE_OP(bclr, 32, r, d)
2394 uint mask = 1 << (DX & 0x1f);
2396 FLAG_Z = *r_dst & mask;
2401 M68KMAKE_OP(bclr, 8, r, .)
2403 uint ea = M68KMAKE_GET_EA_AY_8;
2404 uint src = m68ki_read_8(ea);
2405 uint mask = 1 << (DX & 7);
2407 FLAG_Z = src & mask;
2408 m68ki_write_8(ea, src & ~mask);
2412 M68KMAKE_OP(bclr, 32, s, d)
2415 uint mask = 1 << (OPER_I_8() & 0x1f);
2417 FLAG_Z = *r_dst & mask;
2422 M68KMAKE_OP(bclr, 8, s, .)
2424 uint mask = 1 << (OPER_I_8() & 7);
2425 uint ea = M68KMAKE_GET_EA_AY_8;
2426 uint src = m68ki_read_8(ea);
2428 FLAG_Z = src & mask;
2429 m68ki_write_8(ea, src & ~mask);
2433 M68KMAKE_OP(bfchg, 32, ., d)
2435 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2437 uint word2 = OPER_I_16();
2438 uint offset = (word2>>6)&31;
2445 offset = REG_D[offset&7];
2447 width = REG_D[width&7];
2450 width = ((width-1) & 31) + 1;
2452 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2453 mask = ROR_32(mask, offset);
2455 FLAG_N = NFLAG_32(*data<<offset);
2456 FLAG_Z = *data & mask;
2457 FLAG_V = VFLAG_CLEAR;
2458 FLAG_C = CFLAG_CLEAR;
2464 m68ki_exception_illegal();
2468 M68KMAKE_OP(bfchg, 32, ., .)
2470 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2472 uint word2 = OPER_I_16();
2473 sint offset = (word2>>6)&31;
2480 uint ea = M68KMAKE_GET_EA_AY_8;
2484 offset = MAKE_INT_32(REG_D[offset&7]);
2486 width = REG_D[width&7];
2488 /* Offset is signed so we have to use ugly math =( */
2496 width = ((width-1) & 31) + 1;
2498 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2499 mask_long = mask_base >> offset;
2501 data_long = m68ki_read_32(ea);
2502 FLAG_N = NFLAG_32(data_long << offset);
2503 FLAG_Z = data_long & mask_long;
2504 FLAG_V = VFLAG_CLEAR;
2505 FLAG_C = CFLAG_CLEAR;
2507 m68ki_write_32(ea, data_long ^ mask_long);
2509 if((width + offset) > 32)
2511 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2512 data_byte = m68ki_read_8(ea+4);
2513 FLAG_Z |= (data_byte & mask_byte);
2514 m68ki_write_8(ea+4, data_byte ^ mask_byte);
2518 m68ki_exception_illegal();
2522 M68KMAKE_OP(bfclr, 32, ., d)
2524 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2526 uint word2 = OPER_I_16();
2527 uint offset = (word2>>6)&31;
2534 offset = REG_D[offset&7];
2536 width = REG_D[width&7];
2540 width = ((width-1) & 31) + 1;
2543 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2544 mask = ROR_32(mask, offset);
2546 FLAG_N = NFLAG_32(*data<<offset);
2547 FLAG_Z = *data & mask;
2548 FLAG_V = VFLAG_CLEAR;
2549 FLAG_C = CFLAG_CLEAR;
2555 m68ki_exception_illegal();
2559 M68KMAKE_OP(bfclr, 32, ., .)
2561 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2563 uint word2 = OPER_I_16();
2564 sint offset = (word2>>6)&31;
2571 uint ea = M68KMAKE_GET_EA_AY_8;
2575 offset = MAKE_INT_32(REG_D[offset&7]);
2577 width = REG_D[width&7];
2579 /* Offset is signed so we have to use ugly math =( */
2587 width = ((width-1) & 31) + 1;
2589 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2590 mask_long = mask_base >> offset;
2592 data_long = m68ki_read_32(ea);
2593 FLAG_N = NFLAG_32(data_long << offset);
2594 FLAG_Z = data_long & mask_long;
2595 FLAG_V = VFLAG_CLEAR;
2596 FLAG_C = CFLAG_CLEAR;
2598 m68ki_write_32(ea, data_long & ~mask_long);
2600 if((width + offset) > 32)
2602 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2603 data_byte = m68ki_read_8(ea+4);
2604 FLAG_Z |= (data_byte & mask_byte);
2605 m68ki_write_8(ea+4, data_byte & ~mask_byte);
2609 m68ki_exception_illegal();
2613 M68KMAKE_OP(bfexts, 32, ., d)
2615 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2617 uint word2 = OPER_I_16();
2618 uint offset = (word2>>6)&31;
2624 offset = REG_D[offset&7];
2626 width = REG_D[width&7];
2629 width = ((width-1) & 31) + 1;
2631 data = ROL_32(data, offset);
2632 FLAG_N = NFLAG_32(data);
2633 data = MAKE_INT_32(data) >> (32 - width);
2636 FLAG_V = VFLAG_CLEAR;
2637 FLAG_C = CFLAG_CLEAR;
2639 REG_D[(word2>>12)&7] = data;
2643 m68ki_exception_illegal();
2647 M68KMAKE_OP(bfexts, 32, ., .)
2649 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2651 uint word2 = OPER_I_16();
2652 sint offset = (word2>>6)&31;
2655 uint ea = M68KMAKE_GET_EA_AY_8;
2659 offset = MAKE_INT_32(REG_D[offset&7]);
2661 width = REG_D[width&7];
2663 /* Offset is signed so we have to use ugly math =( */
2671 width = ((width-1) & 31) + 1;
2673 data = m68ki_read_32(ea);
2675 data = MASK_OUT_ABOVE_32(data<<offset);
2677 if((offset+width) > 32)
2678 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2680 FLAG_N = NFLAG_32(data);
2681 data = MAKE_INT_32(data) >> (32 - width);
2684 FLAG_V = VFLAG_CLEAR;
2685 FLAG_C = CFLAG_CLEAR;
2687 REG_D[(word2 >> 12) & 7] = data;
2691 m68ki_exception_illegal();
2695 M68KMAKE_OP(bfextu, 32, ., d)
2697 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2699 uint word2 = OPER_I_16();
2700 uint offset = (word2>>6)&31;
2706 offset = REG_D[offset&7];
2708 width = REG_D[width&7];
2711 width = ((width-1) & 31) + 1;
2713 data = ROL_32(data, offset);
2714 FLAG_N = NFLAG_32(data);
2715 data >>= 32 - width;
2718 FLAG_V = VFLAG_CLEAR;
2719 FLAG_C = CFLAG_CLEAR;
2721 REG_D[(word2>>12)&7] = data;
2725 m68ki_exception_illegal();
2729 M68KMAKE_OP(bfextu, 32, ., .)
2731 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2733 uint word2 = OPER_I_16();
2734 sint offset = (word2>>6)&31;
2737 uint ea = M68KMAKE_GET_EA_AY_8;
2741 offset = MAKE_INT_32(REG_D[offset&7]);
2743 width = REG_D[width&7];
2745 /* Offset is signed so we have to use ugly math =( */
2753 width = ((width-1) & 31) + 1;
2755 data = m68ki_read_32(ea);
2756 data = MASK_OUT_ABOVE_32(data<<offset);
2758 if((offset+width) > 32)
2759 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2761 FLAG_N = NFLAG_32(data);
2762 data >>= (32 - width);
2765 FLAG_V = VFLAG_CLEAR;
2766 FLAG_C = CFLAG_CLEAR;
2768 REG_D[(word2 >> 12) & 7] = data;
2772 m68ki_exception_illegal();
2776 M68KMAKE_OP(bfffo, 32, ., d)
2778 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2780 uint word2 = OPER_I_16();
2781 uint offset = (word2>>6)&31;
2788 offset = REG_D[offset&7];
2790 width = REG_D[width&7];
2793 width = ((width-1) & 31) + 1;
2795 data = ROL_32(data, offset);
2796 FLAG_N = NFLAG_32(data);
2797 data >>= 32 - width;
2800 FLAG_V = VFLAG_CLEAR;
2801 FLAG_C = CFLAG_CLEAR;
2803 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2806 REG_D[(word2>>12)&7] = offset;
2810 m68ki_exception_illegal();
2814 M68KMAKE_OP(bfffo, 32, ., .)
2816 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2818 uint word2 = OPER_I_16();
2819 sint offset = (word2>>6)&31;
2824 uint ea = M68KMAKE_GET_EA_AY_8;
2828 offset = MAKE_INT_32(REG_D[offset&7]);
2830 width = REG_D[width&7];
2832 /* Offset is signed so we have to use ugly math =( */
2834 local_offset = offset % 8;
2835 if(local_offset < 0)
2840 width = ((width-1) & 31) + 1;
2842 data = m68ki_read_32(ea);
2843 data = MASK_OUT_ABOVE_32(data<<local_offset);
2845 if((local_offset+width) > 32)
2846 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
2848 FLAG_N = NFLAG_32(data);
2849 data >>= (32 - width);
2852 FLAG_V = VFLAG_CLEAR;
2853 FLAG_C = CFLAG_CLEAR;
2855 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2858 REG_D[(word2>>12)&7] = offset;
2862 m68ki_exception_illegal();
2866 M68KMAKE_OP(bfins, 32, ., d)
2868 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2870 uint word2 = OPER_I_16();
2871 uint offset = (word2>>6)&31;
2875 uint64 insert = REG_D[(word2>>12)&7];
2879 offset = REG_D[offset&7];
2881 width = REG_D[width&7];
2885 width = ((width-1) & 31) + 1;
2888 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2889 mask = ROR_32(mask, offset);
2891 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
2892 FLAG_N = NFLAG_32(insert);
2894 insert = ROR_32(insert, offset);
2896 FLAG_V = VFLAG_CLEAR;
2897 FLAG_C = CFLAG_CLEAR;
2904 m68ki_exception_illegal();
2908 M68KMAKE_OP(bfins, 32, ., .)
2910 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2912 uint word2 = OPER_I_16();
2913 sint offset = (word2>>6)&31;
2915 uint insert_base = REG_D[(word2>>12)&7];
2923 uint ea = M68KMAKE_GET_EA_AY_8;
2927 offset = MAKE_INT_32(REG_D[offset&7]);
2929 width = REG_D[width&7];
2931 /* Offset is signed so we have to use ugly math =( */
2939 width = ((width-1) & 31) + 1;
2941 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2942 mask_long = mask_base >> offset;
2944 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
2945 FLAG_N = NFLAG_32(insert_base);
2946 FLAG_Z = insert_base;
2947 insert_long = insert_base >> offset;
2949 data_long = m68ki_read_32(ea);
2950 FLAG_V = VFLAG_CLEAR;
2951 FLAG_C = CFLAG_CLEAR;
2953 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
2955 if((width + offset) > 32)
2957 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2958 insert_byte = MASK_OUT_ABOVE_8(insert_base);
2959 data_byte = m68ki_read_8(ea+4);
2960 FLAG_Z |= (data_byte & mask_byte);
2961 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
2965 m68ki_exception_illegal();
2969 M68KMAKE_OP(bfset, 32, ., d)
2971 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2973 uint word2 = OPER_I_16();
2974 uint offset = (word2>>6)&31;
2981 offset = REG_D[offset&7];
2983 width = REG_D[width&7];
2987 width = ((width-1) & 31) + 1;
2990 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2991 mask = ROR_32(mask, offset);
2993 FLAG_N = NFLAG_32(*data<<offset);
2994 FLAG_Z = *data & mask;
2995 FLAG_V = VFLAG_CLEAR;
2996 FLAG_C = CFLAG_CLEAR;
3002 m68ki_exception_illegal();
3006 M68KMAKE_OP(bfset, 32, ., .)
3008 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3010 uint word2 = OPER_I_16();
3011 sint offset = (word2>>6)&31;
3018 uint ea = M68KMAKE_GET_EA_AY_8;
3022 offset = MAKE_INT_32(REG_D[offset&7]);
3024 width = REG_D[width&7];
3026 /* Offset is signed so we have to use ugly math =( */
3034 width = ((width-1) & 31) + 1;
3037 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3038 mask_long = mask_base >> offset;
3040 data_long = m68ki_read_32(ea);
3041 FLAG_N = NFLAG_32(data_long << offset);
3042 FLAG_Z = data_long & mask_long;
3043 FLAG_V = VFLAG_CLEAR;
3044 FLAG_C = CFLAG_CLEAR;
3046 m68ki_write_32(ea, data_long | mask_long);
3048 if((width + offset) > 32)
3050 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3051 data_byte = m68ki_read_8(ea+4);
3052 FLAG_Z |= (data_byte & mask_byte);
3053 m68ki_write_8(ea+4, data_byte | mask_byte);
3057 m68ki_exception_illegal();
3061 M68KMAKE_OP(bftst, 32, ., d)
3063 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3065 uint word2 = OPER_I_16();
3066 uint offset = (word2>>6)&31;
3073 offset = REG_D[offset&7];
3075 width = REG_D[width&7];
3079 width = ((width-1) & 31) + 1;
3082 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3083 mask = ROR_32(mask, offset);
3085 FLAG_N = NFLAG_32(*data<<offset);
3086 FLAG_Z = *data & mask;
3087 FLAG_V = VFLAG_CLEAR;
3088 FLAG_C = CFLAG_CLEAR;
3092 m68ki_exception_illegal();
3096 M68KMAKE_OP(bftst, 32, ., .)
3098 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3100 uint word2 = OPER_I_16();
3101 sint offset = (word2>>6)&31;
3108 uint ea = M68KMAKE_GET_EA_AY_8;
3111 offset = MAKE_INT_32(REG_D[offset&7]);
3113 width = REG_D[width&7];
3115 /* Offset is signed so we have to use ugly math =( */
3123 width = ((width-1) & 31) + 1;
3126 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3127 mask_long = mask_base >> offset;
3129 data_long = m68ki_read_32(ea);
3130 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
3131 FLAG_Z = data_long & mask_long;
3132 FLAG_V = VFLAG_CLEAR;
3133 FLAG_C = CFLAG_CLEAR;
3135 if((width + offset) > 32)
3137 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3138 data_byte = m68ki_read_8(ea+4);
3139 FLAG_Z |= (data_byte & mask_byte);
3143 m68ki_exception_illegal();
3147 M68KMAKE_OP(bkpt, 0, ., .)
3149 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
3151 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
3153 m68ki_exception_illegal();
3157 M68KMAKE_OP(bra, 8, ., .)
3159 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3160 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3161 if(REG_PC == REG_PPC)
3166 M68KMAKE_OP(bra, 16, ., .)
3168 uint offset = OPER_I_16();
3170 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3171 m68ki_branch_16(offset);
3172 if(REG_PC == REG_PPC)
3177 M68KMAKE_OP(bra, 32, ., .)
3179 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3181 uint offset = OPER_I_32();
3183 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3184 m68ki_branch_32(offset);
3185 if(REG_PC == REG_PPC)
3191 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3192 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3193 if(REG_PC == REG_PPC)
3199 M68KMAKE_OP(bset, 32, r, d)
3202 uint mask = 1 << (DX & 0x1f);
3204 FLAG_Z = *r_dst & mask;
3209 M68KMAKE_OP(bset, 8, r, .)
3211 uint ea = M68KMAKE_GET_EA_AY_8;
3212 uint src = m68ki_read_8(ea);
3213 uint mask = 1 << (DX & 7);
3215 FLAG_Z = src & mask;
3216 m68ki_write_8(ea, src | mask);
3220 M68KMAKE_OP(bset, 32, s, d)
3223 uint mask = 1 << (OPER_I_8() & 0x1f);
3225 FLAG_Z = *r_dst & mask;
3230 M68KMAKE_OP(bset, 8, s, .)
3232 uint mask = 1 << (OPER_I_8() & 7);
3233 uint ea = M68KMAKE_GET_EA_AY_8;
3234 uint src = m68ki_read_8(ea);
3236 FLAG_Z = src & mask;
3237 m68ki_write_8(ea, src | mask);
3241 M68KMAKE_OP(bsr, 8, ., .)
3243 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3244 m68ki_push_32(REG_PC);
3245 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3249 M68KMAKE_OP(bsr, 16, ., .)
3251 uint offset = OPER_I_16();
3252 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3253 m68ki_push_32(REG_PC);
3255 m68ki_branch_16(offset);
3259 M68KMAKE_OP(bsr, 32, ., .)
3261 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3263 uint offset = OPER_I_32();
3264 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3265 m68ki_push_32(REG_PC);
3267 m68ki_branch_32(offset);
3272 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3273 m68ki_push_32(REG_PC);
3274 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3279 M68KMAKE_OP(btst, 32, r, d)
3281 FLAG_Z = DY & (1 << (DX & 0x1f));
3285 M68KMAKE_OP(btst, 8, r, .)
3287 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
3291 M68KMAKE_OP(btst, 32, s, d)
3293 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
3297 M68KMAKE_OP(btst, 8, s, .)
3299 uint bit = OPER_I_8() & 7;
3301 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
3305 M68KMAKE_OP(callm, 32, ., .)
3307 /* note: watch out for pcrelative modes */
3308 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
3310 uint ea = M68KMAKE_GET_EA_AY_32;
3312 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3314 (void)ea; /* just to avoid an 'unused variable' warning */
3315 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
3316 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
3317 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
3320 m68ki_exception_illegal();
3324 M68KMAKE_OP(cas, 8, ., .)
3326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3328 uint word2 = OPER_I_16();
3329 uint ea = M68KMAKE_GET_EA_AY_8;
3330 uint dest = m68ki_read_8(ea);
3331 uint* compare = ®_D[word2 & 7];
3332 uint res = dest - MASK_OUT_ABOVE_8(*compare);
3334 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3335 FLAG_N = NFLAG_8(res);
3336 FLAG_Z = MASK_OUT_ABOVE_8(res);
3337 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
3338 FLAG_C = CFLAG_8(res);
3341 *compare = MASK_OUT_BELOW_8(*compare) | dest;
3345 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
3349 m68ki_exception_illegal();
3353 M68KMAKE_OP(cas, 16, ., .)
3355 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3357 uint word2 = OPER_I_16();
3358 uint ea = M68KMAKE_GET_EA_AY_16;
3359 uint dest = m68ki_read_16(ea);
3360 uint* compare = ®_D[word2 & 7];
3361 uint res = dest - MASK_OUT_ABOVE_16(*compare);
3363 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3364 FLAG_N = NFLAG_16(res);
3365 FLAG_Z = MASK_OUT_ABOVE_16(res);
3366 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
3367 FLAG_C = CFLAG_16(res);
3370 *compare = MASK_OUT_BELOW_16(*compare) | dest;
3374 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
3378 m68ki_exception_illegal();
3382 M68KMAKE_OP(cas, 32, ., .)
3384 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3386 uint word2 = OPER_I_16();
3387 uint ea = M68KMAKE_GET_EA_AY_32;
3388 uint dest = m68ki_read_32(ea);
3389 uint* compare = ®_D[word2 & 7];
3390 uint res = dest - *compare;
3392 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3393 FLAG_N = NFLAG_32(res);
3394 FLAG_Z = MASK_OUT_ABOVE_32(res);
3395 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
3396 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
3403 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
3407 m68ki_exception_illegal();
3411 M68KMAKE_OP(cas2, 16, ., .)
3413 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3415 uint word2 = OPER_I_32();
3416 uint* compare1 = ®_D[(word2 >> 16) & 7];
3417 uint ea1 = REG_DA[(word2 >> 28) & 15];
3418 uint dest1 = m68ki_read_16(ea1);
3419 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
3420 uint* compare2 = ®_D[word2 & 7];
3421 uint ea2 = REG_DA[(word2 >> 12) & 15];
3422 uint dest2 = m68ki_read_16(ea2);
3425 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3426 FLAG_N = NFLAG_16(res1);
3427 FLAG_Z = MASK_OUT_ABOVE_16(res1);
3428 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
3429 FLAG_C = CFLAG_16(res1);
3433 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
3435 FLAG_N = NFLAG_16(res2);
3436 FLAG_Z = MASK_OUT_ABOVE_16(res2);
3437 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
3438 FLAG_C = CFLAG_16(res2);
3443 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
3444 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
3448 *compare1 = BIT_1F(word2) ? (uint)MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
3449 *compare2 = BIT_F(word2) ? (uint)MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
3452 m68ki_exception_illegal();
3456 M68KMAKE_OP(cas2, 32, ., .)
3458 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3460 uint word2 = OPER_I_32();
3461 uint* compare1 = ®_D[(word2 >> 16) & 7];
3462 uint ea1 = REG_DA[(word2 >> 28) & 15];
3463 uint dest1 = m68ki_read_32(ea1);
3464 uint res1 = dest1 - *compare1;
3465 uint* compare2 = ®_D[word2 & 7];
3466 uint ea2 = REG_DA[(word2 >> 12) & 15];
3467 uint dest2 = m68ki_read_32(ea2);
3470 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3471 FLAG_N = NFLAG_32(res1);
3472 FLAG_Z = MASK_OUT_ABOVE_32(res1);
3473 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
3474 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
3478 res2 = dest2 - *compare2;
3480 FLAG_N = NFLAG_32(res2);
3481 FLAG_Z = MASK_OUT_ABOVE_32(res2);
3482 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
3483 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
3488 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
3489 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
3497 m68ki_exception_illegal();
3501 M68KMAKE_OP(chk, 16, ., d)
3503 sint src = MAKE_INT_16(DX);
3504 sint bound = MAKE_INT_16(DY);
3506 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3507 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3508 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3510 if(src >= 0 && src <= bound)
3514 FLAG_N = (src < 0)<<7;
3515 m68ki_exception_trap(EXCEPTION_CHK);
3519 M68KMAKE_OP(chk, 16, ., .)
3521 sint src = MAKE_INT_16(DX);
3522 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3524 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3525 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3526 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3528 if(src >= 0 && src <= bound)
3532 FLAG_N = (src < 0)<<7;
3533 m68ki_exception_trap(EXCEPTION_CHK);
3537 M68KMAKE_OP(chk, 32, ., d)
3539 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3541 sint src = MAKE_INT_32(DX);
3542 sint bound = MAKE_INT_32(DY);
3544 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3545 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3546 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3548 if(src >= 0 && src <= bound)
3552 FLAG_N = (src < 0)<<7;
3553 m68ki_exception_trap(EXCEPTION_CHK);
3556 m68ki_exception_illegal();
3560 M68KMAKE_OP(chk, 32, ., .)
3562 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3564 sint src = MAKE_INT_32(DX);
3565 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
3567 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3568 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3569 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3571 if(src >= 0 && src <= bound)
3575 FLAG_N = (src < 0)<<7;
3576 m68ki_exception_trap(EXCEPTION_CHK);
3579 m68ki_exception_illegal();
3583 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
3585 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3587 uint word2 = OPER_I_16();
3588 sint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3589 uint ea = EA_PCDI_8();
3590 sint lower_bound = m68ki_read_pcrel_8(ea);
3591 sint upper_bound = m68ki_read_pcrel_8(ea + 1);
3594 compare = (int32)(int8)compare;
3596 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3598 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3600 if(COND_CS() && BIT_B(word2))
3601 m68ki_exception_trap(EXCEPTION_CHK);
3606 m68ki_exception_illegal();
3610 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
3612 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3614 uint word2 = OPER_I_16();
3615 sint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3616 uint ea = EA_PCIX_8();
3617 sint lower_bound = m68ki_read_pcrel_8(ea);
3618 sint upper_bound = m68ki_read_pcrel_8(ea + 1);
3621 compare = (int32)(int8)compare;
3622 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||, faster operation short circuits
3624 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3626 if(COND_CS() && BIT_B(word2))
3627 m68ki_exception_trap(EXCEPTION_CHK);
3631 m68ki_exception_illegal();
3635 M68KMAKE_OP(chk2cmp2, 8, ., .)
3637 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3639 uint word2 = OPER_I_16();
3640 sint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3641 uint ea = M68KMAKE_GET_EA_AY_8;
3642 sint lower_bound = (int8)m68ki_read_8(ea);
3643 sint upper_bound = (int8)m68ki_read_8(ea + 1);
3646 compare = (int32)(int8)compare;
3648 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3650 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3652 if(COND_CS() && BIT_B(word2))
3653 m68ki_exception_trap(EXCEPTION_CHK);
3656 m68ki_exception_illegal();
3660 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
3662 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3664 uint word2 = OPER_I_16();
3665 sint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3666 uint ea = EA_PCDI_16();
3667 sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
3668 sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
3671 compare = (int32)(int16)compare;
3672 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3674 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3676 if(COND_CS() && BIT_B(word2))
3677 m68ki_exception_trap(EXCEPTION_CHK);
3680 m68ki_exception_illegal();
3684 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
3686 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3688 uint word2 = OPER_I_16();
3689 sint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3690 uint ea = EA_PCIX_16();
3691 sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
3692 sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
3695 compare = (int32)(int16)compare;
3696 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3698 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3700 if(COND_CS() && BIT_B(word2))
3701 m68ki_exception_trap(EXCEPTION_CHK);
3704 m68ki_exception_illegal();
3708 M68KMAKE_OP(chk2cmp2, 16, ., .)
3710 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3712 uint word2 = OPER_I_16();
3713 sint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3714 uint ea = M68KMAKE_GET_EA_AY_16;
3715 sint lower_bound = (int16)m68ki_read_16(ea);
3716 sint upper_bound = (int16)m68ki_read_16(ea + 2);
3719 compare = (int32)(int16)compare;
3720 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3722 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3724 if(COND_CS() && BIT_B(word2))
3725 m68ki_exception_trap(EXCEPTION_CHK);
3728 m68ki_exception_illegal();
3732 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
3734 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3736 uint word2 = OPER_I_16();
3737 sint compare = REG_DA[(word2 >> 12) & 15];
3738 uint ea = EA_PCDI_32();
3739 sint lower_bound = m68ki_read_pcrel_32(ea);
3740 sint upper_bound = m68ki_read_pcrel_32(ea + 4);
3742 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3744 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3746 if(COND_CS() && BIT_B(word2))
3747 m68ki_exception_trap(EXCEPTION_CHK);
3750 m68ki_exception_illegal();
3754 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
3756 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3758 uint word2 = OPER_I_16();
3759 sint compare = REG_DA[(word2 >> 12) & 15];
3760 uint ea = EA_PCIX_32();
3761 sint lower_bound = m68ki_read_32(ea);
3762 sint upper_bound = m68ki_read_32(ea + 4);
3764 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3766 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3768 if(COND_CS() && BIT_B(word2))
3769 m68ki_exception_trap(EXCEPTION_CHK);
3772 m68ki_exception_illegal();
3776 M68KMAKE_OP(chk2cmp2, 32, ., .)
3778 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3780 uint word2 = OPER_I_16();
3781 // JFF changed the logic. chk2/cmp2 uses signed values, not unsigned
3782 sint compare = REG_DA[(word2 >> 12) & 15];
3783 uint ea = M68KMAKE_GET_EA_AY_32;
3784 sint lower_bound = m68ki_read_32(ea);
3785 sint upper_bound = m68ki_read_32(ea + 4);
3787 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3789 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3791 if(COND_CS() && BIT_B(word2))
3792 m68ki_exception_trap(EXCEPTION_CHK);
3795 m68ki_exception_illegal();
3799 M68KMAKE_OP(clr, 8, ., d)
3803 FLAG_N = NFLAG_CLEAR;
3804 FLAG_V = VFLAG_CLEAR;
3805 FLAG_C = CFLAG_CLEAR;
3810 M68KMAKE_OP(clr, 8, ., .)
3812 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
3814 FLAG_N = NFLAG_CLEAR;
3815 FLAG_V = VFLAG_CLEAR;
3816 FLAG_C = CFLAG_CLEAR;
3821 M68KMAKE_OP(clr, 16, ., d)
3825 FLAG_N = NFLAG_CLEAR;
3826 FLAG_V = VFLAG_CLEAR;
3827 FLAG_C = CFLAG_CLEAR;
3832 M68KMAKE_OP(clr, 16, ., .)
3834 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
3836 FLAG_N = NFLAG_CLEAR;
3837 FLAG_V = VFLAG_CLEAR;
3838 FLAG_C = CFLAG_CLEAR;
3843 M68KMAKE_OP(clr, 32, ., d)
3847 FLAG_N = NFLAG_CLEAR;
3848 FLAG_V = VFLAG_CLEAR;
3849 FLAG_C = CFLAG_CLEAR;
3854 M68KMAKE_OP(clr, 32, ., .)
3856 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
3858 FLAG_N = NFLAG_CLEAR;
3859 FLAG_V = VFLAG_CLEAR;
3860 FLAG_C = CFLAG_CLEAR;
3865 M68KMAKE_OP(cmp, 8, ., d)
3867 uint src = MASK_OUT_ABOVE_8(DY);
3868 uint dst = MASK_OUT_ABOVE_8(DX);
3869 uint res = dst - src;
3871 FLAG_N = NFLAG_8(res);
3872 FLAG_Z = MASK_OUT_ABOVE_8(res);
3873 FLAG_V = VFLAG_SUB_8(src, dst, res);
3874 FLAG_C = CFLAG_8(res);
3878 M68KMAKE_OP(cmp, 8, ., .)
3880 uint src = M68KMAKE_GET_OPER_AY_8;
3881 uint dst = MASK_OUT_ABOVE_8(DX);
3882 uint res = dst - src;
3884 FLAG_N = NFLAG_8(res);
3885 FLAG_Z = MASK_OUT_ABOVE_8(res);
3886 FLAG_V = VFLAG_SUB_8(src, dst, res);
3887 FLAG_C = CFLAG_8(res);
3891 M68KMAKE_OP(cmp, 16, ., d)
3893 uint src = MASK_OUT_ABOVE_16(DY);
3894 uint dst = MASK_OUT_ABOVE_16(DX);
3895 uint res = dst - src;
3897 FLAG_N = NFLAG_16(res);
3898 FLAG_Z = MASK_OUT_ABOVE_16(res);
3899 FLAG_V = VFLAG_SUB_16(src, dst, res);
3900 FLAG_C = CFLAG_16(res);
3904 M68KMAKE_OP(cmp, 16, ., a)
3906 uint src = MASK_OUT_ABOVE_16(AY);
3907 uint dst = MASK_OUT_ABOVE_16(DX);
3908 uint res = dst - src;
3910 FLAG_N = NFLAG_16(res);
3911 FLAG_Z = MASK_OUT_ABOVE_16(res);
3912 FLAG_V = VFLAG_SUB_16(src, dst, res);
3913 FLAG_C = CFLAG_16(res);
3917 M68KMAKE_OP(cmp, 16, ., .)
3919 uint src = M68KMAKE_GET_OPER_AY_16;
3920 uint dst = MASK_OUT_ABOVE_16(DX);
3921 uint res = dst - src;
3923 FLAG_N = NFLAG_16(res);
3924 FLAG_Z = MASK_OUT_ABOVE_16(res);
3925 FLAG_V = VFLAG_SUB_16(src, dst, res);
3926 FLAG_C = CFLAG_16(res);
3930 M68KMAKE_OP(cmp, 32, ., d)
3934 uint res = dst - src;
3936 FLAG_N = NFLAG_32(res);
3937 FLAG_Z = MASK_OUT_ABOVE_32(res);
3938 FLAG_V = VFLAG_SUB_32(src, dst, res);
3939 FLAG_C = CFLAG_SUB_32(src, dst, res);
3943 M68KMAKE_OP(cmp, 32, ., a)
3947 uint res = dst - src;
3949 FLAG_N = NFLAG_32(res);
3950 FLAG_Z = MASK_OUT_ABOVE_32(res);
3951 FLAG_V = VFLAG_SUB_32(src, dst, res);
3952 FLAG_C = CFLAG_SUB_32(src, dst, res);
3956 M68KMAKE_OP(cmp, 32, ., .)
3958 uint src = M68KMAKE_GET_OPER_AY_32;
3960 uint res = dst - src;
3962 FLAG_N = NFLAG_32(res);
3963 FLAG_Z = MASK_OUT_ABOVE_32(res);
3964 FLAG_V = VFLAG_SUB_32(src, dst, res);
3965 FLAG_C = CFLAG_SUB_32(src, dst, res);
3969 M68KMAKE_OP(cmpa, 16, ., d)
3971 uint src = MAKE_INT_16(DY);
3973 uint res = dst - src;
3975 FLAG_N = NFLAG_32(res);
3976 FLAG_Z = MASK_OUT_ABOVE_32(res);
3977 FLAG_V = VFLAG_SUB_32(src, dst, res);
3978 FLAG_C = CFLAG_SUB_32(src, dst, res);
3982 M68KMAKE_OP(cmpa, 16, ., a)
3984 uint src = MAKE_INT_16(AY);
3986 uint res = dst - src;
3988 FLAG_N = NFLAG_32(res);
3989 FLAG_Z = MASK_OUT_ABOVE_32(res);
3990 FLAG_V = VFLAG_SUB_32(src, dst, res);
3991 FLAG_C = CFLAG_SUB_32(src, dst, res);
3995 M68KMAKE_OP(cmpa, 16, ., .)
3997 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3999 uint res = dst - src;
4001 FLAG_N = NFLAG_32(res);
4002 FLAG_Z = MASK_OUT_ABOVE_32(res);
4003 FLAG_V = VFLAG_SUB_32(src, dst, res);
4004 FLAG_C = CFLAG_SUB_32(src, dst, res);
4008 M68KMAKE_OP(cmpa, 32, ., d)
4012 uint res = dst - src;
4014 FLAG_N = NFLAG_32(res);
4015 FLAG_Z = MASK_OUT_ABOVE_32(res);
4016 FLAG_V = VFLAG_SUB_32(src, dst, res);
4017 FLAG_C = CFLAG_SUB_32(src, dst, res);
4021 M68KMAKE_OP(cmpa, 32, ., a)
4025 uint res = dst - src;
4027 FLAG_N = NFLAG_32(res);
4028 FLAG_Z = MASK_OUT_ABOVE_32(res);
4029 FLAG_V = VFLAG_SUB_32(src, dst, res);
4030 FLAG_C = CFLAG_SUB_32(src, dst, res);
4034 M68KMAKE_OP(cmpa, 32, ., .)
4036 uint src = M68KMAKE_GET_OPER_AY_32;
4038 uint res = dst - src;
4040 FLAG_N = NFLAG_32(res);
4041 FLAG_Z = MASK_OUT_ABOVE_32(res);
4042 FLAG_V = VFLAG_SUB_32(src, dst, res);
4043 FLAG_C = CFLAG_SUB_32(src, dst, res);
4047 M68KMAKE_OP(cmpi, 8, ., d)
4049 uint src = OPER_I_8();
4050 uint dst = MASK_OUT_ABOVE_8(DY);
4051 uint res = dst - src;
4053 FLAG_N = NFLAG_8(res);
4054 FLAG_Z = MASK_OUT_ABOVE_8(res);
4055 FLAG_V = VFLAG_SUB_8(src, dst, res);
4056 FLAG_C = CFLAG_8(res);
4060 M68KMAKE_OP(cmpi, 8, ., .)
4062 uint src = OPER_I_8();
4063 uint dst = M68KMAKE_GET_OPER_AY_8;
4064 uint res = dst - src;
4066 FLAG_N = NFLAG_8(res);
4067 FLAG_Z = MASK_OUT_ABOVE_8(res);
4068 FLAG_V = VFLAG_SUB_8(src, dst, res);
4069 FLAG_C = CFLAG_8(res);
4073 M68KMAKE_OP(cmpi, 8, ., pcdi)
4075 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4077 uint src = OPER_I_8();
4078 uint dst = OPER_PCDI_8();
4079 uint res = dst - src;
4081 FLAG_N = NFLAG_8(res);
4082 FLAG_Z = MASK_OUT_ABOVE_8(res);
4083 FLAG_V = VFLAG_SUB_8(src, dst, res);
4084 FLAG_C = CFLAG_8(res);
4087 m68ki_exception_illegal();
4091 M68KMAKE_OP(cmpi, 8, ., pcix)
4093 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4095 uint src = OPER_I_8();
4096 uint dst = OPER_PCIX_8();
4097 uint res = dst - src;
4099 FLAG_N = NFLAG_8(res);
4100 FLAG_Z = MASK_OUT_ABOVE_8(res);
4101 FLAG_V = VFLAG_SUB_8(src, dst, res);
4102 FLAG_C = CFLAG_8(res);
4105 m68ki_exception_illegal();
4109 M68KMAKE_OP(cmpi, 16, ., d)
4111 uint src = OPER_I_16();
4112 uint dst = MASK_OUT_ABOVE_16(DY);
4113 uint res = dst - src;
4115 FLAG_N = NFLAG_16(res);
4116 FLAG_Z = MASK_OUT_ABOVE_16(res);
4117 FLAG_V = VFLAG_SUB_16(src, dst, res);
4118 FLAG_C = CFLAG_16(res);
4122 M68KMAKE_OP(cmpi, 16, ., .)
4124 uint src = OPER_I_16();
4125 uint dst = M68KMAKE_GET_OPER_AY_16;
4126 uint res = dst - src;
4128 FLAG_N = NFLAG_16(res);
4129 FLAG_Z = MASK_OUT_ABOVE_16(res);
4130 FLAG_V = VFLAG_SUB_16(src, dst, res);
4131 FLAG_C = CFLAG_16(res);
4135 M68KMAKE_OP(cmpi, 16, ., pcdi)
4137 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4139 uint src = OPER_I_16();
4140 uint dst = OPER_PCDI_16();
4141 uint res = dst - src;
4143 FLAG_N = NFLAG_16(res);
4144 FLAG_Z = MASK_OUT_ABOVE_16(res);
4145 FLAG_V = VFLAG_SUB_16(src, dst, res);
4146 FLAG_C = CFLAG_16(res);
4149 m68ki_exception_illegal();
4153 M68KMAKE_OP(cmpi, 16, ., pcix)
4155 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4157 uint src = OPER_I_16();
4158 uint dst = OPER_PCIX_16();
4159 uint res = dst - src;
4161 FLAG_N = NFLAG_16(res);
4162 FLAG_Z = MASK_OUT_ABOVE_16(res);
4163 FLAG_V = VFLAG_SUB_16(src, dst, res);
4164 FLAG_C = CFLAG_16(res);
4167 m68ki_exception_illegal();
4171 M68KMAKE_OP(cmpi, 32, ., d)
4173 uint src = OPER_I_32();
4175 uint res = dst - src;
4177 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
4178 FLAG_N = NFLAG_32(res);
4179 FLAG_Z = MASK_OUT_ABOVE_32(res);
4180 FLAG_V = VFLAG_SUB_32(src, dst, res);
4181 FLAG_C = CFLAG_SUB_32(src, dst, res);
4185 M68KMAKE_OP(cmpi, 32, ., .)
4187 uint src = OPER_I_32();
4188 uint dst = M68KMAKE_GET_OPER_AY_32;
4189 uint res = dst - src;
4191 FLAG_N = NFLAG_32(res);
4192 FLAG_Z = MASK_OUT_ABOVE_32(res);
4193 FLAG_V = VFLAG_SUB_32(src, dst, res);
4194 FLAG_C = CFLAG_SUB_32(src, dst, res);
4198 M68KMAKE_OP(cmpi, 32, ., pcdi)
4200 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4202 uint src = OPER_I_32();
4203 uint dst = OPER_PCDI_32();
4204 uint res = dst - src;
4206 FLAG_N = NFLAG_32(res);
4207 FLAG_Z = MASK_OUT_ABOVE_32(res);
4208 FLAG_V = VFLAG_SUB_32(src, dst, res);
4209 FLAG_C = CFLAG_SUB_32(src, dst, res);
4212 m68ki_exception_illegal();
4216 M68KMAKE_OP(cmpi, 32, ., pcix)
4218 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4220 uint src = OPER_I_32();
4221 uint dst = OPER_PCIX_32();
4222 uint res = dst - src;
4224 FLAG_N = NFLAG_32(res);
4225 FLAG_Z = MASK_OUT_ABOVE_32(res);
4226 FLAG_V = VFLAG_SUB_32(src, dst, res);
4227 FLAG_C = CFLAG_SUB_32(src, dst, res);
4230 m68ki_exception_illegal();
4234 M68KMAKE_OP(cmpm, 8, ., ax7)
4236 uint src = OPER_AY_PI_8();
4237 uint dst = OPER_A7_PI_8();
4238 uint res = dst - src;
4240 FLAG_N = NFLAG_8(res);
4241 FLAG_Z = MASK_OUT_ABOVE_8(res);
4242 FLAG_V = VFLAG_SUB_8(src, dst, res);
4243 FLAG_C = CFLAG_8(res);
4247 M68KMAKE_OP(cmpm, 8, ., ay7)
4249 uint src = OPER_A7_PI_8();
4250 uint dst = OPER_AX_PI_8();
4251 uint res = dst - src;
4253 FLAG_N = NFLAG_8(res);
4254 FLAG_Z = MASK_OUT_ABOVE_8(res);
4255 FLAG_V = VFLAG_SUB_8(src, dst, res);
4256 FLAG_C = CFLAG_8(res);
4260 M68KMAKE_OP(cmpm, 8, ., axy7)
4262 uint src = OPER_A7_PI_8();
4263 uint dst = OPER_A7_PI_8();
4264 uint res = dst - src;
4266 FLAG_N = NFLAG_8(res);
4267 FLAG_Z = MASK_OUT_ABOVE_8(res);
4268 FLAG_V = VFLAG_SUB_8(src, dst, res);
4269 FLAG_C = CFLAG_8(res);
4273 M68KMAKE_OP(cmpm, 8, ., .)
4275 uint src = OPER_AY_PI_8();
4276 uint dst = OPER_AX_PI_8();
4277 uint res = dst - src;
4279 FLAG_N = NFLAG_8(res);
4280 FLAG_Z = MASK_OUT_ABOVE_8(res);
4281 FLAG_V = VFLAG_SUB_8(src, dst, res);
4282 FLAG_C = CFLAG_8(res);
4286 M68KMAKE_OP(cmpm, 16, ., .)
4288 uint src = OPER_AY_PI_16();
4289 uint dst = OPER_AX_PI_16();
4290 uint res = dst - src;
4292 FLAG_N = NFLAG_16(res);
4293 FLAG_Z = MASK_OUT_ABOVE_16(res);
4294 FLAG_V = VFLAG_SUB_16(src, dst, res);
4295 FLAG_C = CFLAG_16(res);
4299 M68KMAKE_OP(cmpm, 32, ., .)
4301 uint src = OPER_AY_PI_32();
4302 uint dst = OPER_AX_PI_32();
4303 uint res = dst - src;
4305 FLAG_N = NFLAG_32(res);
4306 FLAG_Z = MASK_OUT_ABOVE_32(res);
4307 FLAG_V = VFLAG_SUB_32(src, dst, res);
4308 FLAG_C = CFLAG_SUB_32(src, dst, res);
4312 M68KMAKE_OP(cpbcc, 32, ., .)
4314 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4316 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4317 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4318 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4321 m68ki_exception_1111();
4325 M68KMAKE_OP(cpdbcc, 32, ., .)
4327 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4329 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4330 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4331 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4334 m68ki_exception_1111();
4338 M68KMAKE_OP(cpgen, 32, ., .)
4340 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4342 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4343 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4344 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4347 m68ki_exception_1111();
4351 M68KMAKE_OP(cpscc, 32, ., .)
4353 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4355 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4356 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4357 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4360 m68ki_exception_1111();
4364 M68KMAKE_OP(cptrapcc, 32, ., .)
4366 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4368 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4369 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4370 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4371 // JFF: unsupported, but at least if the trap doesn't occur, app should still work, so at least PC increase is correct
4375 m68ki_exception_1111();
4378 M68KMAKE_OP(ftrapcc,32, ., .)
4384 m68ki_exception_1111();
4388 M68KMAKE_OP(dbt, 16, ., .)
4394 M68KMAKE_OP(dbf, 16, ., .)
4397 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4399 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4402 uint offset = OPER_I_16();
4404 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4405 m68ki_branch_16(offset);
4406 USE_CYCLES(CYC_DBCC_F_NOEXP);
4410 USE_CYCLES(CYC_DBCC_F_EXP);
4414 M68KMAKE_OP(dbcc, 16, ., .)
4419 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4421 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4424 uint offset = OPER_I_16();
4426 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4427 m68ki_branch_16(offset);
4428 USE_CYCLES(CYC_DBCC_F_NOEXP);
4432 USE_CYCLES(CYC_DBCC_F_EXP);
4439 M68KMAKE_OP(divs, 16, ., d)
4442 sint src = MAKE_INT_16(DY);
4448 if((uint32)*r_dst == 0x80000000 && src == -1)
4451 FLAG_N = NFLAG_CLEAR;
4452 FLAG_V = VFLAG_CLEAR;
4453 FLAG_C = CFLAG_CLEAR;
4458 quotient = MAKE_INT_32(*r_dst) / src;
4459 remainder = MAKE_INT_32(*r_dst) % src;
4461 if(quotient == MAKE_INT_16(quotient))
4464 FLAG_N = NFLAG_16(quotient);
4465 FLAG_V = VFLAG_CLEAR;
4466 FLAG_C = CFLAG_CLEAR;
4467 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4473 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4477 M68KMAKE_OP(divs, 16, ., .)
4480 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4486 if((uint32)*r_dst == 0x80000000 && src == -1)
4489 FLAG_N = NFLAG_CLEAR;
4490 FLAG_V = VFLAG_CLEAR;
4491 FLAG_C = CFLAG_CLEAR;
4496 quotient = MAKE_INT_32(*r_dst) / src;
4497 remainder = MAKE_INT_32(*r_dst) % src;
4499 if(quotient == MAKE_INT_16(quotient))
4502 FLAG_N = NFLAG_16(quotient);
4503 FLAG_V = VFLAG_CLEAR;
4504 FLAG_C = CFLAG_CLEAR;
4505 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4511 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4515 M68KMAKE_OP(divu, 16, ., d)
4518 uint src = MASK_OUT_ABOVE_16(DY);
4522 uint quotient = *r_dst / src;
4523 uint remainder = *r_dst % src;
4525 if(quotient < 0x10000)
4528 FLAG_N = NFLAG_16(quotient);
4529 FLAG_V = VFLAG_CLEAR;
4530 FLAG_C = CFLAG_CLEAR;
4531 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4537 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4541 M68KMAKE_OP(divu, 16, ., .)
4544 uint src = M68KMAKE_GET_OPER_AY_16;
4548 uint quotient = *r_dst / src;
4549 uint remainder = *r_dst % src;
4551 if(quotient < 0x10000)
4554 FLAG_N = NFLAG_16(quotient);
4555 FLAG_V = VFLAG_CLEAR;
4556 FLAG_C = CFLAG_CLEAR;
4557 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4563 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4567 M68KMAKE_OP(divl, 32, ., d)
4571 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4573 uint word2 = OPER_I_16();
4574 uint64 divisor = DY;
4575 uint64 dividend = 0;
4576 uint64 quotient = 0;
4577 uint64 remainder = 0;
4581 if(BIT_A(word2)) /* 64 bit */
4583 dividend = REG_D[word2 & 7];
4585 dividend |= REG_D[(word2 >> 12) & 7];
4587 if(BIT_B(word2)) /* signed */
4589 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4590 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4591 if((sint64)quotient != (sint64)((sint32)quotient))
4599 quotient = dividend / divisor;
4600 if(quotient > 0xffffffff)
4605 remainder = dividend % divisor;
4610 dividend = REG_D[(word2 >> 12) & 7];
4611 if(BIT_B(word2)) /* signed */
4613 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4614 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4618 quotient = dividend / divisor;
4619 remainder = dividend % divisor;
4623 REG_D[word2 & 7] = remainder;
4624 REG_D[(word2 >> 12) & 7] = quotient;
4626 FLAG_N = NFLAG_32(quotient);
4628 FLAG_V = VFLAG_CLEAR;
4629 FLAG_C = CFLAG_CLEAR;
4632 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4635 m68ki_exception_illegal();
4639 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4641 uint word2 = OPER_I_16();
4643 uint dividend_hi = REG_D[word2 & 7];
4644 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4647 uint dividend_neg = 0;
4648 uint divisor_neg = 0;
4654 /* quad / long : long quotient, long remainder */
4657 if(BIT_B(word2)) /* signed */
4659 /* special case in signed divide */
4660 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4662 REG_D[word2 & 7] = 0;
4663 REG_D[(word2 >> 12) & 7] = 0x80000000;
4666 FLAG_Z = ZFLAG_CLEAR;
4667 FLAG_V = VFLAG_CLEAR;
4668 FLAG_C = CFLAG_CLEAR;
4671 if(GET_MSB_32(dividend_hi))
4674 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4675 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4677 if(GET_MSB_32(divisor))
4680 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4685 /* if the upper long is greater than the divisor, we're overflowing. */
4686 if(dividend_hi >= divisor)
4692 for(i = 31; i >= 0; i--)
4695 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4696 if(remainder >= divisor)
4698 remainder -= divisor;
4702 for(i = 31; i >= 0; i--)
4705 overflow = GET_MSB_32(remainder);
4706 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4707 if(remainder >= divisor || overflow)
4709 remainder -= divisor;
4714 if(BIT_B(word2)) /* signed */
4716 if(quotient > 0x7fffffff)
4723 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4724 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4727 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4730 REG_D[word2 & 7] = remainder;
4731 REG_D[(word2 >> 12) & 7] = quotient;
4733 FLAG_N = NFLAG_32(quotient);
4735 FLAG_V = VFLAG_CLEAR;
4736 FLAG_C = CFLAG_CLEAR;
4740 /* long / long: long quotient, maybe long remainder */
4741 if(BIT_B(word2)) /* signed */
4743 /* Special case in divide */
4744 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4747 FLAG_Z = ZFLAG_CLEAR;
4748 FLAG_V = VFLAG_CLEAR;
4749 FLAG_C = CFLAG_CLEAR;
4750 REG_D[(word2 >> 12) & 7] = 0x80000000;
4751 REG_D[word2 & 7] = 0;
4754 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4755 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4759 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4760 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4763 FLAG_N = NFLAG_32(quotient);
4765 FLAG_V = VFLAG_CLEAR;
4766 FLAG_C = CFLAG_CLEAR;
4769 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4772 m68ki_exception_illegal();
4778 M68KMAKE_OP(divl, 32, ., .)
4782 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4784 uint word2 = OPER_I_16();
4785 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
4786 uint64 dividend = 0;
4787 uint64 quotient = 0;
4788 uint64 remainder = 0;
4792 if(BIT_A(word2)) /* 64 bit */
4794 dividend = REG_D[word2 & 7];
4796 dividend |= REG_D[(word2 >> 12) & 7];
4798 if(BIT_B(word2)) /* signed */
4800 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4801 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4802 if((sint64)quotient != (sint64)((sint32)quotient))
4810 quotient = dividend / divisor;
4811 if(quotient > 0xffffffff)
4816 remainder = dividend % divisor;
4821 dividend = REG_D[(word2 >> 12) & 7];
4822 if(BIT_B(word2)) /* signed */
4824 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4825 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4829 quotient = dividend / divisor;
4830 remainder = dividend % divisor;
4834 REG_D[word2 & 7] = remainder;
4835 REG_D[(word2 >> 12) & 7] = quotient;
4837 FLAG_N = NFLAG_32(quotient);
4839 FLAG_V = VFLAG_CLEAR;
4840 FLAG_C = CFLAG_CLEAR;
4843 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4846 m68ki_exception_illegal();
4850 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4852 uint word2 = OPER_I_16();
4853 uint divisor = M68KMAKE_GET_OPER_AY_32;
4854 uint dividend_hi = REG_D[word2 & 7];
4855 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4858 uint dividend_neg = 0;
4859 uint divisor_neg = 0;
4865 /* quad / long : long quotient, long remainder */
4868 if(BIT_B(word2)) /* signed */
4870 /* special case in signed divide */
4871 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4873 REG_D[word2 & 7] = 0;
4874 REG_D[(word2 >> 12) & 7] = 0x80000000;
4877 FLAG_Z = ZFLAG_CLEAR;
4878 FLAG_V = VFLAG_CLEAR;
4879 FLAG_C = CFLAG_CLEAR;
4882 if(GET_MSB_32(dividend_hi))
4885 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4886 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4888 if(GET_MSB_32(divisor))
4891 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4896 /* if the upper long is greater than the divisor, we're overflowing. */
4897 if(dividend_hi >= divisor)
4903 for(i = 31; i >= 0; i--)
4906 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4907 if(remainder >= divisor)
4909 remainder -= divisor;
4913 for(i = 31; i >= 0; i--)
4916 overflow = GET_MSB_32(remainder);
4917 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4918 if(remainder >= divisor || overflow)
4920 remainder -= divisor;
4925 if(BIT_B(word2)) /* signed */
4927 if(quotient > 0x7fffffff)
4934 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4935 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4938 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4941 REG_D[word2 & 7] = remainder;
4942 REG_D[(word2 >> 12) & 7] = quotient;
4944 FLAG_N = NFLAG_32(quotient);
4946 FLAG_V = VFLAG_CLEAR;
4947 FLAG_C = CFLAG_CLEAR;
4951 /* long / long: long quotient, maybe long remainder */
4952 if(BIT_B(word2)) /* signed */
4954 /* Special case in divide */
4955 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4958 FLAG_Z = ZFLAG_CLEAR;
4959 FLAG_V = VFLAG_CLEAR;
4960 FLAG_C = CFLAG_CLEAR;
4961 REG_D[(word2 >> 12) & 7] = 0x80000000;
4962 REG_D[word2 & 7] = 0;
4965 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4966 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4970 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4971 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4974 FLAG_N = NFLAG_32(quotient);
4976 FLAG_V = VFLAG_CLEAR;
4977 FLAG_C = CFLAG_CLEAR;
4980 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4983 m68ki_exception_illegal();
4989 M68KMAKE_OP(eor, 8, ., d)
4991 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
4993 FLAG_N = NFLAG_8(res);
4995 FLAG_C = CFLAG_CLEAR;
4996 FLAG_V = VFLAG_CLEAR;
5000 M68KMAKE_OP(eor, 8, ., .)
5002 uint ea = M68KMAKE_GET_EA_AY_8;
5003 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
5005 m68ki_write_8(ea, res);
5007 FLAG_N = NFLAG_8(res);
5009 FLAG_C = CFLAG_CLEAR;
5010 FLAG_V = VFLAG_CLEAR;
5014 M68KMAKE_OP(eor, 16, ., d)
5016 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
5018 FLAG_N = NFLAG_16(res);
5020 FLAG_C = CFLAG_CLEAR;
5021 FLAG_V = VFLAG_CLEAR;
5025 M68KMAKE_OP(eor, 16, ., .)
5027 uint ea = M68KMAKE_GET_EA_AY_16;
5028 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
5030 m68ki_write_16(ea, res);
5032 FLAG_N = NFLAG_16(res);
5034 FLAG_C = CFLAG_CLEAR;
5035 FLAG_V = VFLAG_CLEAR;
5039 M68KMAKE_OP(eor, 32, ., d)
5041 uint res = DY ^= DX;
5043 FLAG_N = NFLAG_32(res);
5045 FLAG_C = CFLAG_CLEAR;
5046 FLAG_V = VFLAG_CLEAR;
5050 M68KMAKE_OP(eor, 32, ., .)
5052 uint ea = M68KMAKE_GET_EA_AY_32;
5053 uint res = DX ^ m68ki_read_32(ea);
5055 m68ki_write_32(ea, res);
5057 FLAG_N = NFLAG_32(res);
5059 FLAG_C = CFLAG_CLEAR;
5060 FLAG_V = VFLAG_CLEAR;
5064 M68KMAKE_OP(eori, 8, ., d)
5066 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
5068 FLAG_N = NFLAG_8(res);
5070 FLAG_C = CFLAG_CLEAR;
5071 FLAG_V = VFLAG_CLEAR;
5075 M68KMAKE_OP(eori, 8, ., .)
5077 uint src = OPER_I_8();
5078 uint ea = M68KMAKE_GET_EA_AY_8;
5079 uint res = src ^ m68ki_read_8(ea);
5081 m68ki_write_8(ea, res);
5083 FLAG_N = NFLAG_8(res);
5085 FLAG_C = CFLAG_CLEAR;
5086 FLAG_V = VFLAG_CLEAR;
5090 M68KMAKE_OP(eori, 16, ., d)
5092 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
5094 FLAG_N = NFLAG_16(res);
5096 FLAG_C = CFLAG_CLEAR;
5097 FLAG_V = VFLAG_CLEAR;
5101 M68KMAKE_OP(eori, 16, ., .)
5103 uint src = OPER_I_16();
5104 uint ea = M68KMAKE_GET_EA_AY_16;
5105 uint res = src ^ m68ki_read_16(ea);
5107 m68ki_write_16(ea, res);
5109 FLAG_N = NFLAG_16(res);
5111 FLAG_C = CFLAG_CLEAR;
5112 FLAG_V = VFLAG_CLEAR;
5116 M68KMAKE_OP(eori, 32, ., d)
5118 uint res = DY ^= OPER_I_32();
5120 FLAG_N = NFLAG_32(res);
5122 FLAG_C = CFLAG_CLEAR;
5123 FLAG_V = VFLAG_CLEAR;
5127 M68KMAKE_OP(eori, 32, ., .)
5129 uint src = OPER_I_32();
5130 uint ea = M68KMAKE_GET_EA_AY_32;
5131 uint res = src ^ m68ki_read_32(ea);
5133 m68ki_write_32(ea, res);
5135 FLAG_N = NFLAG_32(res);
5137 FLAG_C = CFLAG_CLEAR;
5138 FLAG_V = VFLAG_CLEAR;
5142 M68KMAKE_OP(eori, 16, toc, .)
5144 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8());
5148 M68KMAKE_OP(eori, 16, tos, .)
5152 uint src = OPER_I_16();
5153 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5154 m68ki_set_sr(m68ki_get_sr() ^ src);
5157 m68ki_exception_privilege_violation();
5161 M68KMAKE_OP(exg, 32, dd, .)
5171 M68KMAKE_OP(exg, 32, aa, .)
5181 M68KMAKE_OP(exg, 32, da, .)
5191 M68KMAKE_OP(ext, 16, ., .)
5195 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
5197 FLAG_N = NFLAG_16(*r_dst);
5198 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
5199 FLAG_V = VFLAG_CLEAR;
5200 FLAG_C = CFLAG_CLEAR;
5204 M68KMAKE_OP(ext, 32, ., .)
5208 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
5210 FLAG_N = NFLAG_32(*r_dst);
5212 FLAG_V = VFLAG_CLEAR;
5213 FLAG_C = CFLAG_CLEAR;
5217 M68KMAKE_OP(extb, 32, ., .)
5219 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5223 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
5225 FLAG_N = NFLAG_32(*r_dst);
5227 FLAG_V = VFLAG_CLEAR;
5228 FLAG_C = CFLAG_CLEAR;
5231 m68ki_exception_illegal();
5235 M68KMAKE_OP(illegal, 0, ., .)
5237 m68ki_exception_illegal();
5240 M68KMAKE_OP(jmp, 32, ., .)
5242 m68ki_jump(M68KMAKE_GET_EA_AY_32);
5243 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5244 if(REG_PC == REG_PPC)
5249 M68KMAKE_OP(jsr, 32, ., .)
5251 uint ea = M68KMAKE_GET_EA_AY_32;
5252 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5253 m68ki_push_32(REG_PC);
5258 M68KMAKE_OP(lea, 32, ., .)
5260 AX = M68KMAKE_GET_EA_AY_32;
5264 M68KMAKE_OP(link, 16, ., a7)
5267 m68ki_write_32(REG_A[7], REG_A[7]);
5268 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5272 M68KMAKE_OP(link, 16, ., .)
5276 m68ki_push_32(*r_dst);
5278 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5282 M68KMAKE_OP(link, 32, ., a7)
5284 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5287 m68ki_write_32(REG_A[7], REG_A[7]);
5288 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5291 m68ki_exception_illegal();
5295 M68KMAKE_OP(link, 32, ., .)
5297 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5301 m68ki_push_32(*r_dst);
5303 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5306 m68ki_exception_illegal();
5310 M68KMAKE_OP(lsr, 8, s, .)
5313 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5314 uint src = MASK_OUT_ABOVE_8(*r_dst);
5315 uint res = src >> shift;
5318 USE_CYCLES(shift<<CYC_SHIFT);
5320 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5322 FLAG_N = NFLAG_CLEAR;
5324 FLAG_X = FLAG_C = src << (9-shift);
5325 FLAG_V = VFLAG_CLEAR;
5329 M68KMAKE_OP(lsr, 16, s, .)
5332 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5333 uint src = MASK_OUT_ABOVE_16(*r_dst);
5334 uint res = src >> shift;
5337 USE_CYCLES(shift<<CYC_SHIFT);
5339 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5341 FLAG_N = NFLAG_CLEAR;
5343 FLAG_X = FLAG_C = src << (9-shift);
5344 FLAG_V = VFLAG_CLEAR;
5348 M68KMAKE_OP(lsr, 32, s, .)
5351 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5353 uint res = src >> shift;
5356 USE_CYCLES(shift<<CYC_SHIFT);
5360 FLAG_N = NFLAG_CLEAR;
5362 FLAG_X = FLAG_C = src << (9-shift);
5363 FLAG_V = VFLAG_CLEAR;
5367 M68KMAKE_OP(lsr, 8, r, .)
5370 uint shift = DX & 0x3f;
5371 uint src = MASK_OUT_ABOVE_8(*r_dst);
5372 uint res = src >> shift;
5376 USE_CYCLES(shift<<CYC_SHIFT);
5380 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5381 FLAG_X = FLAG_C = src << (9-shift);
5382 FLAG_N = NFLAG_CLEAR;
5384 FLAG_V = VFLAG_CLEAR;
5388 *r_dst &= 0xffffff00;
5389 FLAG_X = XFLAG_CLEAR;
5390 FLAG_C = CFLAG_CLEAR;
5391 FLAG_N = NFLAG_CLEAR;
5393 FLAG_V = VFLAG_CLEAR;
5397 FLAG_C = CFLAG_CLEAR;
5398 FLAG_N = NFLAG_8(src);
5400 FLAG_V = VFLAG_CLEAR;
5404 M68KMAKE_OP(lsr, 16, r, .)
5407 uint shift = DX & 0x3f;
5408 uint src = MASK_OUT_ABOVE_16(*r_dst);
5409 uint res = src >> shift;
5413 USE_CYCLES(shift<<CYC_SHIFT);
5417 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5418 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5419 FLAG_N = NFLAG_CLEAR;
5421 FLAG_V = VFLAG_CLEAR;
5425 *r_dst &= 0xffff0000;
5426 FLAG_X = XFLAG_CLEAR;
5427 FLAG_C = CFLAG_CLEAR;
5428 FLAG_N = NFLAG_CLEAR;
5430 FLAG_V = VFLAG_CLEAR;
5434 FLAG_C = CFLAG_CLEAR;
5435 FLAG_N = NFLAG_16(src);
5437 FLAG_V = VFLAG_CLEAR;
5441 M68KMAKE_OP(lsr, 32, r, .)
5444 uint shift = DX & 0x3f;
5446 uint res = src >> shift;
5450 USE_CYCLES(shift<<CYC_SHIFT);
5455 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5456 FLAG_N = NFLAG_CLEAR;
5458 FLAG_V = VFLAG_CLEAR;
5463 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
5464 FLAG_N = NFLAG_CLEAR;
5466 FLAG_V = VFLAG_CLEAR;
5470 FLAG_C = CFLAG_CLEAR;
5471 FLAG_N = NFLAG_32(src);
5473 FLAG_V = VFLAG_CLEAR;
5477 M68KMAKE_OP(lsr, 16, ., .)
5479 uint ea = M68KMAKE_GET_EA_AY_16;
5480 uint src = m68ki_read_16(ea);
5481 uint res = src >> 1;
5483 m68ki_write_16(ea, res);
5485 FLAG_N = NFLAG_CLEAR;
5487 FLAG_C = FLAG_X = src << 8;
5488 FLAG_V = VFLAG_CLEAR;
5492 M68KMAKE_OP(lsl, 8, s, .)
5495 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5496 uint src = MASK_OUT_ABOVE_8(*r_dst);
5497 uint res = MASK_OUT_ABOVE_8(src << shift);
5500 USE_CYCLES(shift<<CYC_SHIFT);
5502 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5504 FLAG_N = NFLAG_8(res);
5506 FLAG_X = FLAG_C = src << shift;
5507 FLAG_V = VFLAG_CLEAR;
5511 M68KMAKE_OP(lsl, 16, s, .)
5514 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5515 uint src = MASK_OUT_ABOVE_16(*r_dst);
5516 uint res = MASK_OUT_ABOVE_16(src << shift);
5519 USE_CYCLES(shift<<CYC_SHIFT);
5521 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5523 FLAG_N = NFLAG_16(res);
5525 FLAG_X = FLAG_C = src >> (8-shift);
5526 FLAG_V = VFLAG_CLEAR;
5530 M68KMAKE_OP(lsl, 32, s, .)
5533 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5535 uint res = MASK_OUT_ABOVE_32(src << shift);
5538 USE_CYCLES(shift<<CYC_SHIFT);
5542 FLAG_N = NFLAG_32(res);
5544 FLAG_X = FLAG_C = src >> (24-shift);
5545 FLAG_V = VFLAG_CLEAR;
5549 M68KMAKE_OP(lsl, 8, r, .)
5552 uint shift = DX & 0x3f;
5553 uint src = MASK_OUT_ABOVE_8(*r_dst);
5554 uint res = MASK_OUT_ABOVE_8(src << shift);
5558 USE_CYCLES(shift<<CYC_SHIFT);
5562 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5563 FLAG_X = FLAG_C = src << shift;
5564 FLAG_N = NFLAG_8(res);
5566 FLAG_V = VFLAG_CLEAR;
5570 *r_dst &= 0xffffff00;
5571 FLAG_X = XFLAG_CLEAR;
5572 FLAG_C = CFLAG_CLEAR;
5573 FLAG_N = NFLAG_CLEAR;
5575 FLAG_V = VFLAG_CLEAR;
5579 FLAG_C = CFLAG_CLEAR;
5580 FLAG_N = NFLAG_8(src);
5582 FLAG_V = VFLAG_CLEAR;
5586 M68KMAKE_OP(lsl, 16, r, .)
5589 uint shift = DX & 0x3f;
5590 uint src = MASK_OUT_ABOVE_16(*r_dst);
5591 uint res = MASK_OUT_ABOVE_16(src << shift);
5595 USE_CYCLES(shift<<CYC_SHIFT);
5599 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5600 FLAG_X = FLAG_C = (src << shift) >> 8;
5601 FLAG_N = NFLAG_16(res);
5603 FLAG_V = VFLAG_CLEAR;
5607 *r_dst &= 0xffff0000;
5608 FLAG_X = XFLAG_CLEAR;
5609 FLAG_C = CFLAG_CLEAR;
5610 FLAG_N = NFLAG_CLEAR;
5612 FLAG_V = VFLAG_CLEAR;
5616 FLAG_C = CFLAG_CLEAR;
5617 FLAG_N = NFLAG_16(src);
5619 FLAG_V = VFLAG_CLEAR;
5623 M68KMAKE_OP(lsl, 32, r, .)
5626 uint shift = DX & 0x3f;
5628 uint res = MASK_OUT_ABOVE_32(src << shift);
5632 USE_CYCLES(shift<<CYC_SHIFT);
5637 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
5638 FLAG_N = NFLAG_32(res);
5640 FLAG_V = VFLAG_CLEAR;
5645 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
5646 FLAG_N = NFLAG_CLEAR;
5648 FLAG_V = VFLAG_CLEAR;
5652 FLAG_C = CFLAG_CLEAR;
5653 FLAG_N = NFLAG_32(src);
5655 FLAG_V = VFLAG_CLEAR;
5659 M68KMAKE_OP(lsl, 16, ., .)
5661 uint ea = M68KMAKE_GET_EA_AY_16;
5662 uint src = m68ki_read_16(ea);
5663 uint res = MASK_OUT_ABOVE_16(src << 1);
5665 m68ki_write_16(ea, res);
5667 FLAG_N = NFLAG_16(res);
5669 FLAG_X = FLAG_C = src >> 7;
5670 FLAG_V = VFLAG_CLEAR;
5674 M68KMAKE_OP(move, 8, d, d)
5676 uint res = MASK_OUT_ABOVE_8(DY);
5679 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5681 FLAG_N = NFLAG_8(res);
5683 FLAG_V = VFLAG_CLEAR;
5684 FLAG_C = CFLAG_CLEAR;
5688 M68KMAKE_OP(move, 8, d, .)
5690 uint res = M68KMAKE_GET_OPER_AY_8;
5693 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5695 FLAG_N = NFLAG_8(res);
5697 FLAG_V = VFLAG_CLEAR;
5698 FLAG_C = CFLAG_CLEAR;
5702 M68KMAKE_OP(move, 8, ai, d)
5704 uint res = MASK_OUT_ABOVE_8(DY);
5705 uint ea = EA_AX_AI_8();
5707 m68ki_write_8(ea, res);
5709 FLAG_N = NFLAG_8(res);
5711 FLAG_V = VFLAG_CLEAR;
5712 FLAG_C = CFLAG_CLEAR;
5716 M68KMAKE_OP(move, 8, ai, .)
5718 uint res = M68KMAKE_GET_OPER_AY_8;
5719 uint ea = EA_AX_AI_8();
5721 m68ki_write_8(ea, res);
5723 FLAG_N = NFLAG_8(res);
5725 FLAG_V = VFLAG_CLEAR;
5726 FLAG_C = CFLAG_CLEAR;
5730 M68KMAKE_OP(move, 8, pi7, d)
5732 uint res = MASK_OUT_ABOVE_8(DY);
5733 uint ea = EA_A7_PI_8();
5735 m68ki_write_8(ea, res);
5737 FLAG_N = NFLAG_8(res);
5739 FLAG_V = VFLAG_CLEAR;
5740 FLAG_C = CFLAG_CLEAR;
5744 M68KMAKE_OP(move, 8, pi, d)
5746 uint res = MASK_OUT_ABOVE_8(DY);
5747 uint ea = EA_AX_PI_8();
5749 m68ki_write_8(ea, res);
5751 FLAG_N = NFLAG_8(res);
5753 FLAG_V = VFLAG_CLEAR;
5754 FLAG_C = CFLAG_CLEAR;
5758 M68KMAKE_OP(move, 8, pi7, .)
5760 uint res = M68KMAKE_GET_OPER_AY_8;
5761 uint ea = EA_A7_PI_8();
5763 m68ki_write_8(ea, res);
5765 FLAG_N = NFLAG_8(res);
5767 FLAG_V = VFLAG_CLEAR;
5768 FLAG_C = CFLAG_CLEAR;
5772 M68KMAKE_OP(move, 8, pi, .)
5774 uint res = M68KMAKE_GET_OPER_AY_8;
5775 uint ea = EA_AX_PI_8();
5777 m68ki_write_8(ea, res);
5779 FLAG_N = NFLAG_8(res);
5781 FLAG_V = VFLAG_CLEAR;
5782 FLAG_C = CFLAG_CLEAR;
5786 M68KMAKE_OP(move, 8, pd7, d)
5788 uint res = MASK_OUT_ABOVE_8(DY);
5789 uint ea = EA_A7_PD_8();
5791 m68ki_write_8(ea, res);
5793 FLAG_N = NFLAG_8(res);
5795 FLAG_V = VFLAG_CLEAR;
5796 FLAG_C = CFLAG_CLEAR;
5800 M68KMAKE_OP(move, 8, pd, d)
5802 uint res = MASK_OUT_ABOVE_8(DY);
5803 uint ea = EA_AX_PD_8();
5805 m68ki_write_8(ea, res);
5807 FLAG_N = NFLAG_8(res);
5809 FLAG_V = VFLAG_CLEAR;
5810 FLAG_C = CFLAG_CLEAR;
5814 M68KMAKE_OP(move, 8, pd7, .)
5816 uint res = M68KMAKE_GET_OPER_AY_8;
5817 uint ea = EA_A7_PD_8();
5819 m68ki_write_8(ea, res);
5821 FLAG_N = NFLAG_8(res);
5823 FLAG_V = VFLAG_CLEAR;
5824 FLAG_C = CFLAG_CLEAR;
5828 M68KMAKE_OP(move, 8, pd, .)
5830 uint res = M68KMAKE_GET_OPER_AY_8;
5831 uint ea = EA_AX_PD_8();
5833 m68ki_write_8(ea, res);
5835 FLAG_N = NFLAG_8(res);
5837 FLAG_V = VFLAG_CLEAR;
5838 FLAG_C = CFLAG_CLEAR;
5842 M68KMAKE_OP(move, 8, di, d)
5844 uint res = MASK_OUT_ABOVE_8(DY);
5845 uint ea = EA_AX_DI_8();
5847 m68ki_write_8(ea, res);
5849 FLAG_N = NFLAG_8(res);
5851 FLAG_V = VFLAG_CLEAR;
5852 FLAG_C = CFLAG_CLEAR;
5856 M68KMAKE_OP(move, 8, di, .)
5858 uint res = M68KMAKE_GET_OPER_AY_8;
5859 uint ea = EA_AX_DI_8();
5861 m68ki_write_8(ea, res);
5863 FLAG_N = NFLAG_8(res);
5865 FLAG_V = VFLAG_CLEAR;
5866 FLAG_C = CFLAG_CLEAR;
5870 M68KMAKE_OP(move, 8, ix, d)
5872 uint res = MASK_OUT_ABOVE_8(DY);
5873 uint ea = EA_AX_IX_8();
5875 m68ki_write_8(ea, res);
5877 FLAG_N = NFLAG_8(res);
5879 FLAG_V = VFLAG_CLEAR;
5880 FLAG_C = CFLAG_CLEAR;
5884 M68KMAKE_OP(move, 8, ix, .)
5886 uint res = M68KMAKE_GET_OPER_AY_8;
5887 uint ea = EA_AX_IX_8();
5889 m68ki_write_8(ea, res);
5891 FLAG_N = NFLAG_8(res);
5893 FLAG_V = VFLAG_CLEAR;
5894 FLAG_C = CFLAG_CLEAR;
5898 M68KMAKE_OP(move, 8, aw, d)
5900 uint res = MASK_OUT_ABOVE_8(DY);
5901 uint ea = EA_AW_8();
5903 m68ki_write_8(ea, res);
5905 FLAG_N = NFLAG_8(res);
5907 FLAG_V = VFLAG_CLEAR;
5908 FLAG_C = CFLAG_CLEAR;
5912 M68KMAKE_OP(move, 8, aw, .)
5914 uint res = M68KMAKE_GET_OPER_AY_8;
5915 uint ea = EA_AW_8();
5917 m68ki_write_8(ea, res);
5919 FLAG_N = NFLAG_8(res);
5921 FLAG_V = VFLAG_CLEAR;
5922 FLAG_C = CFLAG_CLEAR;
5926 M68KMAKE_OP(move, 8, al, d)
5928 uint res = MASK_OUT_ABOVE_8(DY);
5929 uint ea = EA_AL_8();
5931 m68ki_write_8(ea, res);
5933 FLAG_N = NFLAG_8(res);
5935 FLAG_V = VFLAG_CLEAR;
5936 FLAG_C = CFLAG_CLEAR;
5940 M68KMAKE_OP(move, 8, al, .)
5942 uint res = M68KMAKE_GET_OPER_AY_8;
5943 uint ea = EA_AL_8();
5945 m68ki_write_8(ea, res);
5947 FLAG_N = NFLAG_8(res);
5949 FLAG_V = VFLAG_CLEAR;
5950 FLAG_C = CFLAG_CLEAR;
5954 M68KMAKE_OP(move, 16, d, d)
5956 uint res = MASK_OUT_ABOVE_16(DY);
5959 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5961 FLAG_N = NFLAG_16(res);
5963 FLAG_V = VFLAG_CLEAR;
5964 FLAG_C = CFLAG_CLEAR;
5968 M68KMAKE_OP(move, 16, d, a)
5970 uint res = MASK_OUT_ABOVE_16(AY);
5973 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5975 FLAG_N = NFLAG_16(res);
5977 FLAG_V = VFLAG_CLEAR;
5978 FLAG_C = CFLAG_CLEAR;
5982 M68KMAKE_OP(move, 16, d, .)
5984 uint res = M68KMAKE_GET_OPER_AY_16;
5987 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5989 FLAG_N = NFLAG_16(res);
5991 FLAG_V = VFLAG_CLEAR;
5992 FLAG_C = CFLAG_CLEAR;
5996 M68KMAKE_OP(move, 16, ai, d)
5998 uint res = MASK_OUT_ABOVE_16(DY);
5999 uint ea = EA_AX_AI_16();
6001 m68ki_write_16(ea, res);
6003 FLAG_N = NFLAG_16(res);
6005 FLAG_V = VFLAG_CLEAR;
6006 FLAG_C = CFLAG_CLEAR;
6010 M68KMAKE_OP(move, 16, ai, a)
6012 uint res = MASK_OUT_ABOVE_16(AY);
6013 uint ea = EA_AX_AI_16();
6015 m68ki_write_16(ea, res);
6017 FLAG_N = NFLAG_16(res);
6019 FLAG_V = VFLAG_CLEAR;
6020 FLAG_C = CFLAG_CLEAR;
6024 M68KMAKE_OP(move, 16, ai, .)
6026 uint res = M68KMAKE_GET_OPER_AY_16;
6027 uint ea = EA_AX_AI_16();
6029 m68ki_write_16(ea, res);
6031 FLAG_N = NFLAG_16(res);
6033 FLAG_V = VFLAG_CLEAR;
6034 FLAG_C = CFLAG_CLEAR;
6038 M68KMAKE_OP(move, 16, pi, d)
6040 uint res = MASK_OUT_ABOVE_16(DY);
6041 uint ea = EA_AX_PI_16();
6043 m68ki_write_16(ea, res);
6045 FLAG_N = NFLAG_16(res);
6047 FLAG_V = VFLAG_CLEAR;
6048 FLAG_C = CFLAG_CLEAR;
6052 M68KMAKE_OP(move, 16, pi, a)
6054 uint res = MASK_OUT_ABOVE_16(AY);
6055 uint ea = EA_AX_PI_16();
6057 m68ki_write_16(ea, res);
6059 FLAG_N = NFLAG_16(res);
6061 FLAG_V = VFLAG_CLEAR;
6062 FLAG_C = CFLAG_CLEAR;
6066 M68KMAKE_OP(move, 16, pi, .)
6068 uint res = M68KMAKE_GET_OPER_AY_16;
6069 uint ea = EA_AX_PI_16();
6071 m68ki_write_16(ea, res);
6073 FLAG_N = NFLAG_16(res);
6075 FLAG_V = VFLAG_CLEAR;
6076 FLAG_C = CFLAG_CLEAR;
6080 M68KMAKE_OP(move, 16, pd, d)
6082 uint res = MASK_OUT_ABOVE_16(DY);
6083 uint ea = EA_AX_PD_16();
6085 m68ki_write_16(ea, res);
6087 FLAG_N = NFLAG_16(res);
6089 FLAG_V = VFLAG_CLEAR;
6090 FLAG_C = CFLAG_CLEAR;
6094 M68KMAKE_OP(move, 16, pd, a)
6096 uint res = MASK_OUT_ABOVE_16(AY);
6097 uint ea = EA_AX_PD_16();
6099 m68ki_write_16(ea, res);
6101 FLAG_N = NFLAG_16(res);
6103 FLAG_V = VFLAG_CLEAR;
6104 FLAG_C = CFLAG_CLEAR;
6108 M68KMAKE_OP(move, 16, pd, .)
6110 uint res = M68KMAKE_GET_OPER_AY_16;
6111 uint ea = EA_AX_PD_16();
6113 m68ki_write_16(ea, res);
6115 FLAG_N = NFLAG_16(res);
6117 FLAG_V = VFLAG_CLEAR;
6118 FLAG_C = CFLAG_CLEAR;
6122 M68KMAKE_OP(move, 16, di, d)
6124 uint res = MASK_OUT_ABOVE_16(DY);
6125 uint ea = EA_AX_DI_16();
6127 m68ki_write_16(ea, res);
6129 FLAG_N = NFLAG_16(res);
6131 FLAG_V = VFLAG_CLEAR;
6132 FLAG_C = CFLAG_CLEAR;
6136 M68KMAKE_OP(move, 16, di, a)
6138 uint res = MASK_OUT_ABOVE_16(AY);
6139 uint ea = EA_AX_DI_16();
6141 m68ki_write_16(ea, res);
6143 FLAG_N = NFLAG_16(res);
6145 FLAG_V = VFLAG_CLEAR;
6146 FLAG_C = CFLAG_CLEAR;
6150 M68KMAKE_OP(move, 16, di, .)
6152 uint res = M68KMAKE_GET_OPER_AY_16;
6153 uint ea = EA_AX_DI_16();
6155 m68ki_write_16(ea, res);
6157 FLAG_N = NFLAG_16(res);
6159 FLAG_V = VFLAG_CLEAR;
6160 FLAG_C = CFLAG_CLEAR;
6164 M68KMAKE_OP(move, 16, ix, d)
6166 uint res = MASK_OUT_ABOVE_16(DY);
6167 uint ea = EA_AX_IX_16();
6169 m68ki_write_16(ea, res);
6171 FLAG_N = NFLAG_16(res);
6173 FLAG_V = VFLAG_CLEAR;
6174 FLAG_C = CFLAG_CLEAR;
6178 M68KMAKE_OP(move, 16, ix, a)
6180 uint res = MASK_OUT_ABOVE_16(AY);
6181 uint ea = EA_AX_IX_16();
6183 m68ki_write_16(ea, res);
6185 FLAG_N = NFLAG_16(res);
6187 FLAG_V = VFLAG_CLEAR;
6188 FLAG_C = CFLAG_CLEAR;
6192 M68KMAKE_OP(move, 16, ix, .)
6194 uint res = M68KMAKE_GET_OPER_AY_16;
6195 uint ea = EA_AX_IX_16();
6197 m68ki_write_16(ea, res);
6199 FLAG_N = NFLAG_16(res);
6201 FLAG_V = VFLAG_CLEAR;
6202 FLAG_C = CFLAG_CLEAR;
6206 M68KMAKE_OP(move, 16, aw, d)
6208 uint res = MASK_OUT_ABOVE_16(DY);
6209 uint ea = EA_AW_16();
6211 m68ki_write_16(ea, res);
6213 FLAG_N = NFLAG_16(res);
6215 FLAG_V = VFLAG_CLEAR;
6216 FLAG_C = CFLAG_CLEAR;
6220 M68KMAKE_OP(move, 16, aw, a)
6222 uint res = MASK_OUT_ABOVE_16(AY);
6223 uint ea = EA_AW_16();
6225 m68ki_write_16(ea, res);
6227 FLAG_N = NFLAG_16(res);
6229 FLAG_V = VFLAG_CLEAR;
6230 FLAG_C = CFLAG_CLEAR;
6234 M68KMAKE_OP(move, 16, aw, .)
6236 uint res = M68KMAKE_GET_OPER_AY_16;
6237 uint ea = EA_AW_16();
6239 m68ki_write_16(ea, res);
6241 FLAG_N = NFLAG_16(res);
6243 FLAG_V = VFLAG_CLEAR;
6244 FLAG_C = CFLAG_CLEAR;
6248 M68KMAKE_OP(move, 16, al, d)
6250 uint res = MASK_OUT_ABOVE_16(DY);
6251 uint ea = EA_AL_16();
6253 m68ki_write_16(ea, res);
6255 FLAG_N = NFLAG_16(res);
6257 FLAG_V = VFLAG_CLEAR;
6258 FLAG_C = CFLAG_CLEAR;
6262 M68KMAKE_OP(move, 16, al, a)
6264 uint res = MASK_OUT_ABOVE_16(AY);
6265 uint ea = EA_AL_16();
6267 m68ki_write_16(ea, res);
6269 FLAG_N = NFLAG_16(res);
6271 FLAG_V = VFLAG_CLEAR;
6272 FLAG_C = CFLAG_CLEAR;
6276 M68KMAKE_OP(move, 16, al, .)
6278 uint res = M68KMAKE_GET_OPER_AY_16;
6279 uint ea = EA_AL_16();
6281 m68ki_write_16(ea, res);
6283 FLAG_N = NFLAG_16(res);
6285 FLAG_V = VFLAG_CLEAR;
6286 FLAG_C = CFLAG_CLEAR;
6290 M68KMAKE_OP(move, 32, d, d)
6297 FLAG_N = NFLAG_32(res);
6299 FLAG_V = VFLAG_CLEAR;
6300 FLAG_C = CFLAG_CLEAR;
6304 M68KMAKE_OP(move, 32, d, a)
6311 FLAG_N = NFLAG_32(res);
6313 FLAG_V = VFLAG_CLEAR;
6314 FLAG_C = CFLAG_CLEAR;
6318 M68KMAKE_OP(move, 32, d, .)
6320 uint res = M68KMAKE_GET_OPER_AY_32;
6325 FLAG_N = NFLAG_32(res);
6327 FLAG_V = VFLAG_CLEAR;
6328 FLAG_C = CFLAG_CLEAR;
6332 M68KMAKE_OP(move, 32, ai, d)
6335 uint ea = EA_AX_AI_32();
6337 m68ki_write_32(ea, res);
6339 FLAG_N = NFLAG_32(res);
6341 FLAG_V = VFLAG_CLEAR;
6342 FLAG_C = CFLAG_CLEAR;
6346 M68KMAKE_OP(move, 32, ai, a)
6349 uint ea = EA_AX_AI_32();
6351 m68ki_write_32(ea, res);
6353 FLAG_N = NFLAG_32(res);
6355 FLAG_V = VFLAG_CLEAR;
6356 FLAG_C = CFLAG_CLEAR;
6360 M68KMAKE_OP(move, 32, ai, .)
6362 uint res = M68KMAKE_GET_OPER_AY_32;
6363 uint ea = EA_AX_AI_32();
6365 m68ki_write_32(ea, res);
6367 FLAG_N = NFLAG_32(res);
6369 FLAG_V = VFLAG_CLEAR;
6370 FLAG_C = CFLAG_CLEAR;
6374 M68KMAKE_OP(move, 32, pi, d)
6377 uint ea = EA_AX_PI_32();
6379 m68ki_write_32(ea, res);
6381 FLAG_N = NFLAG_32(res);
6383 FLAG_V = VFLAG_CLEAR;
6384 FLAG_C = CFLAG_CLEAR;
6388 M68KMAKE_OP(move, 32, pi, a)
6391 uint ea = EA_AX_PI_32();
6393 m68ki_write_32(ea, res);
6395 FLAG_N = NFLAG_32(res);
6397 FLAG_V = VFLAG_CLEAR;
6398 FLAG_C = CFLAG_CLEAR;
6402 M68KMAKE_OP(move, 32, pi, .)
6404 uint res = M68KMAKE_GET_OPER_AY_32;
6405 uint ea = EA_AX_PI_32();
6407 m68ki_write_32(ea, res);
6409 FLAG_N = NFLAG_32(res);
6411 FLAG_V = VFLAG_CLEAR;
6412 FLAG_C = CFLAG_CLEAR;
6416 M68KMAKE_OP(move, 32, pd, d)
6419 uint ea = EA_AX_PD_32();
6421 m68ki_write_16(ea+2, res & 0xFFFF );
6422 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6424 FLAG_N = NFLAG_32(res);
6426 FLAG_V = VFLAG_CLEAR;
6427 FLAG_C = CFLAG_CLEAR;
6431 M68KMAKE_OP(move, 32, pd, a)
6434 uint ea = EA_AX_PD_32();
6436 m68ki_write_16(ea+2, res & 0xFFFF );
6437 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6439 FLAG_N = NFLAG_32(res);
6441 FLAG_V = VFLAG_CLEAR;
6442 FLAG_C = CFLAG_CLEAR;
6446 M68KMAKE_OP(move, 32, pd, .)
6448 uint res = M68KMAKE_GET_OPER_AY_32;
6449 uint ea = EA_AX_PD_32();
6451 m68ki_write_16(ea+2, res & 0xFFFF );
6452 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6454 FLAG_N = NFLAG_32(res);
6456 FLAG_V = VFLAG_CLEAR;
6457 FLAG_C = CFLAG_CLEAR;
6461 M68KMAKE_OP(move, 32, di, d)
6464 uint ea = EA_AX_DI_32();
6466 m68ki_write_32(ea, res);
6468 FLAG_N = NFLAG_32(res);
6470 FLAG_V = VFLAG_CLEAR;
6471 FLAG_C = CFLAG_CLEAR;
6475 M68KMAKE_OP(move, 32, di, a)
6478 uint ea = EA_AX_DI_32();
6480 m68ki_write_32(ea, res);
6482 FLAG_N = NFLAG_32(res);
6484 FLAG_V = VFLAG_CLEAR;
6485 FLAG_C = CFLAG_CLEAR;
6489 M68KMAKE_OP(move, 32, di, .)
6491 uint res = M68KMAKE_GET_OPER_AY_32;
6492 uint ea = EA_AX_DI_32();
6494 m68ki_write_32(ea, res);
6496 FLAG_N = NFLAG_32(res);
6498 FLAG_V = VFLAG_CLEAR;
6499 FLAG_C = CFLAG_CLEAR;
6503 M68KMAKE_OP(move, 32, ix, d)
6506 uint ea = EA_AX_IX_32();
6508 m68ki_write_32(ea, res);
6510 FLAG_N = NFLAG_32(res);
6512 FLAG_V = VFLAG_CLEAR;
6513 FLAG_C = CFLAG_CLEAR;
6517 M68KMAKE_OP(move, 32, ix, a)
6520 uint ea = EA_AX_IX_32();
6522 m68ki_write_32(ea, res);
6524 FLAG_N = NFLAG_32(res);
6526 FLAG_V = VFLAG_CLEAR;
6527 FLAG_C = CFLAG_CLEAR;
6531 M68KMAKE_OP(move, 32, ix, .)
6533 uint res = M68KMAKE_GET_OPER_AY_32;
6534 uint ea = EA_AX_IX_32();
6536 m68ki_write_32(ea, res);
6538 FLAG_N = NFLAG_32(res);
6540 FLAG_V = VFLAG_CLEAR;
6541 FLAG_C = CFLAG_CLEAR;
6545 M68KMAKE_OP(move, 32, aw, d)
6548 uint ea = EA_AW_32();
6550 m68ki_write_32(ea, res);
6552 FLAG_N = NFLAG_32(res);
6554 FLAG_V = VFLAG_CLEAR;
6555 FLAG_C = CFLAG_CLEAR;
6559 M68KMAKE_OP(move, 32, aw, a)
6562 uint ea = EA_AW_32();
6564 m68ki_write_32(ea, res);
6566 FLAG_N = NFLAG_32(res);
6568 FLAG_V = VFLAG_CLEAR;
6569 FLAG_C = CFLAG_CLEAR;
6573 M68KMAKE_OP(move, 32, aw, .)
6575 uint res = M68KMAKE_GET_OPER_AY_32;
6576 uint ea = EA_AW_32();
6578 m68ki_write_32(ea, res);
6580 FLAG_N = NFLAG_32(res);
6582 FLAG_V = VFLAG_CLEAR;
6583 FLAG_C = CFLAG_CLEAR;
6587 M68KMAKE_OP(move, 32, al, d)
6590 uint ea = EA_AL_32();
6592 m68ki_write_32(ea, res);
6594 FLAG_N = NFLAG_32(res);
6596 FLAG_V = VFLAG_CLEAR;
6597 FLAG_C = CFLAG_CLEAR;
6601 M68KMAKE_OP(move, 32, al, a)
6604 uint ea = EA_AL_32();
6606 m68ki_write_32(ea, res);
6608 FLAG_N = NFLAG_32(res);
6610 FLAG_V = VFLAG_CLEAR;
6611 FLAG_C = CFLAG_CLEAR;
6615 M68KMAKE_OP(move, 32, al, .)
6617 uint res = M68KMAKE_GET_OPER_AY_32;
6618 uint ea = EA_AL_32();
6620 m68ki_write_32(ea, res);
6622 FLAG_N = NFLAG_32(res);
6624 FLAG_V = VFLAG_CLEAR;
6625 FLAG_C = CFLAG_CLEAR;
6629 M68KMAKE_OP(movea, 16, ., d)
6631 AX = MAKE_INT_16(DY);
6635 M68KMAKE_OP(movea, 16, ., a)
6637 AX = MAKE_INT_16(AY);
6641 M68KMAKE_OP(movea, 16, ., .)
6643 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
6647 M68KMAKE_OP(movea, 32, ., d)
6653 M68KMAKE_OP(movea, 32, ., a)
6659 M68KMAKE_OP(movea, 32, ., .)
6661 AX = M68KMAKE_GET_OPER_AY_32;
6665 M68KMAKE_OP(move, 16, frc, d)
6667 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6669 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
6672 m68ki_exception_illegal();
6676 M68KMAKE_OP(move, 16, frc, .)
6678 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6680 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
6683 m68ki_exception_illegal();
6687 M68KMAKE_OP(move, 16, toc, d)
6693 M68KMAKE_OP(move, 16, toc, .)
6695 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
6699 M68KMAKE_OP(move, 16, frs, d)
6701 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6703 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
6706 m68ki_exception_privilege_violation();
6710 M68KMAKE_OP(move, 16, frs, .)
6712 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6714 uint ea = M68KMAKE_GET_EA_AY_16;
6715 m68ki_write_16(ea, m68ki_get_sr());
6718 m68ki_exception_privilege_violation();
6722 M68KMAKE_OP(move, 16, tos, d)
6729 m68ki_exception_privilege_violation();
6733 M68KMAKE_OP(move, 16, tos, .)
6737 uint new_sr = M68KMAKE_GET_OPER_AY_16;
6738 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6739 m68ki_set_sr(new_sr);
6742 m68ki_exception_privilege_violation();
6746 M68KMAKE_OP(move, 32, fru, .)
6753 m68ki_exception_privilege_violation();
6757 M68KMAKE_OP(move, 32, tou, .)
6761 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6765 m68ki_exception_privilege_violation();
6769 M68KMAKE_OP(movec, 32, cr, .)
6771 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6775 uint word2 = OPER_I_16();
6777 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6778 switch (word2 & 0xfff)
6780 case 0x000: /* SFC */
6781 REG_DA[(word2 >> 12) & 15] = REG_SFC;
6783 case 0x001: /* DFC */
6784 REG_DA[(word2 >> 12) & 15] = REG_DFC;
6786 case 0x002: /* CACR */
6787 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6789 REG_DA[(word2 >> 12) & 15] = REG_CACR;
6793 case 0x800: /* USP */
6794 REG_DA[(word2 >> 12) & 15] = REG_USP;
6796 case 0x801: /* VBR */
6797 REG_DA[(word2 >> 12) & 15] = REG_VBR;
6799 case 0x802: /* CAAR */
6800 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6802 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
6805 m68ki_exception_illegal();
6807 case 0x803: /* MSP */
6808 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6810 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
6813 m68ki_exception_illegal();
6815 case 0x804: /* ISP */
6816 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6818 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
6821 m68ki_exception_illegal();
6823 case 0x003: /* TC */
6824 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6826 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_tc;
6829 m68ki_exception_illegal();
6831 case 0x004: /* ITT0 */
6832 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6834 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_itt0;
6837 m68ki_exception_illegal();
6839 case 0x005: /* ITT1 */
6840 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6842 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_itt1;
6845 m68ki_exception_illegal();
6847 case 0x006: /* DTT0 */
6848 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6850 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_dtt0;
6853 m68ki_exception_illegal();
6855 case 0x007: /* DTT1 */
6856 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6858 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_dtt1;
6861 m68ki_exception_illegal();
6863 case 0x805: /* MMUSR */
6864 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6866 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_sr_040;
6869 m68ki_exception_illegal();
6871 case 0x806: /* URP */
6872 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6874 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_urp_aptr;
6877 m68ki_exception_illegal();
6879 case 0x807: /* SRP */
6880 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6882 REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_srp_aptr;
6885 m68ki_exception_illegal();
6888 m68ki_exception_illegal();
6892 m68ki_exception_privilege_violation();
6895 m68ki_exception_illegal();
6899 M68KMAKE_OP(movec, 32, rc, .)
6901 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6905 uint word2 = OPER_I_16();
6907 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6908 switch (word2 & 0xfff)
6910 case 0x000: /* SFC */
6911 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
6913 case 0x001: /* DFC */
6914 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
6916 case 0x002: /* CACR */
6917 /* Only EC020 and later have CACR */
6918 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6920 /* 68030 can write all bits except 5-7, 040 can write all */
6921 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6923 REG_CACR = REG_DA[(word2 >> 12) & 15];
6925 else if (CPU_TYPE_IS_030_PLUS(CPU_TYPE))
6927 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0xff1f;
6931 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
6935 m68ki_exception_illegal();
6937 case 0x800: /* USP */
6938 REG_USP = REG_DA[(word2 >> 12) & 15];
6940 case 0x801: /* VBR */
6941 REG_VBR = REG_DA[(word2 >> 12) & 15];
6943 case 0x802: /* CAAR */
6944 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6946 REG_CAAR = REG_DA[(word2 >> 12) & 15];
6949 m68ki_exception_illegal();
6951 case 0x803: /* MSP */
6952 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6954 /* we are in supervisor mode so just check for M flag */
6957 REG_MSP = REG_DA[(word2 >> 12) & 15];
6960 REG_SP = REG_DA[(word2 >> 12) & 15];
6963 m68ki_exception_illegal();
6965 case 0x804: /* ISP */
6966 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6970 REG_SP = REG_DA[(word2 >> 12) & 15];
6973 REG_ISP = REG_DA[(word2 >> 12) & 15];
6976 m68ki_exception_illegal();
6978 case 0x003: /* TC */
6979 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6981 m68ki_cpu.mmu_tc = REG_DA[(word2 >> 12) & 15];
6983 if (m68ki_cpu.mmu_tc & 0x8000)
6985 m68ki_cpu.pmmu_enabled = 1;
6989 m68ki_cpu.pmmu_enabled = 0;
6993 m68ki_exception_illegal();
6995 case 0x004: /* ITT0 */
6996 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6998 m68ki_cpu.mmu_itt0 = REG_DA[(word2 >> 12) & 15];
7001 m68ki_exception_illegal();
7003 case 0x005: /* ITT1 */
7004 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7006 m68ki_cpu.mmu_itt1 = REG_DA[(word2 >> 12) & 15];
7009 m68ki_exception_illegal();
7011 case 0x006: /* DTT0 */
7012 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7014 m68ki_cpu.mmu_dtt0 = REG_DA[(word2 >> 12) & 15];
7017 m68ki_exception_illegal();
7019 case 0x007: /* DTT1 */
7020 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7022 m68ki_cpu.mmu_dtt1 = REG_DA[(word2 >> 12) & 15];
7025 m68ki_exception_illegal();
7027 case 0x805: /* MMUSR */
7028 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7030 m68ki_cpu.mmu_sr_040 = REG_DA[(word2 >> 12) & 15];
7033 m68ki_exception_illegal();
7035 case 0x806: /* URP */
7036 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7038 m68ki_cpu.mmu_urp_aptr = REG_DA[(word2 >> 12) & 15];
7041 m68ki_exception_illegal();
7043 case 0x807: /* SRP */
7044 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7046 m68ki_cpu.mmu_srp_aptr = REG_DA[(word2 >> 12) & 15];
7049 m68ki_exception_illegal();
7052 m68ki_exception_illegal();
7056 m68ki_exception_privilege_violation();
7059 m68ki_exception_illegal();
7063 M68KMAKE_OP(movem, 16, re, pd)
7066 uint register_list = OPER_I_16();
7071 if(register_list & (1 << i))
7074 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
7079 USE_CYCLES(count<<CYC_MOVEM_W);
7083 M68KMAKE_OP(movem, 16, re, .)
7086 uint register_list = OPER_I_16();
7087 uint ea = M68KMAKE_GET_EA_AY_16;
7091 if(register_list & (1 << i))
7093 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
7098 USE_CYCLES(count<<CYC_MOVEM_W);
7102 M68KMAKE_OP(movem, 32, re, pd)
7105 uint register_list = OPER_I_16();
7110 if(register_list & (1 << i))
7113 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
7114 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
7119 USE_CYCLES(count<<CYC_MOVEM_L);
7123 M68KMAKE_OP(movem, 32, re, .)
7126 uint register_list = OPER_I_16();
7127 uint ea = M68KMAKE_GET_EA_AY_32;
7131 if(register_list & (1 << i))
7133 m68ki_write_32(ea, REG_DA[i]);
7138 USE_CYCLES(count<<CYC_MOVEM_L);
7142 M68KMAKE_OP(movem, 16, er, pi)
7145 uint register_list = OPER_I_16();
7150 if(register_list & (1 << i))
7152 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7158 USE_CYCLES(count<<CYC_MOVEM_W);
7162 M68KMAKE_OP(movem, 16, er, pcdi)
7165 uint register_list = OPER_I_16();
7166 uint ea = EA_PCDI_16();
7170 if(register_list & (1 << i))
7172 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7177 USE_CYCLES(count<<CYC_MOVEM_W);
7181 M68KMAKE_OP(movem, 16, er, pcix)
7184 uint register_list = OPER_I_16();
7185 uint ea = EA_PCIX_16();
7189 if(register_list & (1 << i))
7191 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7196 USE_CYCLES(count<<CYC_MOVEM_W);
7200 M68KMAKE_OP(movem, 16, er, .)
7203 uint register_list = OPER_I_16();
7204 uint ea = M68KMAKE_GET_EA_AY_16;
7208 if(register_list & (1 << i))
7210 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7215 USE_CYCLES(count<<CYC_MOVEM_W);
7219 M68KMAKE_OP(movem, 32, er, pi)
7222 uint register_list = OPER_I_16();
7227 if(register_list & (1 << i))
7229 REG_DA[i] = m68ki_read_32(ea);
7235 USE_CYCLES(count<<CYC_MOVEM_L);
7239 M68KMAKE_OP(movem, 32, er, pcdi)
7242 uint register_list = OPER_I_16();
7243 uint ea = EA_PCDI_32();
7247 if(register_list & (1 << i))
7249 REG_DA[i] = m68ki_read_pcrel_32(ea);
7254 USE_CYCLES(count<<CYC_MOVEM_L);
7258 M68KMAKE_OP(movem, 32, er, pcix)
7261 uint register_list = OPER_I_16();
7262 uint ea = EA_PCIX_32();
7266 if(register_list & (1 << i))
7268 REG_DA[i] = m68ki_read_pcrel_32(ea);
7273 USE_CYCLES(count<<CYC_MOVEM_L);
7277 M68KMAKE_OP(movem, 32, er, .)
7280 uint register_list = OPER_I_16();
7281 uint ea = M68KMAKE_GET_EA_AY_32;
7285 if(register_list & (1 << i))
7287 REG_DA[i] = m68ki_read_32(ea);
7292 USE_CYCLES(count<<CYC_MOVEM_L);
7296 M68KMAKE_OP(movep, 16, re, .)
7298 uint ea = EA_AY_DI_16();
7301 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
7302 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7306 M68KMAKE_OP(movep, 32, re, .)
7308 uint ea = EA_AY_DI_32();
7311 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
7312 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
7313 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
7314 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7318 M68KMAKE_OP(movep, 16, er, .)
7320 uint ea = EA_AY_DI_16();
7323 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
7327 M68KMAKE_OP(movep, 32, er, .)
7329 uint ea = EA_AY_DI_32();
7331 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
7332 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
7336 M68KMAKE_OP(moves, 8, ., .)
7338 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7342 uint word2 = OPER_I_16();
7343 uint ea = M68KMAKE_GET_EA_AY_8;
7345 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7346 if(BIT_B(word2)) /* Register to memory */
7348 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
7351 if(BIT_F(word2)) /* Memory to address register */
7353 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
7354 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7358 /* Memory to data register */
7359 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
7360 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7364 m68ki_exception_privilege_violation();
7367 m68ki_exception_illegal();
7371 M68KMAKE_OP(moves, 16, ., .)
7373 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7377 uint word2 = OPER_I_16();
7378 uint ea = M68KMAKE_GET_EA_AY_16;
7380 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7381 if(BIT_B(word2)) /* Register to memory */
7383 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
7386 if(BIT_F(word2)) /* Memory to address register */
7388 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
7389 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7393 /* Memory to data register */
7394 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
7395 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7399 m68ki_exception_privilege_violation();
7402 m68ki_exception_illegal();
7406 M68KMAKE_OP(moves, 32, ., .)
7408 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7412 uint word2 = OPER_I_16();
7413 uint ea = M68KMAKE_GET_EA_AY_32;
7415 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7416 if(BIT_B(word2)) /* Register to memory */
7418 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
7419 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7423 /* Memory to register */
7424 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
7425 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7429 m68ki_exception_privilege_violation();
7432 m68ki_exception_illegal();
7436 M68KMAKE_OP(moveq, 32, ., .)
7438 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
7440 FLAG_N = NFLAG_32(res);
7442 FLAG_V = VFLAG_CLEAR;
7443 FLAG_C = CFLAG_CLEAR;
7447 M68KMAKE_OP(move16, 32, ., .)
7449 uint16 w2 = OPER_I_16();
7450 int ax = REG_IR & 7;
7451 int ay = (w2 >> 12) & 7;
7453 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
7454 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
7455 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
7456 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
7463 M68KMAKE_OP(muls, 16, ., d)
7466 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7471 FLAG_N = NFLAG_32(res);
7472 FLAG_V = VFLAG_CLEAR;
7473 FLAG_C = CFLAG_CLEAR;
7477 M68KMAKE_OP(muls, 16, ., .)
7480 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7485 FLAG_N = NFLAG_32(res);
7486 FLAG_V = VFLAG_CLEAR;
7487 FLAG_C = CFLAG_CLEAR;
7491 M68KMAKE_OP(mulu, 16, ., d)
7494 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
7499 FLAG_N = NFLAG_32(res);
7500 FLAG_V = VFLAG_CLEAR;
7501 FLAG_C = CFLAG_CLEAR;
7505 M68KMAKE_OP(mulu, 16, ., .)
7508 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
7513 FLAG_N = NFLAG_32(res);
7514 FLAG_V = VFLAG_CLEAR;
7515 FLAG_C = CFLAG_CLEAR;
7519 M68KMAKE_OP(mull, 32, ., d)
7523 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7525 uint word2 = OPER_I_16();
7527 uint64 dst = REG_D[(word2 >> 12) & 7];
7530 FLAG_C = CFLAG_CLEAR;
7532 if(BIT_B(word2)) /* signed */
7534 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7537 FLAG_Z = MASK_OUT_ABOVE_32(res);
7538 FLAG_N = NFLAG_32(res);
7539 FLAG_V = ((sint64)res != (sint32)res)<<7;
7540 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7543 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7544 FLAG_N = NFLAG_64(res);
7545 FLAG_V = VFLAG_CLEAR;
7546 REG_D[word2 & 7] = (res >> 32);
7547 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7554 FLAG_Z = MASK_OUT_ABOVE_32(res);
7555 FLAG_N = NFLAG_32(res);
7556 FLAG_V = (res > 0xffffffff)<<7;
7557 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7560 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7561 FLAG_N = NFLAG_64(res);
7562 FLAG_V = VFLAG_CLEAR;
7563 REG_D[word2 & 7] = (res >> 32);
7564 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7567 m68ki_exception_illegal();
7571 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7573 uint word2 = OPER_I_16();
7575 uint dst = REG_D[(word2 >> 12) & 7];
7576 uint neg = GET_MSB_32(src ^ dst);
7588 FLAG_C = CFLAG_CLEAR;
7590 if(BIT_B(word2)) /* signed */
7593 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7595 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7598 src1 = MASK_OUT_ABOVE_16(src);
7600 dst1 = MASK_OUT_ABOVE_16(dst);
7609 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7610 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7612 if(BIT_B(word2) && neg)
7614 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7615 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7620 REG_D[word2 & 7] = hi;
7621 REG_D[(word2 >> 12) & 7] = lo;
7622 FLAG_N = NFLAG_32(hi);
7624 FLAG_V = VFLAG_CLEAR;
7628 REG_D[(word2 >> 12) & 7] = lo;
7629 FLAG_N = NFLAG_32(lo);
7632 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7634 FLAG_V = (hi != 0) << 7;
7637 m68ki_exception_illegal();
7643 M68KMAKE_OP(mull, 32, ., .)
7647 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7649 uint word2 = OPER_I_16();
7650 uint64 src = M68KMAKE_GET_OPER_AY_32;
7651 uint64 dst = REG_D[(word2 >> 12) & 7];
7654 FLAG_C = CFLAG_CLEAR;
7656 if(BIT_B(word2)) /* signed */
7658 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7661 FLAG_Z = MASK_OUT_ABOVE_32(res);
7662 FLAG_N = NFLAG_32(res);
7663 FLAG_V = ((sint64)res != (sint32)res)<<7;
7664 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7667 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7668 FLAG_N = NFLAG_64(res);
7669 FLAG_V = VFLAG_CLEAR;
7670 REG_D[word2 & 7] = (res >> 32);
7671 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7678 FLAG_Z = MASK_OUT_ABOVE_32(res);
7679 FLAG_N = NFLAG_32(res);
7680 FLAG_V = (res > 0xffffffff)<<7;
7681 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7684 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7685 FLAG_N = NFLAG_64(res);
7686 FLAG_V = VFLAG_CLEAR;
7687 REG_D[word2 & 7] = (res >> 32);
7688 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7691 m68ki_exception_illegal();
7695 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7697 uint word2 = OPER_I_16();
7698 uint src = M68KMAKE_GET_OPER_AY_32;
7699 uint dst = REG_D[(word2 >> 12) & 7];
7700 uint neg = GET_MSB_32(src ^ dst);
7712 FLAG_C = CFLAG_CLEAR;
7714 if(BIT_B(word2)) /* signed */
7717 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7719 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7722 src1 = MASK_OUT_ABOVE_16(src);
7724 dst1 = MASK_OUT_ABOVE_16(dst);
7733 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7734 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7736 if(BIT_B(word2) && neg)
7738 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7739 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7744 REG_D[word2 & 7] = hi;
7745 REG_D[(word2 >> 12) & 7] = lo;
7746 FLAG_N = NFLAG_32(hi);
7748 FLAG_V = VFLAG_CLEAR;
7752 REG_D[(word2 >> 12) & 7] = lo;
7753 FLAG_N = NFLAG_32(lo);
7756 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7758 FLAG_V = (hi != 0) << 7;
7761 m68ki_exception_illegal();
7767 M68KMAKE_OP(nbcd, 8, ., d)
7771 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
7775 FLAG_V = ~res; /* Undefined V behavior */
7777 if((res & 0x0f) == 0xa)
7778 res = (res & 0xf0) + 0x10;
7780 res = MASK_OUT_ABOVE_8(res);
7782 FLAG_V &= res; /* Undefined V behavior part II */
7784 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7792 FLAG_V = VFLAG_CLEAR;
7793 FLAG_C = CFLAG_CLEAR;
7794 FLAG_X = XFLAG_CLEAR;
7796 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7800 M68KMAKE_OP(nbcd, 8, ., .)
7802 uint ea = M68KMAKE_GET_EA_AY_8;
7803 uint dst = m68ki_read_8(ea);
7804 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
7808 FLAG_V = ~res; /* Undefined V behavior */
7810 if((res & 0x0f) == 0xa)
7811 res = (res & 0xf0) + 0x10;
7813 res = MASK_OUT_ABOVE_8(res);
7815 FLAG_V &= res; /* Undefined V behavior part II */
7817 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
7825 FLAG_V = VFLAG_CLEAR;
7826 FLAG_C = CFLAG_CLEAR;
7827 FLAG_X = XFLAG_CLEAR;
7829 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7833 M68KMAKE_OP(neg, 8, ., d)
7836 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
7838 FLAG_N = NFLAG_8(res);
7839 FLAG_C = FLAG_X = CFLAG_8(res);
7840 FLAG_V = *r_dst & res;
7841 FLAG_Z = MASK_OUT_ABOVE_8(res);
7843 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
7847 M68KMAKE_OP(neg, 8, ., .)
7849 uint ea = M68KMAKE_GET_EA_AY_8;
7850 uint src = m68ki_read_8(ea);
7853 FLAG_N = NFLAG_8(res);
7854 FLAG_C = FLAG_X = CFLAG_8(res);
7856 FLAG_Z = MASK_OUT_ABOVE_8(res);
7858 m68ki_write_8(ea, FLAG_Z);
7862 M68KMAKE_OP(neg, 16, ., d)
7865 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
7867 FLAG_N = NFLAG_16(res);
7868 FLAG_C = FLAG_X = CFLAG_16(res);
7869 FLAG_V = (*r_dst & res)>>8;
7870 FLAG_Z = MASK_OUT_ABOVE_16(res);
7872 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
7876 M68KMAKE_OP(neg, 16, ., .)
7878 uint ea = M68KMAKE_GET_EA_AY_16;
7879 uint src = m68ki_read_16(ea);
7882 FLAG_N = NFLAG_16(res);
7883 FLAG_C = FLAG_X = CFLAG_16(res);
7884 FLAG_V = (src & res)>>8;
7885 FLAG_Z = MASK_OUT_ABOVE_16(res);
7887 m68ki_write_16(ea, FLAG_Z);
7891 M68KMAKE_OP(neg, 32, ., d)
7894 uint res = 0 - *r_dst;
7896 FLAG_N = NFLAG_32(res);
7897 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
7898 FLAG_V = (*r_dst & res)>>24;
7899 FLAG_Z = MASK_OUT_ABOVE_32(res);
7905 M68KMAKE_OP(neg, 32, ., .)
7907 uint ea = M68KMAKE_GET_EA_AY_32;
7908 uint src = m68ki_read_32(ea);
7911 FLAG_N = NFLAG_32(res);
7912 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
7913 FLAG_V = (src & res)>>24;
7914 FLAG_Z = MASK_OUT_ABOVE_32(res);
7916 m68ki_write_32(ea, FLAG_Z);
7920 M68KMAKE_OP(negx, 8, ., d)
7923 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
7925 FLAG_N = NFLAG_8(res);
7926 FLAG_X = FLAG_C = CFLAG_8(res);
7927 FLAG_V = *r_dst & res;
7929 res = MASK_OUT_ABOVE_8(res);
7932 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7936 M68KMAKE_OP(negx, 8, ., .)
7938 uint ea = M68KMAKE_GET_EA_AY_8;
7939 uint src = m68ki_read_8(ea);
7940 uint res = 0 - src - XFLAG_AS_1();
7942 FLAG_N = NFLAG_8(res);
7943 FLAG_X = FLAG_C = CFLAG_8(res);
7946 res = MASK_OUT_ABOVE_8(res);
7949 m68ki_write_8(ea, res);
7953 M68KMAKE_OP(negx, 16, ., d)
7956 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
7958 FLAG_N = NFLAG_16(res);
7959 FLAG_X = FLAG_C = CFLAG_16(res);
7960 FLAG_V = (*r_dst & res)>>8;
7962 res = MASK_OUT_ABOVE_16(res);
7965 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
7969 M68KMAKE_OP(negx, 16, ., .)
7971 uint ea = M68KMAKE_GET_EA_AY_16;
7972 uint src = m68ki_read_16(ea);
7973 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
7975 FLAG_N = NFLAG_16(res);
7976 FLAG_X = FLAG_C = CFLAG_16(res);
7977 FLAG_V = (src & res)>>8;
7979 res = MASK_OUT_ABOVE_16(res);
7982 m68ki_write_16(ea, res);
7986 M68KMAKE_OP(negx, 32, ., d)
7989 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
7991 FLAG_N = NFLAG_32(res);
7992 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
7993 FLAG_V = (*r_dst & res)>>24;
7995 res = MASK_OUT_ABOVE_32(res);
8002 M68KMAKE_OP(negx, 32, ., .)
8004 uint ea = M68KMAKE_GET_EA_AY_32;
8005 uint src = m68ki_read_32(ea);
8006 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
8008 FLAG_N = NFLAG_32(res);
8009 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
8010 FLAG_V = (src & res)>>24;
8012 res = MASK_OUT_ABOVE_32(res);
8015 m68ki_write_32(ea, res);
8019 M68KMAKE_OP(nop, 0, ., .)
8021 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8025 M68KMAKE_OP(not, 8, ., d)
8028 uint res = MASK_OUT_ABOVE_8(~*r_dst);
8030 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8032 FLAG_N = NFLAG_8(res);
8034 FLAG_C = CFLAG_CLEAR;
8035 FLAG_V = VFLAG_CLEAR;
8039 M68KMAKE_OP(not, 8, ., .)
8041 uint ea = M68KMAKE_GET_EA_AY_8;
8042 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
8044 m68ki_write_8(ea, res);
8046 FLAG_N = NFLAG_8(res);
8048 FLAG_C = CFLAG_CLEAR;
8049 FLAG_V = VFLAG_CLEAR;
8053 M68KMAKE_OP(not, 16, ., d)
8056 uint res = MASK_OUT_ABOVE_16(~*r_dst);
8058 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8060 FLAG_N = NFLAG_16(res);
8062 FLAG_C = CFLAG_CLEAR;
8063 FLAG_V = VFLAG_CLEAR;
8067 M68KMAKE_OP(not, 16, ., .)
8069 uint ea = M68KMAKE_GET_EA_AY_16;
8070 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
8072 m68ki_write_16(ea, res);
8074 FLAG_N = NFLAG_16(res);
8076 FLAG_C = CFLAG_CLEAR;
8077 FLAG_V = VFLAG_CLEAR;
8081 M68KMAKE_OP(not, 32, ., d)
8084 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
8086 FLAG_N = NFLAG_32(res);
8088 FLAG_C = CFLAG_CLEAR;
8089 FLAG_V = VFLAG_CLEAR;
8093 M68KMAKE_OP(not, 32, ., .)
8095 uint ea = M68KMAKE_GET_EA_AY_32;
8096 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
8098 m68ki_write_32(ea, res);
8100 FLAG_N = NFLAG_32(res);
8102 FLAG_C = CFLAG_CLEAR;
8103 FLAG_V = VFLAG_CLEAR;
8107 M68KMAKE_OP(or, 8, er, d)
8109 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
8111 FLAG_N = NFLAG_8(res);
8113 FLAG_C = CFLAG_CLEAR;
8114 FLAG_V = VFLAG_CLEAR;
8118 M68KMAKE_OP(or, 8, er, .)
8120 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
8122 FLAG_N = NFLAG_8(res);
8124 FLAG_C = CFLAG_CLEAR;
8125 FLAG_V = VFLAG_CLEAR;
8129 M68KMAKE_OP(or, 16, er, d)
8131 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
8133 FLAG_N = NFLAG_16(res);
8135 FLAG_C = CFLAG_CLEAR;
8136 FLAG_V = VFLAG_CLEAR;
8140 M68KMAKE_OP(or, 16, er, .)
8142 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
8144 FLAG_N = NFLAG_16(res);
8146 FLAG_C = CFLAG_CLEAR;
8147 FLAG_V = VFLAG_CLEAR;
8151 M68KMAKE_OP(or, 32, er, d)
8153 uint res = DX |= DY;
8155 FLAG_N = NFLAG_32(res);
8157 FLAG_C = CFLAG_CLEAR;
8158 FLAG_V = VFLAG_CLEAR;
8162 M68KMAKE_OP(or, 32, er, .)
8164 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
8166 FLAG_N = NFLAG_32(res);
8168 FLAG_C = CFLAG_CLEAR;
8169 FLAG_V = VFLAG_CLEAR;
8173 M68KMAKE_OP(or, 8, re, .)
8175 uint ea = M68KMAKE_GET_EA_AY_8;
8176 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
8178 m68ki_write_8(ea, res);
8180 FLAG_N = NFLAG_8(res);
8182 FLAG_C = CFLAG_CLEAR;
8183 FLAG_V = VFLAG_CLEAR;
8187 M68KMAKE_OP(or, 16, re, .)
8189 uint ea = M68KMAKE_GET_EA_AY_16;
8190 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
8192 m68ki_write_16(ea, res);
8194 FLAG_N = NFLAG_16(res);
8196 FLAG_C = CFLAG_CLEAR;
8197 FLAG_V = VFLAG_CLEAR;
8201 M68KMAKE_OP(or, 32, re, .)
8203 uint ea = M68KMAKE_GET_EA_AY_32;
8204 uint res = DX | m68ki_read_32(ea);
8206 m68ki_write_32(ea, res);
8208 FLAG_N = NFLAG_32(res);
8210 FLAG_C = CFLAG_CLEAR;
8211 FLAG_V = VFLAG_CLEAR;
8215 M68KMAKE_OP(ori, 8, ., d)
8217 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
8219 FLAG_N = NFLAG_8(res);
8221 FLAG_C = CFLAG_CLEAR;
8222 FLAG_V = VFLAG_CLEAR;
8226 M68KMAKE_OP(ori, 8, ., .)
8228 uint src = OPER_I_8();
8229 uint ea = M68KMAKE_GET_EA_AY_8;
8230 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
8232 m68ki_write_8(ea, res);
8234 FLAG_N = NFLAG_8(res);
8236 FLAG_C = CFLAG_CLEAR;
8237 FLAG_V = VFLAG_CLEAR;
8241 M68KMAKE_OP(ori, 16, ., d)
8243 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
8245 FLAG_N = NFLAG_16(res);
8247 FLAG_C = CFLAG_CLEAR;
8248 FLAG_V = VFLAG_CLEAR;
8252 M68KMAKE_OP(ori, 16, ., .)
8254 uint src = OPER_I_16();
8255 uint ea = M68KMAKE_GET_EA_AY_16;
8256 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
8258 m68ki_write_16(ea, res);
8260 FLAG_N = NFLAG_16(res);
8262 FLAG_C = CFLAG_CLEAR;
8263 FLAG_V = VFLAG_CLEAR;
8267 M68KMAKE_OP(ori, 32, ., d)
8269 uint res = DY |= OPER_I_32();
8271 FLAG_N = NFLAG_32(res);
8273 FLAG_C = CFLAG_CLEAR;
8274 FLAG_V = VFLAG_CLEAR;
8278 M68KMAKE_OP(ori, 32, ., .)
8280 uint src = OPER_I_32();
8281 uint ea = M68KMAKE_GET_EA_AY_32;
8282 uint res = src | m68ki_read_32(ea);
8284 m68ki_write_32(ea, res);
8286 FLAG_N = NFLAG_32(res);
8288 FLAG_C = CFLAG_CLEAR;
8289 FLAG_V = VFLAG_CLEAR;
8293 M68KMAKE_OP(ori, 16, toc, .)
8295 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8());
8299 M68KMAKE_OP(ori, 16, tos, .)
8303 uint src = OPER_I_16();
8304 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8305 m68ki_set_sr(m68ki_get_sr() | src);
8308 m68ki_exception_privilege_violation();
8312 M68KMAKE_OP(pack, 16, rr, .)
8314 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8316 /* Note: DX and DY are reversed in Motorola's docs */
8317 uint src = DY + OPER_I_16();
8320 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
8323 m68ki_exception_illegal();
8327 M68KMAKE_OP(pack, 16, mm, ax7)
8329 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8331 /* Note: AX and AY are reversed in Motorola's docs */
8332 uint ea_src = EA_AY_PD_8();
8333 uint src = m68ki_read_8(ea_src);
8334 ea_src = EA_AY_PD_8();
8335 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8337 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8340 m68ki_exception_illegal();
8344 M68KMAKE_OP(pack, 16, mm, ay7)
8346 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8348 /* Note: AX and AY are reversed in Motorola's docs */
8349 uint ea_src = EA_A7_PD_8();
8350 uint src = m68ki_read_8(ea_src);
8351 ea_src = EA_A7_PD_8();
8352 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8354 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8357 m68ki_exception_illegal();
8361 M68KMAKE_OP(pack, 16, mm, axy7)
8363 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8365 uint ea_src = EA_A7_PD_8();
8366 uint src = m68ki_read_8(ea_src);
8367 ea_src = EA_A7_PD_8();
8368 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8370 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8373 m68ki_exception_illegal();
8377 M68KMAKE_OP(pack, 16, mm, .)
8379 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8381 /* Note: AX and AY are reversed in Motorola's docs */
8382 uint ea_src = EA_AY_PD_8();
8383 uint src = m68ki_read_8(ea_src);
8384 ea_src = EA_AY_PD_8();
8385 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8387 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8390 m68ki_exception_illegal();
8394 M68KMAKE_OP(pea, 32, ., .)
8396 uint ea = M68KMAKE_GET_EA_AY_32;
8401 M68KMAKE_OP(pflusha, 32, ., .)
8405 fprintf(stderr,"68040: unhandled PFLUSHA (ir=%04x)\n", REG_IR);
8408 m68ki_exception_1111();
8411 M68KMAKE_OP(pflushan, 32, ., .)
8415 fprintf(stderr,"68040: unhandled PFLUSHAN (ir=%04x)\n", REG_IR);
8418 m68ki_exception_1111();
8421 M68KMAKE_OP(pmmu, 32, ., .)
8423 if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU))
8429 m68ki_exception_1111();
8433 M68KMAKE_OP(reset, 0, ., .)
8437 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
8438 USE_CYCLES(CYC_RESET);
8441 m68ki_exception_privilege_violation();
8445 M68KMAKE_OP(ror, 8, s, .)
8448 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8449 uint shift = orig_shift & 7;
8450 uint src = MASK_OUT_ABOVE_8(*r_dst);
8451 uint res = ROR_8(src, shift);
8454 USE_CYCLES(orig_shift<<CYC_SHIFT);
8456 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8458 FLAG_N = NFLAG_8(res);
8460 FLAG_C = src << (9-orig_shift);
8461 FLAG_V = VFLAG_CLEAR;
8465 M68KMAKE_OP(ror, 16, s, .)
8468 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8469 uint src = MASK_OUT_ABOVE_16(*r_dst);
8470 uint res = ROR_16(src, shift);
8473 USE_CYCLES(shift<<CYC_SHIFT);
8475 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8477 FLAG_N = NFLAG_16(res);
8479 FLAG_C = src << (9-shift);
8480 FLAG_V = VFLAG_CLEAR;
8484 M68KMAKE_OP(ror, 32, s, .)
8487 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8488 uint64 src = *r_dst;
8489 uint res = ROR_32(src, shift);
8492 USE_CYCLES(shift<<CYC_SHIFT);
8496 FLAG_N = NFLAG_32(res);
8498 FLAG_C = src << (9-shift);
8499 FLAG_V = VFLAG_CLEAR;
8503 M68KMAKE_OP(ror, 8, r, .)
8506 uint orig_shift = DX & 0x3f;
8507 uint shift = orig_shift & 7;
8508 uint src = MASK_OUT_ABOVE_8(*r_dst);
8509 uint res = ROR_8(src, shift);
8513 USE_CYCLES(orig_shift<<CYC_SHIFT);
8515 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8516 FLAG_C = src << (8-((shift-1)&7));
8517 FLAG_N = NFLAG_8(res);
8519 FLAG_V = VFLAG_CLEAR;
8523 FLAG_C = CFLAG_CLEAR;
8524 FLAG_N = NFLAG_8(src);
8526 FLAG_V = VFLAG_CLEAR;
8530 M68KMAKE_OP(ror, 16, r, .)
8533 uint orig_shift = DX & 0x3f;
8534 uint shift = orig_shift & 15;
8535 uint src = MASK_OUT_ABOVE_16(*r_dst);
8536 uint res = ROR_16(src, shift);
8540 USE_CYCLES(orig_shift<<CYC_SHIFT);
8542 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8543 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
8544 FLAG_N = NFLAG_16(res);
8546 FLAG_V = VFLAG_CLEAR;
8550 FLAG_C = CFLAG_CLEAR;
8551 FLAG_N = NFLAG_16(src);
8553 FLAG_V = VFLAG_CLEAR;
8557 M68KMAKE_OP(ror, 32, r, .)
8560 uint orig_shift = DX & 0x3f;
8561 uint shift = orig_shift & 31;
8562 uint64 src = *r_dst;
8563 uint res = ROR_32(src, shift);
8567 USE_CYCLES(orig_shift<<CYC_SHIFT);
8570 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
8571 FLAG_N = NFLAG_32(res);
8573 FLAG_V = VFLAG_CLEAR;
8577 FLAG_C = CFLAG_CLEAR;
8578 FLAG_N = NFLAG_32(src);
8580 FLAG_V = VFLAG_CLEAR;
8584 M68KMAKE_OP(ror, 16, ., .)
8586 uint ea = M68KMAKE_GET_EA_AY_16;
8587 uint src = m68ki_read_16(ea);
8588 uint res = ROR_16(src, 1);
8590 m68ki_write_16(ea, res);
8592 FLAG_N = NFLAG_16(res);
8595 FLAG_V = VFLAG_CLEAR;
8599 M68KMAKE_OP(rol, 8, s, .)
8602 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8603 uint shift = orig_shift & 7;
8604 uint src = MASK_OUT_ABOVE_8(*r_dst);
8605 uint res = ROL_8(src, shift);
8608 USE_CYCLES(orig_shift<<CYC_SHIFT);
8610 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8612 FLAG_N = NFLAG_8(res);
8614 FLAG_C = src << orig_shift;
8615 FLAG_V = VFLAG_CLEAR;
8619 M68KMAKE_OP(rol, 16, s, .)
8622 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8623 uint src = MASK_OUT_ABOVE_16(*r_dst);
8624 uint res = ROL_16(src, shift);
8627 USE_CYCLES(shift<<CYC_SHIFT);
8629 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8631 FLAG_N = NFLAG_16(res);
8633 FLAG_C = src >> (8-shift);
8634 FLAG_V = VFLAG_CLEAR;
8638 M68KMAKE_OP(rol, 32, s, .)
8641 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8642 uint64 src = *r_dst;
8643 uint res = ROL_32(src, shift);
8646 USE_CYCLES(shift<<CYC_SHIFT);
8650 FLAG_N = NFLAG_32(res);
8652 FLAG_C = src >> (24-shift);
8653 FLAG_V = VFLAG_CLEAR;
8657 M68KMAKE_OP(rol, 8, r, .)
8660 uint orig_shift = DX & 0x3f;
8661 uint shift = orig_shift & 7;
8662 uint src = MASK_OUT_ABOVE_8(*r_dst);
8663 uint res = ROL_8(src, shift);
8667 USE_CYCLES(orig_shift<<CYC_SHIFT);
8671 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8672 FLAG_C = src << shift;
8673 FLAG_N = NFLAG_8(res);
8675 FLAG_V = VFLAG_CLEAR;
8678 FLAG_C = (src & 1)<<8;
8679 FLAG_N = NFLAG_8(src);
8681 FLAG_V = VFLAG_CLEAR;
8685 FLAG_C = CFLAG_CLEAR;
8686 FLAG_N = NFLAG_8(src);
8688 FLAG_V = VFLAG_CLEAR;
8692 M68KMAKE_OP(rol, 16, r, .)
8695 uint orig_shift = DX & 0x3f;
8696 uint shift = orig_shift & 15;
8697 uint src = MASK_OUT_ABOVE_16(*r_dst);
8698 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
8702 USE_CYCLES(orig_shift<<CYC_SHIFT);
8706 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8707 FLAG_C = (src << shift) >> 8;
8708 FLAG_N = NFLAG_16(res);
8710 FLAG_V = VFLAG_CLEAR;
8713 FLAG_C = (src & 1)<<8;
8714 FLAG_N = NFLAG_16(src);
8716 FLAG_V = VFLAG_CLEAR;
8720 FLAG_C = CFLAG_CLEAR;
8721 FLAG_N = NFLAG_16(src);
8723 FLAG_V = VFLAG_CLEAR;
8727 M68KMAKE_OP(rol, 32, r, .)
8730 uint orig_shift = DX & 0x3f;
8731 uint shift = orig_shift & 31;
8732 uint64 src = *r_dst;
8733 uint res = ROL_32(src, shift);
8737 USE_CYCLES(orig_shift<<CYC_SHIFT);
8741 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
8742 FLAG_N = NFLAG_32(res);
8744 FLAG_V = VFLAG_CLEAR;
8748 FLAG_C = CFLAG_CLEAR;
8749 FLAG_N = NFLAG_32(src);
8751 FLAG_V = VFLAG_CLEAR;
8755 M68KMAKE_OP(rol, 16, ., .)
8757 uint ea = M68KMAKE_GET_EA_AY_16;
8758 uint src = m68ki_read_16(ea);
8759 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
8761 m68ki_write_16(ea, res);
8763 FLAG_N = NFLAG_16(res);
8766 FLAG_V = VFLAG_CLEAR;
8770 M68KMAKE_OP(roxr, 8, s, .)
8773 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8774 uint src = MASK_OUT_ABOVE_8(*r_dst);
8775 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8778 USE_CYCLES(shift<<CYC_SHIFT);
8780 FLAG_C = FLAG_X = res;
8781 res = MASK_OUT_ABOVE_8(res);
8783 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8785 FLAG_N = NFLAG_8(res);
8787 FLAG_V = VFLAG_CLEAR;
8791 M68KMAKE_OP(roxr, 16, s, .)
8794 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8795 uint src = MASK_OUT_ABOVE_16(*r_dst);
8796 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8799 USE_CYCLES(shift<<CYC_SHIFT);
8801 FLAG_C = FLAG_X = res >> 8;
8802 res = MASK_OUT_ABOVE_16(res);
8804 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8806 FLAG_N = NFLAG_16(res);
8808 FLAG_V = VFLAG_CLEAR;
8812 M68KMAKE_OP(roxr, 32, s, .)
8817 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8818 uint64 src = *r_dst;
8819 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8822 USE_CYCLES(shift<<CYC_SHIFT);
8824 res = ROR_33_64(res, shift);
8826 FLAG_C = FLAG_X = res >> 24;
8827 res = MASK_OUT_ABOVE_32(res);
8831 FLAG_N = NFLAG_32(res);
8833 FLAG_V = VFLAG_CLEAR;
8838 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8840 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8841 uint new_x_flag = src & (1 << (shift - 1));
8844 USE_CYCLES(shift<<CYC_SHIFT);
8848 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
8849 FLAG_N = NFLAG_32(res);
8851 FLAG_V = VFLAG_CLEAR;
8857 M68KMAKE_OP(roxr, 8, r, .)
8860 uint orig_shift = DX & 0x3f;
8864 uint shift = orig_shift % 9;
8865 uint src = MASK_OUT_ABOVE_8(*r_dst);
8866 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8868 USE_CYCLES(orig_shift<<CYC_SHIFT);
8870 FLAG_C = FLAG_X = res;
8871 res = MASK_OUT_ABOVE_8(res);
8873 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8874 FLAG_N = NFLAG_8(res);
8876 FLAG_V = VFLAG_CLEAR;
8881 FLAG_N = NFLAG_8(*r_dst);
8882 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
8883 FLAG_V = VFLAG_CLEAR;
8887 M68KMAKE_OP(roxr, 16, r, .)
8890 uint orig_shift = DX & 0x3f;
8894 uint shift = orig_shift % 17;
8895 uint src = MASK_OUT_ABOVE_16(*r_dst);
8896 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8898 USE_CYCLES(orig_shift<<CYC_SHIFT);
8900 FLAG_C = FLAG_X = res >> 8;
8901 res = MASK_OUT_ABOVE_16(res);
8903 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8904 FLAG_N = NFLAG_16(res);
8906 FLAG_V = VFLAG_CLEAR;
8911 FLAG_N = NFLAG_16(*r_dst);
8912 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
8913 FLAG_V = VFLAG_CLEAR;
8917 M68KMAKE_OP(roxr, 32, r, .)
8922 uint orig_shift = DX & 0x3f;
8926 uint shift = orig_shift % 33;
8927 uint64 src = *r_dst;
8928 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8930 res = ROR_33_64(res, shift);
8932 USE_CYCLES(orig_shift<<CYC_SHIFT);
8934 FLAG_C = FLAG_X = res >> 24;
8935 res = MASK_OUT_ABOVE_32(res);
8938 FLAG_N = NFLAG_32(res);
8940 FLAG_V = VFLAG_CLEAR;
8945 FLAG_N = NFLAG_32(*r_dst);
8947 FLAG_V = VFLAG_CLEAR;
8952 uint orig_shift = DX & 0x3f;
8953 uint shift = orig_shift % 33;
8955 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8956 uint new_x_flag = src & (1 << (shift - 1));
8959 USE_CYCLES(orig_shift<<CYC_SHIFT);
8964 FLAG_X = (new_x_flag != 0)<<8;
8969 FLAG_N = NFLAG_32(res);
8971 FLAG_V = VFLAG_CLEAR;
8977 M68KMAKE_OP(roxr, 16, ., .)
8979 uint ea = M68KMAKE_GET_EA_AY_16;
8980 uint src = m68ki_read_16(ea);
8981 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
8983 FLAG_C = FLAG_X = res >> 8;
8984 res = MASK_OUT_ABOVE_16(res);
8986 m68ki_write_16(ea, res);
8988 FLAG_N = NFLAG_16(res);
8990 FLAG_V = VFLAG_CLEAR;
8994 M68KMAKE_OP(roxl, 8, s, .)
8997 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8998 uint src = MASK_OUT_ABOVE_8(*r_dst);
8999 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9002 USE_CYCLES(shift<<CYC_SHIFT);
9004 FLAG_C = FLAG_X = res;
9005 res = MASK_OUT_ABOVE_8(res);
9007 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9009 FLAG_N = NFLAG_8(res);
9011 FLAG_V = VFLAG_CLEAR;
9015 M68KMAKE_OP(roxl, 16, s, .)
9018 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9019 uint src = MASK_OUT_ABOVE_16(*r_dst);
9020 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9023 USE_CYCLES(shift<<CYC_SHIFT);
9025 FLAG_C = FLAG_X = res >> 8;
9026 res = MASK_OUT_ABOVE_16(res);
9028 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9030 FLAG_N = NFLAG_16(res);
9032 FLAG_V = VFLAG_CLEAR;
9036 M68KMAKE_OP(roxl, 32, s, .)
9041 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9042 uint64 src = *r_dst;
9043 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9046 USE_CYCLES(shift<<CYC_SHIFT);
9048 res = ROL_33_64(res, shift);
9050 FLAG_C = FLAG_X = res >> 24;
9051 res = MASK_OUT_ABOVE_32(res);
9055 FLAG_N = NFLAG_32(res);
9057 FLAG_V = VFLAG_CLEAR;
9062 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9064 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9065 uint new_x_flag = src & (1 << (32 - shift));
9068 USE_CYCLES(shift<<CYC_SHIFT);
9072 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
9073 FLAG_N = NFLAG_32(res);
9075 FLAG_V = VFLAG_CLEAR;
9081 M68KMAKE_OP(roxl, 8, r, .)
9084 uint orig_shift = DX & 0x3f;
9089 uint shift = orig_shift % 9;
9090 uint src = MASK_OUT_ABOVE_8(*r_dst);
9091 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9093 USE_CYCLES(orig_shift<<CYC_SHIFT);
9095 FLAG_C = FLAG_X = res;
9096 res = MASK_OUT_ABOVE_8(res);
9098 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9099 FLAG_N = NFLAG_8(res);
9101 FLAG_V = VFLAG_CLEAR;
9106 FLAG_N = NFLAG_8(*r_dst);
9107 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
9108 FLAG_V = VFLAG_CLEAR;
9112 M68KMAKE_OP(roxl, 16, r, .)
9115 uint orig_shift = DX & 0x3f;
9119 uint shift = orig_shift % 17;
9120 uint src = MASK_OUT_ABOVE_16(*r_dst);
9121 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9123 USE_CYCLES(orig_shift<<CYC_SHIFT);
9125 FLAG_C = FLAG_X = res >> 8;
9126 res = MASK_OUT_ABOVE_16(res);
9128 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9129 FLAG_N = NFLAG_16(res);
9131 FLAG_V = VFLAG_CLEAR;
9136 FLAG_N = NFLAG_16(*r_dst);
9137 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
9138 FLAG_V = VFLAG_CLEAR;
9142 M68KMAKE_OP(roxl, 32, r, .)
9147 uint orig_shift = DX & 0x3f;
9151 uint shift = orig_shift % 33;
9152 uint64 src = *r_dst;
9153 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9155 res = ROL_33_64(res, shift);
9157 USE_CYCLES(orig_shift<<CYC_SHIFT);
9159 FLAG_C = FLAG_X = res >> 24;
9160 res = MASK_OUT_ABOVE_32(res);
9163 FLAG_N = NFLAG_32(res);
9165 FLAG_V = VFLAG_CLEAR;
9170 FLAG_N = NFLAG_32(*r_dst);
9172 FLAG_V = VFLAG_CLEAR;
9177 uint orig_shift = DX & 0x3f;
9178 uint shift = orig_shift % 33;
9180 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9181 uint new_x_flag = src & (1 << (32 - shift));
9184 USE_CYCLES(orig_shift<<CYC_SHIFT);
9189 FLAG_X = (new_x_flag != 0)<<8;
9194 FLAG_N = NFLAG_32(res);
9196 FLAG_V = VFLAG_CLEAR;
9202 M68KMAKE_OP(roxl, 16, ., .)
9204 uint ea = M68KMAKE_GET_EA_AY_16;
9205 uint src = m68ki_read_16(ea);
9206 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
9208 FLAG_C = FLAG_X = res >> 8;
9209 res = MASK_OUT_ABOVE_16(res);
9211 m68ki_write_16(ea, res);
9213 FLAG_N = NFLAG_16(res);
9215 FLAG_V = VFLAG_CLEAR;
9219 M68KMAKE_OP(rtd, 32, ., .)
9221 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
9223 uint new_pc = m68ki_pull_32();
9225 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9226 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
9230 m68ki_exception_illegal();
9234 M68KMAKE_OP(rte, 32, ., .)
9242 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
9243 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9245 if(CPU_TYPE_IS_000(CPU_TYPE))
9247 new_sr = m68ki_pull_16();
9248 new_pc = m68ki_pull_32();
9250 m68ki_set_sr(new_sr);
9252 CPU_INSTR_MODE = INSTRUCTION_YES;
9253 CPU_RUN_MODE = RUN_MODE_NORMAL;
9258 if(CPU_TYPE_IS_010(CPU_TYPE))
9260 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9261 if(format_word == 0)
9263 new_sr = m68ki_pull_16();
9264 new_pc = m68ki_pull_32();
9265 m68ki_fake_pull_16(); /* format word */
9267 m68ki_set_sr(new_sr);
9268 CPU_INSTR_MODE = INSTRUCTION_YES;
9269 CPU_RUN_MODE = RUN_MODE_NORMAL;
9271 } else if (format_word == 8) {
9272 /* Format 8 stack frame -- 68010 only. 29 word bus/address error */
9273 new_sr = m68ki_pull_16();
9274 new_pc = m68ki_pull_32();
9275 m68ki_fake_pull_16(); /* format word */
9276 m68ki_fake_pull_16(); /* special status word */
9277 m68ki_fake_pull_32(); /* fault address */
9278 m68ki_fake_pull_16(); /* unused/reserved */
9279 m68ki_fake_pull_16(); /* data output buffer */
9280 m68ki_fake_pull_16(); /* unused/reserved */
9281 m68ki_fake_pull_16(); /* data input buffer */
9282 m68ki_fake_pull_16(); /* unused/reserved */
9283 m68ki_fake_pull_16(); /* instruction input buffer */
9284 m68ki_fake_pull_32(); /* internal information, 16 words */
9285 m68ki_fake_pull_32(); /* (actually, we use 8 DWORDs) */
9286 m68ki_fake_pull_32();
9287 m68ki_fake_pull_32();
9288 m68ki_fake_pull_32();
9289 m68ki_fake_pull_32();
9290 m68ki_fake_pull_32();
9291 m68ki_fake_pull_32();
9293 m68ki_set_sr(new_sr);
9294 CPU_INSTR_MODE = INSTRUCTION_YES;
9295 CPU_RUN_MODE = RUN_MODE_NORMAL;
9298 CPU_INSTR_MODE = INSTRUCTION_YES;
9299 CPU_RUN_MODE = RUN_MODE_NORMAL;
9300 /* Not handling other exception types (9) */
9301 m68ki_exception_format_error();
9305 /* Otherwise it's 020 */
9307 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9310 case 0: /* Normal */
9311 new_sr = m68ki_pull_16();
9312 new_pc = m68ki_pull_32();
9313 m68ki_fake_pull_16(); /* format word */
9315 m68ki_set_sr(new_sr);
9316 CPU_INSTR_MODE = INSTRUCTION_YES;
9317 CPU_RUN_MODE = RUN_MODE_NORMAL;
9319 case 1: /* Throwaway */
9320 new_sr = m68ki_pull_16();
9321 m68ki_fake_pull_32(); /* program counter */
9322 m68ki_fake_pull_16(); /* format word */
9323 m68ki_set_sr_noint(new_sr);
9326 new_sr = m68ki_pull_16();
9327 new_pc = m68ki_pull_32();
9328 m68ki_fake_pull_16(); /* format word */
9329 m68ki_fake_pull_32(); /* address */
9331 m68ki_set_sr(new_sr);
9332 CPU_INSTR_MODE = INSTRUCTION_YES;
9333 CPU_RUN_MODE = RUN_MODE_NORMAL;
9336 /* Not handling long or short bus fault */
9337 CPU_INSTR_MODE = INSTRUCTION_YES;
9338 CPU_RUN_MODE = RUN_MODE_NORMAL;
9339 m68ki_exception_format_error();
9342 m68ki_exception_privilege_violation();
9346 M68KMAKE_OP(rtm, 32, ., .)
9348 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
9350 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9351 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
9352 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
9353 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
9356 m68ki_exception_illegal();
9360 M68KMAKE_OP(rtr, 32, ., .)
9362 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9363 m68ki_set_ccr(m68ki_pull_16());
9364 m68ki_jump(m68ki_pull_32());
9368 M68KMAKE_OP(rts, 32, ., .)
9370 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9371 m68ki_jump(m68ki_pull_32());
9375 M68KMAKE_OP(sbcd, 8, rr, .)
9380 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9382 FLAG_V = ~res; /* Undefined V behavior */
9386 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9387 FLAG_X = FLAG_C = (res > 0x99) << 8;
9391 res = MASK_OUT_ABOVE_8(res);
9393 FLAG_V &= res; /* Undefined V behavior part II */
9394 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9397 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9401 M68KMAKE_OP(sbcd, 8, mm, ax7)
9403 uint src = OPER_AY_PD_8();
9404 uint ea = EA_A7_PD_8();
9405 uint dst = m68ki_read_8(ea);
9406 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9408 FLAG_V = ~res; /* Undefined V behavior */
9412 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9413 FLAG_X = FLAG_C = (res > 0x99) << 8;
9417 res = MASK_OUT_ABOVE_8(res);
9419 FLAG_V &= res; /* Undefined V behavior part II */
9420 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9423 m68ki_write_8(ea, res);
9427 M68KMAKE_OP(sbcd, 8, mm, ay7)
9429 uint src = OPER_A7_PD_8();
9430 uint ea = EA_AX_PD_8();
9431 uint dst = m68ki_read_8(ea);
9432 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9434 FLAG_V = ~res; /* Undefined V behavior */
9438 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9439 FLAG_X = FLAG_C = (res > 0x99) << 8;
9443 res = MASK_OUT_ABOVE_8(res);
9445 FLAG_V &= res; /* Undefined V behavior part II */
9446 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9449 m68ki_write_8(ea, res);
9453 M68KMAKE_OP(sbcd, 8, mm, axy7)
9455 uint src = OPER_A7_PD_8();
9456 uint ea = EA_A7_PD_8();
9457 uint dst = m68ki_read_8(ea);
9458 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9460 FLAG_V = ~res; /* Undefined V behavior */
9464 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9465 FLAG_X = FLAG_C = (res > 0x99) << 8;
9469 res = MASK_OUT_ABOVE_8(res);
9471 FLAG_V &= res; /* Undefined V behavior part II */
9472 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9475 m68ki_write_8(ea, res);
9479 M68KMAKE_OP(sbcd, 8, mm, .)
9481 uint src = OPER_AY_PD_8();
9482 uint ea = EA_AX_PD_8();
9483 uint dst = m68ki_read_8(ea);
9484 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9486 FLAG_V = ~res; /* Undefined V behavior */
9490 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9491 FLAG_X = FLAG_C = (res > 0x99) << 8;
9495 res = MASK_OUT_ABOVE_8(res);
9497 FLAG_V &= res; /* Undefined V behavior part II */
9498 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9501 m68ki_write_8(ea, res);
9505 M68KMAKE_OP(st, 8, ., d)
9511 M68KMAKE_OP(st, 8, ., .)
9513 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
9517 M68KMAKE_OP(sf, 8, ., d)
9523 M68KMAKE_OP(sf, 8, ., .)
9525 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
9529 M68KMAKE_OP(scc, 8, ., d)
9534 USE_CYCLES(CYC_SCC_R_TRUE);
9541 M68KMAKE_OP(scc, 8, ., .)
9543 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
9547 M68KMAKE_OP(stop, 0, ., .)
9551 uint new_sr = OPER_I_16();
9552 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9553 CPU_STOPPED |= STOP_LEVEL_STOP;
9554 m68ki_set_sr(new_sr);
9555 if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR])
9556 m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR];
9561 m68ki_exception_privilege_violation();
9565 M68KMAKE_OP(sub, 8, er, d)
9568 uint src = MASK_OUT_ABOVE_8(DY);
9569 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9570 uint res = dst - src;
9572 FLAG_N = NFLAG_8(res);
9573 FLAG_X = FLAG_C = CFLAG_8(res);
9574 FLAG_V = VFLAG_SUB_8(src, dst, res);
9575 FLAG_Z = MASK_OUT_ABOVE_8(res);
9577 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9581 M68KMAKE_OP(sub, 8, er, .)
9584 uint src = M68KMAKE_GET_OPER_AY_8;
9585 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9586 uint res = dst - src;
9588 FLAG_N = NFLAG_8(res);
9589 FLAG_X = FLAG_C = CFLAG_8(res);
9590 FLAG_V = VFLAG_SUB_8(src, dst, res);
9591 FLAG_Z = MASK_OUT_ABOVE_8(res);
9593 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9597 M68KMAKE_OP(sub, 16, er, d)
9600 uint src = MASK_OUT_ABOVE_16(DY);
9601 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9602 uint res = dst - src;
9604 FLAG_N = NFLAG_16(res);
9605 FLAG_X = FLAG_C = CFLAG_16(res);
9606 FLAG_V = VFLAG_SUB_16(src, dst, res);
9607 FLAG_Z = MASK_OUT_ABOVE_16(res);
9609 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9613 M68KMAKE_OP(sub, 16, er, a)
9616 uint src = MASK_OUT_ABOVE_16(AY);
9617 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9618 uint res = dst - src;
9620 FLAG_N = NFLAG_16(res);
9621 FLAG_X = FLAG_C = CFLAG_16(res);
9622 FLAG_V = VFLAG_SUB_16(src, dst, res);
9623 FLAG_Z = MASK_OUT_ABOVE_16(res);
9625 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9629 M68KMAKE_OP(sub, 16, er, .)
9632 uint src = M68KMAKE_GET_OPER_AY_16;
9633 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9634 uint res = dst - src;
9636 FLAG_N = NFLAG_16(res);
9637 FLAG_X = FLAG_C = CFLAG_16(res);
9638 FLAG_V = VFLAG_SUB_16(src, dst, res);
9639 FLAG_Z = MASK_OUT_ABOVE_16(res);
9641 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9645 M68KMAKE_OP(sub, 32, er, d)
9650 uint res = dst - src;
9652 FLAG_N = NFLAG_32(res);
9653 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9654 FLAG_V = VFLAG_SUB_32(src, dst, res);
9655 FLAG_Z = MASK_OUT_ABOVE_32(res);
9661 M68KMAKE_OP(sub, 32, er, a)
9666 uint res = dst - src;
9668 FLAG_N = NFLAG_32(res);
9669 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9670 FLAG_V = VFLAG_SUB_32(src, dst, res);
9671 FLAG_Z = MASK_OUT_ABOVE_32(res);
9677 M68KMAKE_OP(sub, 32, er, .)
9680 uint src = M68KMAKE_GET_OPER_AY_32;
9682 uint res = dst - src;
9684 FLAG_N = NFLAG_32(res);
9685 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9686 FLAG_V = VFLAG_SUB_32(src, dst, res);
9687 FLAG_Z = MASK_OUT_ABOVE_32(res);
9693 M68KMAKE_OP(sub, 8, re, .)
9695 uint ea = M68KMAKE_GET_EA_AY_8;
9696 uint src = MASK_OUT_ABOVE_8(DX);
9697 uint dst = m68ki_read_8(ea);
9698 uint res = dst - src;
9700 FLAG_N = NFLAG_8(res);
9701 FLAG_Z = MASK_OUT_ABOVE_8(res);
9702 FLAG_X = FLAG_C = CFLAG_8(res);
9703 FLAG_V = VFLAG_SUB_8(src, dst, res);
9705 m68ki_write_8(ea, FLAG_Z);
9709 M68KMAKE_OP(sub, 16, re, .)
9711 uint ea = M68KMAKE_GET_EA_AY_16;
9712 uint src = MASK_OUT_ABOVE_16(DX);
9713 uint dst = m68ki_read_16(ea);
9714 uint res = dst - src;
9716 FLAG_N = NFLAG_16(res);
9717 FLAG_Z = MASK_OUT_ABOVE_16(res);
9718 FLAG_X = FLAG_C = CFLAG_16(res);
9719 FLAG_V = VFLAG_SUB_16(src, dst, res);
9721 m68ki_write_16(ea, FLAG_Z);
9725 M68KMAKE_OP(sub, 32, re, .)
9727 uint ea = M68KMAKE_GET_EA_AY_32;
9729 uint dst = m68ki_read_32(ea);
9730 uint res = dst - src;
9732 FLAG_N = NFLAG_32(res);
9733 FLAG_Z = MASK_OUT_ABOVE_32(res);
9734 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9735 FLAG_V = VFLAG_SUB_32(src, dst, res);
9737 m68ki_write_32(ea, FLAG_Z);
9741 M68KMAKE_OP(suba, 16, ., d)
9745 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
9749 M68KMAKE_OP(suba, 16, ., a)
9753 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
9757 M68KMAKE_OP(suba, 16, ., .)
9760 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
9762 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9766 M68KMAKE_OP(suba, 32, ., d)
9770 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
9774 M68KMAKE_OP(suba, 32, ., a)
9778 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
9782 M68KMAKE_OP(suba, 32, ., .)
9784 uint src = M68KMAKE_GET_OPER_AY_32;
9787 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9791 M68KMAKE_OP(subi, 8, ., d)
9794 uint src = OPER_I_8();
9795 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9796 uint res = dst - src;
9798 FLAG_N = NFLAG_8(res);
9799 FLAG_Z = MASK_OUT_ABOVE_8(res);
9800 FLAG_X = FLAG_C = CFLAG_8(res);
9801 FLAG_V = VFLAG_SUB_8(src, dst, res);
9803 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9807 M68KMAKE_OP(subi, 8, ., .)
9809 uint src = OPER_I_8();
9810 uint ea = M68KMAKE_GET_EA_AY_8;
9811 uint dst = m68ki_read_8(ea);
9812 uint res = dst - src;
9814 FLAG_N = NFLAG_8(res);
9815 FLAG_Z = MASK_OUT_ABOVE_8(res);
9816 FLAG_X = FLAG_C = CFLAG_8(res);
9817 FLAG_V = VFLAG_SUB_8(src, dst, res);
9819 m68ki_write_8(ea, FLAG_Z);
9823 M68KMAKE_OP(subi, 16, ., d)
9826 uint src = OPER_I_16();
9827 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9828 uint res = dst - src;
9830 FLAG_N = NFLAG_16(res);
9831 FLAG_Z = MASK_OUT_ABOVE_16(res);
9832 FLAG_X = FLAG_C = CFLAG_16(res);
9833 FLAG_V = VFLAG_SUB_16(src, dst, res);
9835 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9839 M68KMAKE_OP(subi, 16, ., .)
9841 uint src = OPER_I_16();
9842 uint ea = M68KMAKE_GET_EA_AY_16;
9843 uint dst = m68ki_read_16(ea);
9844 uint res = dst - src;
9846 FLAG_N = NFLAG_16(res);
9847 FLAG_Z = MASK_OUT_ABOVE_16(res);
9848 FLAG_X = FLAG_C = CFLAG_16(res);
9849 FLAG_V = VFLAG_SUB_16(src, dst, res);
9851 m68ki_write_16(ea, FLAG_Z);
9855 M68KMAKE_OP(subi, 32, ., d)
9858 uint src = OPER_I_32();
9860 uint res = dst - src;
9862 FLAG_N = NFLAG_32(res);
9863 FLAG_Z = MASK_OUT_ABOVE_32(res);
9864 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9865 FLAG_V = VFLAG_SUB_32(src, dst, res);
9871 M68KMAKE_OP(subi, 32, ., .)
9873 uint src = OPER_I_32();
9874 uint ea = M68KMAKE_GET_EA_AY_32;
9875 uint dst = m68ki_read_32(ea);
9876 uint res = dst - src;
9878 FLAG_N = NFLAG_32(res);
9879 FLAG_Z = MASK_OUT_ABOVE_32(res);
9880 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9881 FLAG_V = VFLAG_SUB_32(src, dst, res);
9883 m68ki_write_32(ea, FLAG_Z);
9887 M68KMAKE_OP(subq, 8, ., d)
9890 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9891 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9892 uint res = dst - src;
9894 FLAG_N = NFLAG_8(res);
9895 FLAG_Z = MASK_OUT_ABOVE_8(res);
9896 FLAG_X = FLAG_C = CFLAG_8(res);
9897 FLAG_V = VFLAG_SUB_8(src, dst, res);
9899 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9903 M68KMAKE_OP(subq, 8, ., .)
9905 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9906 uint ea = M68KMAKE_GET_EA_AY_8;
9907 uint dst = m68ki_read_8(ea);
9908 uint res = dst - src;
9910 FLAG_N = NFLAG_8(res);
9911 FLAG_Z = MASK_OUT_ABOVE_8(res);
9912 FLAG_X = FLAG_C = CFLAG_8(res);
9913 FLAG_V = VFLAG_SUB_8(src, dst, res);
9915 m68ki_write_8(ea, FLAG_Z);
9919 M68KMAKE_OP(subq, 16, ., d)
9922 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9923 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9924 uint res = dst - src;
9926 FLAG_N = NFLAG_16(res);
9927 FLAG_Z = MASK_OUT_ABOVE_16(res);
9928 FLAG_X = FLAG_C = CFLAG_16(res);
9929 FLAG_V = VFLAG_SUB_16(src, dst, res);
9931 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9935 M68KMAKE_OP(subq, 16, ., a)
9939 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9943 M68KMAKE_OP(subq, 16, ., .)
9945 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9946 uint ea = M68KMAKE_GET_EA_AY_16;
9947 uint dst = m68ki_read_16(ea);
9948 uint res = dst - src;
9950 FLAG_N = NFLAG_16(res);
9951 FLAG_Z = MASK_OUT_ABOVE_16(res);
9952 FLAG_X = FLAG_C = CFLAG_16(res);
9953 FLAG_V = VFLAG_SUB_16(src, dst, res);
9955 m68ki_write_16(ea, FLAG_Z);
9959 M68KMAKE_OP(subq, 32, ., d)
9962 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9964 uint res = dst - src;
9966 FLAG_N = NFLAG_32(res);
9967 FLAG_Z = MASK_OUT_ABOVE_32(res);
9968 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9969 FLAG_V = VFLAG_SUB_32(src, dst, res);
9975 M68KMAKE_OP(subq, 32, ., a)
9979 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9983 M68KMAKE_OP(subq, 32, ., .)
9985 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9986 uint ea = M68KMAKE_GET_EA_AY_32;
9987 uint dst = m68ki_read_32(ea);
9988 uint res = dst - src;
9990 FLAG_N = NFLAG_32(res);
9991 FLAG_Z = MASK_OUT_ABOVE_32(res);
9992 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9993 FLAG_V = VFLAG_SUB_32(src, dst, res);
9995 m68ki_write_32(ea, FLAG_Z);
9999 M68KMAKE_OP(subx, 8, rr, .)
10002 uint src = MASK_OUT_ABOVE_8(DY);
10003 uint dst = MASK_OUT_ABOVE_8(*r_dst);
10004 uint res = dst - src - XFLAG_AS_1();
10006 FLAG_N = NFLAG_8(res);
10007 FLAG_X = FLAG_C = CFLAG_8(res);
10008 FLAG_V = VFLAG_SUB_8(src, dst, res);
10010 res = MASK_OUT_ABOVE_8(res);
10013 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
10017 M68KMAKE_OP(subx, 16, rr, .)
10020 uint src = MASK_OUT_ABOVE_16(DY);
10021 uint dst = MASK_OUT_ABOVE_16(*r_dst);
10022 uint res = dst - src - XFLAG_AS_1();
10024 FLAG_N = NFLAG_16(res);
10025 FLAG_X = FLAG_C = CFLAG_16(res);
10026 FLAG_V = VFLAG_SUB_16(src, dst, res);
10028 res = MASK_OUT_ABOVE_16(res);
10031 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
10035 M68KMAKE_OP(subx, 32, rr, .)
10040 uint res = dst - src - XFLAG_AS_1();
10042 FLAG_N = NFLAG_32(res);
10043 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10044 FLAG_V = VFLAG_SUB_32(src, dst, res);
10046 res = MASK_OUT_ABOVE_32(res);
10053 M68KMAKE_OP(subx, 8, mm, ax7)
10055 uint src = OPER_AY_PD_8();
10056 uint ea = EA_A7_PD_8();
10057 uint dst = m68ki_read_8(ea);
10058 uint res = dst - src - XFLAG_AS_1();
10060 FLAG_N = NFLAG_8(res);
10061 FLAG_X = FLAG_C = CFLAG_8(res);
10062 FLAG_V = VFLAG_SUB_8(src, dst, res);
10064 res = MASK_OUT_ABOVE_8(res);
10067 m68ki_write_8(ea, res);
10071 M68KMAKE_OP(subx, 8, mm, ay7)
10073 uint src = OPER_A7_PD_8();
10074 uint ea = EA_AX_PD_8();
10075 uint dst = m68ki_read_8(ea);
10076 uint res = dst - src - XFLAG_AS_1();
10078 FLAG_N = NFLAG_8(res);
10079 FLAG_X = FLAG_C = CFLAG_8(res);
10080 FLAG_V = VFLAG_SUB_8(src, dst, res);
10082 res = MASK_OUT_ABOVE_8(res);
10085 m68ki_write_8(ea, res);
10089 M68KMAKE_OP(subx, 8, mm, axy7)
10091 uint src = OPER_A7_PD_8();
10092 uint ea = EA_A7_PD_8();
10093 uint dst = m68ki_read_8(ea);
10094 uint res = dst - src - XFLAG_AS_1();
10096 FLAG_N = NFLAG_8(res);
10097 FLAG_X = FLAG_C = CFLAG_8(res);
10098 FLAG_V = VFLAG_SUB_8(src, dst, res);
10100 res = MASK_OUT_ABOVE_8(res);
10103 m68ki_write_8(ea, res);
10107 M68KMAKE_OP(subx, 8, mm, .)
10109 uint src = OPER_AY_PD_8();
10110 uint ea = EA_AX_PD_8();
10111 uint dst = m68ki_read_8(ea);
10112 uint res = dst - src - XFLAG_AS_1();
10114 FLAG_N = NFLAG_8(res);
10115 FLAG_X = FLAG_C = CFLAG_8(res);
10116 FLAG_V = VFLAG_SUB_8(src, dst, res);
10118 res = MASK_OUT_ABOVE_8(res);
10121 m68ki_write_8(ea, res);
10125 M68KMAKE_OP(subx, 16, mm, .)
10127 uint src = OPER_AY_PD_16();
10128 uint ea = EA_AX_PD_16();
10129 uint dst = m68ki_read_16(ea);
10130 uint res = dst - src - XFLAG_AS_1();
10132 FLAG_N = NFLAG_16(res);
10133 FLAG_X = FLAG_C = CFLAG_16(res);
10134 FLAG_V = VFLAG_SUB_16(src, dst, res);
10136 res = MASK_OUT_ABOVE_16(res);
10139 m68ki_write_16(ea, res);
10143 M68KMAKE_OP(subx, 32, mm, .)
10145 uint src = OPER_AY_PD_32();
10146 uint ea = EA_AX_PD_32();
10147 uint dst = m68ki_read_32(ea);
10148 uint res = dst - src - XFLAG_AS_1();
10150 FLAG_N = NFLAG_32(res);
10151 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10152 FLAG_V = VFLAG_SUB_32(src, dst, res);
10154 res = MASK_OUT_ABOVE_32(res);
10157 m68ki_write_32(ea, res);
10161 M68KMAKE_OP(swap, 32, ., .)
10165 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
10166 *r_dst = (*r_dst>>16) | FLAG_Z;
10169 FLAG_N = NFLAG_32(*r_dst);
10170 FLAG_C = CFLAG_CLEAR;
10171 FLAG_V = VFLAG_CLEAR;
10175 M68KMAKE_OP(tas, 8, ., d)
10179 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
10180 FLAG_N = NFLAG_8(*r_dst);
10181 FLAG_V = VFLAG_CLEAR;
10182 FLAG_C = CFLAG_CLEAR;
10187 M68KMAKE_OP(tas, 8, ., .)
10189 uint ea = M68KMAKE_GET_EA_AY_8;
10190 uint dst = m68ki_read_8(ea);
10191 uint allow_writeback;
10194 FLAG_N = NFLAG_8(dst);
10195 FLAG_V = VFLAG_CLEAR;
10196 FLAG_C = CFLAG_CLEAR;
10198 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
10199 disabled in order to function properly. Some Amiga software may also rely
10200 on this, but only when accessing specific addresses so additional functionality
10202 allow_writeback = m68ki_tas_callback();
10204 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
10208 M68KMAKE_OP(trap, 0, ., .)
10210 /* Trap#n stacks exception frame type 0 */
10211 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
10215 M68KMAKE_OP(trapt, 0, ., .)
10217 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10219 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10222 m68ki_exception_illegal();
10226 M68KMAKE_OP(trapt, 16, ., .)
10228 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10230 REG_PC += 2; // JFF else stackframe & return addresses are incorrect
10231 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10234 m68ki_exception_illegal();
10238 M68KMAKE_OP(trapt, 32, ., .)
10240 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10242 REG_PC += 4; // JFF else stackframe & return addresses are incorrect
10243 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10246 m68ki_exception_illegal();
10250 M68KMAKE_OP(trapf, 0, ., .)
10252 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10256 m68ki_exception_illegal();
10260 M68KMAKE_OP(trapf, 16, ., .)
10262 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10267 m68ki_exception_illegal();
10271 M68KMAKE_OP(trapf, 32, ., .)
10273 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10278 m68ki_exception_illegal();
10282 M68KMAKE_OP(trapcc, 0, ., .)
10284 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10287 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10290 m68ki_exception_illegal();
10294 M68KMAKE_OP(trapcc, 16, ., .)
10296 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10298 REG_PC += 2; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10301 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10307 m68ki_exception_illegal();
10311 M68KMAKE_OP(trapcc, 32, ., .)
10313 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10315 REG_PC += 4; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10318 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10323 m68ki_exception_illegal();
10327 M68KMAKE_OP(trapv, 0, ., .)
10333 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10337 M68KMAKE_OP(tst, 8, ., d)
10339 uint res = MASK_OUT_ABOVE_8(DY);
10341 FLAG_N = NFLAG_8(res);
10343 FLAG_V = VFLAG_CLEAR;
10344 FLAG_C = CFLAG_CLEAR;
10348 M68KMAKE_OP(tst, 8, ., .)
10350 uint res = M68KMAKE_GET_OPER_AY_8;
10352 FLAG_N = NFLAG_8(res);
10354 FLAG_V = VFLAG_CLEAR;
10355 FLAG_C = CFLAG_CLEAR;
10359 M68KMAKE_OP(tst, 8, ., pcdi)
10361 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10363 uint res = OPER_PCDI_8();
10365 FLAG_N = NFLAG_8(res);
10367 FLAG_V = VFLAG_CLEAR;
10368 FLAG_C = CFLAG_CLEAR;
10371 m68ki_exception_illegal();
10375 M68KMAKE_OP(tst, 8, ., pcix)
10377 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10379 uint res = OPER_PCIX_8();
10381 FLAG_N = NFLAG_8(res);
10383 FLAG_V = VFLAG_CLEAR;
10384 FLAG_C = CFLAG_CLEAR;
10387 m68ki_exception_illegal();
10391 M68KMAKE_OP(tst, 8, ., i)
10393 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10395 uint res = OPER_I_8();
10397 FLAG_N = NFLAG_8(res);
10399 FLAG_V = VFLAG_CLEAR;
10400 FLAG_C = CFLAG_CLEAR;
10403 m68ki_exception_illegal();
10407 M68KMAKE_OP(tst, 16, ., d)
10409 uint res = MASK_OUT_ABOVE_16(DY);
10411 FLAG_N = NFLAG_16(res);
10413 FLAG_V = VFLAG_CLEAR;
10414 FLAG_C = CFLAG_CLEAR;
10418 M68KMAKE_OP(tst, 16, ., a)
10420 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10422 uint res = MAKE_INT_16(AY);
10424 FLAG_N = NFLAG_16(res);
10426 FLAG_V = VFLAG_CLEAR;
10427 FLAG_C = CFLAG_CLEAR;
10430 m68ki_exception_illegal();
10434 M68KMAKE_OP(tst, 16, ., .)
10436 uint res = M68KMAKE_GET_OPER_AY_16;
10438 FLAG_N = NFLAG_16(res);
10440 FLAG_V = VFLAG_CLEAR;
10441 FLAG_C = CFLAG_CLEAR;
10445 M68KMAKE_OP(tst, 16, ., pcdi)
10447 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10449 uint res = OPER_PCDI_16();
10451 FLAG_N = NFLAG_16(res);
10453 FLAG_V = VFLAG_CLEAR;
10454 FLAG_C = CFLAG_CLEAR;
10457 m68ki_exception_illegal();
10461 M68KMAKE_OP(tst, 16, ., pcix)
10463 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10465 uint res = OPER_PCIX_16();
10467 FLAG_N = NFLAG_16(res);
10469 FLAG_V = VFLAG_CLEAR;
10470 FLAG_C = CFLAG_CLEAR;
10473 m68ki_exception_illegal();
10477 M68KMAKE_OP(tst, 16, ., i)
10479 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10481 uint res = OPER_I_16();
10483 FLAG_N = NFLAG_16(res);
10485 FLAG_V = VFLAG_CLEAR;
10486 FLAG_C = CFLAG_CLEAR;
10489 m68ki_exception_illegal();
10493 M68KMAKE_OP(tst, 32, ., d)
10497 FLAG_N = NFLAG_32(res);
10499 FLAG_V = VFLAG_CLEAR;
10500 FLAG_C = CFLAG_CLEAR;
10504 M68KMAKE_OP(tst, 32, ., a)
10506 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10510 FLAG_N = NFLAG_32(res);
10512 FLAG_V = VFLAG_CLEAR;
10513 FLAG_C = CFLAG_CLEAR;
10516 m68ki_exception_illegal();
10520 M68KMAKE_OP(tst, 32, ., .)
10522 uint res = M68KMAKE_GET_OPER_AY_32;
10524 FLAG_N = NFLAG_32(res);
10526 FLAG_V = VFLAG_CLEAR;
10527 FLAG_C = CFLAG_CLEAR;
10531 M68KMAKE_OP(tst, 32, ., pcdi)
10533 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10535 uint res = OPER_PCDI_32();
10537 FLAG_N = NFLAG_32(res);
10539 FLAG_V = VFLAG_CLEAR;
10540 FLAG_C = CFLAG_CLEAR;
10543 m68ki_exception_illegal();
10547 M68KMAKE_OP(tst, 32, ., pcix)
10549 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10551 uint res = OPER_PCIX_32();
10553 FLAG_N = NFLAG_32(res);
10555 FLAG_V = VFLAG_CLEAR;
10556 FLAG_C = CFLAG_CLEAR;
10559 m68ki_exception_illegal();
10563 M68KMAKE_OP(tst, 32, ., i)
10565 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10567 uint res = OPER_I_32();
10569 FLAG_N = NFLAG_32(res);
10571 FLAG_V = VFLAG_CLEAR;
10572 FLAG_C = CFLAG_CLEAR;
10575 m68ki_exception_illegal();
10579 M68KMAKE_OP(unlk, 32, ., a7)
10581 REG_A[7] = m68ki_read_32(REG_A[7]);
10585 M68KMAKE_OP(unlk, 32, ., .)
10590 *r_dst = m68ki_pull_32();
10594 M68KMAKE_OP(unpk, 16, rr, .)
10596 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10598 /* Note: DX and DY are reversed in Motorola's docs */
10602 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
10605 m68ki_exception_illegal();
10609 M68KMAKE_OP(unpk, 16, mm, ax7)
10611 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10613 /* Note: AX and AY are reversed in Motorola's docs */
10614 uint src = OPER_AY_PD_8();
10617 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10618 ea_dst = EA_A7_PD_8();
10619 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10620 ea_dst = EA_A7_PD_8();
10621 m68ki_write_8(ea_dst, src & 0xff);
10624 m68ki_exception_illegal();
10628 M68KMAKE_OP(unpk, 16, mm, ay7)
10630 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10632 /* Note: AX and AY are reversed in Motorola's docs */
10633 uint src = OPER_A7_PD_8();
10636 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10637 ea_dst = EA_AX_PD_8();
10638 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10639 ea_dst = EA_AX_PD_8();
10640 m68ki_write_8(ea_dst, src & 0xff);
10643 m68ki_exception_illegal();
10647 M68KMAKE_OP(unpk, 16, mm, axy7)
10649 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10651 uint src = OPER_A7_PD_8();
10654 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10655 ea_dst = EA_A7_PD_8();
10656 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10657 ea_dst = EA_A7_PD_8();
10658 m68ki_write_8(ea_dst, src & 0xff);
10661 m68ki_exception_illegal();
10665 M68KMAKE_OP(unpk, 16, mm, .)
10667 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10669 /* Note: AX and AY are reversed in Motorola's docs */
10670 uint src = OPER_AY_PD_8();
10673 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10674 ea_dst = EA_AX_PD_8();
10675 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10676 ea_dst = EA_AX_PD_8();
10677 m68ki_write_8(ea_dst, src & 0xff);
10680 m68ki_exception_illegal();
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projects / pistorm / blob