#include <stdio.h>
#include "m68kcpu.h"
-extern void m68040_fpu_op0(void);
-extern void m68040_fpu_op1(void);
-extern void m68851_mmu_ops();
-extern void m68881_ftrap();
+extern void m68040_fpu_op0(m68ki_cpu_core *state);
+extern void m68040_fpu_op1(m68ki_cpu_core *state);
+extern void m68851_mmu_ops(m68ki_cpu_core *state);
+extern void m68881_ftrap(m68ki_cpu_core *state);
/* ======================================================================== */
/* ========================= INSTRUCTION HANDLERS ========================= */
// printf("FPU 040fpu0 HAS_FPU=%d\n",!!HAS_FPU);
if(HAS_FPU)
{
- m68040_fpu_op0();
+ void m68040_fpu_op0(m68ki_cpu_core *state);
return;
}
m68ki_exception_1111();
// printf("FPU 040fpu1 HAS_FPU=%d\n",!!HAS_FPU);
if(HAS_FPU)
{
- m68040_fpu_op1();
+ void m68040_fpu_op1(m68ki_cpu_core *state);
return;
}
m68ki_exception_1111();
M68KMAKE_OP(abcd, 8, mm, ax7)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_A7_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
M68KMAKE_OP(abcd, 8, mm, ay7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_AX_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
M68KMAKE_OP(abcd, 8, mm, axy7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_A7_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
M68KMAKE_OP(abcd, 8, mm, .)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_AX_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
M68KMAKE_OP(addi, 8, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint dst = MASK_OUT_ABOVE_8(*r_dst);
uint res = src + dst;
M68KMAKE_OP(addi, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
uint dst = m68ki_read_8(ea);
uint res = src + dst;
M68KMAKE_OP(addi, 16, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint dst = MASK_OUT_ABOVE_16(*r_dst);
uint res = src + dst;
M68KMAKE_OP(addi, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint dst = m68ki_read_16(ea);
uint res = src + dst;
M68KMAKE_OP(addi, 32, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint dst = *r_dst;
uint res = src + dst;
M68KMAKE_OP(addi, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint dst = m68ki_read_32(ea);
uint res = src + dst;
M68KMAKE_OP(addx, 8, mm, ax7)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_A7_PD_8();
uint dst = m68ki_read_8(ea);
uint res = src + dst + XFLAG_AS_1();
M68KMAKE_OP(addx, 8, mm, ay7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_AX_PD_8();
uint dst = m68ki_read_8(ea);
uint res = src + dst + XFLAG_AS_1();
M68KMAKE_OP(addx, 8, mm, axy7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_A7_PD_8();
uint dst = m68ki_read_8(ea);
uint res = src + dst + XFLAG_AS_1();
M68KMAKE_OP(addx, 8, mm, .)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_AX_PD_8();
uint dst = m68ki_read_8(ea);
uint res = src + dst + XFLAG_AS_1();
M68KMAKE_OP(addx, 16, mm, .)
{
- uint src = OPER_AY_PD_16();
+ uint src = OPER_AY_PD_16(state);
uint ea = EA_AX_PD_16();
uint dst = m68ki_read_16(ea);
uint res = src + dst + XFLAG_AS_1();
M68KMAKE_OP(addx, 32, mm, .)
{
- uint src = OPER_AY_PD_32();
+ uint src = OPER_AY_PD_32(state);
uint ea = EA_AX_PD_32();
uint dst = m68ki_read_32(ea);
uint res = src + dst + XFLAG_AS_1();
M68KMAKE_OP(andi, 8, ., d)
{
- FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
+ FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8(state) | 0xffffff00));
FLAG_N = NFLAG_8(FLAG_Z);
FLAG_C = CFLAG_CLEAR;
M68KMAKE_OP(andi, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
uint res = src & m68ki_read_8(ea);
M68KMAKE_OP(andi, 16, ., d)
{
- FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
+ FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16(state) | 0xffff0000));
FLAG_N = NFLAG_16(FLAG_Z);
FLAG_C = CFLAG_CLEAR;
M68KMAKE_OP(andi, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint res = src & m68ki_read_16(ea);
M68KMAKE_OP(andi, 32, ., d)
{
- FLAG_Z = DY &= (OPER_I_32());
+ FLAG_Z = DY &= (OPER_I_32(state));
FLAG_N = NFLAG_32(FLAG_Z);
FLAG_C = CFLAG_CLEAR;
M68KMAKE_OP(andi, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint res = src & m68ki_read_32(ea);
M68KMAKE_OP(andi, 16, toc, .)
{
- m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8());
+ m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8(state));
}
{
if(FLAG_S)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_set_sr(m68ki_get_sr() & src);
+ m68ki_set_sr(state, m68ki_get_sr() & src);
return;
}
m68ki_exception_privilege_violation();
{
if(M68KMAKE_CC)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
REG_PC -= 2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_branch_16(offset);
{
if(M68KMAKE_CC)
{
- uint offset = OPER_I_32();
+ uint offset = OPER_I_32(state);
REG_PC -= 4;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_branch_32(offset);
M68KMAKE_OP(bchg, 32, s, d)
{
uint* r_dst = &DY;
- uint mask = 1 << (OPER_I_8() & 0x1f);
+ uint mask = 1 << (OPER_I_8(state) & 0x1f);
FLAG_Z = *r_dst & mask;
*r_dst ^= mask;
M68KMAKE_OP(bchg, 8, s, .)
{
- uint mask = 1 << (OPER_I_8() & 7);
+ uint mask = 1 << (OPER_I_8(state) & 7);
uint ea = M68KMAKE_GET_EA_AY_8;
uint src = m68ki_read_8(ea);
M68KMAKE_OP(bclr, 32, s, d)
{
uint* r_dst = &DY;
- uint mask = 1 << (OPER_I_8() & 0x1f);
+ uint mask = 1 << (OPER_I_8(state) & 0x1f);
FLAG_Z = *r_dst & mask;
*r_dst &= ~mask;
M68KMAKE_OP(bclr, 8, s, .)
{
- uint mask = 1 << (OPER_I_8() & 7);
+ uint mask = 1 << (OPER_I_8(state) & 7);
uint ea = M68KMAKE_GET_EA_AY_8;
uint src = m68ki_read_8(ea);
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint mask_base;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint mask_base;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint64 data = DY;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint data;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint64 data = DY;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint data;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint64 data = DY;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
sint local_offset;
uint width = word2;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint insert_base = REG_D[(word2>>12)&7];
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint mask_base;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint offset = (word2>>6)&31;
uint width = word2;
uint* data = &DY;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint offset = (word2>>6)&31;
uint width = word2;
uint mask_base;
M68KMAKE_OP(bra, 16, ., .)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
REG_PC -= 2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_branch_16(offset);
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint offset = OPER_I_32();
+ uint offset = OPER_I_32(state);
REG_PC -= 4;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_branch_32(offset);
M68KMAKE_OP(bset, 32, s, d)
{
uint* r_dst = &DY;
- uint mask = 1 << (OPER_I_8() & 0x1f);
+ uint mask = 1 << (OPER_I_8(state) & 0x1f);
FLAG_Z = *r_dst & mask;
*r_dst |= mask;
M68KMAKE_OP(bset, 8, s, .)
{
- uint mask = 1 << (OPER_I_8() & 7);
+ uint mask = 1 << (OPER_I_8(state) & 7);
uint ea = M68KMAKE_GET_EA_AY_8;
uint src = m68ki_read_8(ea);
M68KMAKE_OP(bsr, 16, ., .)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_push_32(REG_PC);
REG_PC -= 2;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint offset = OPER_I_32();
+ uint offset = OPER_I_32(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_push_32(REG_PC);
REG_PC -= 4;
M68KMAKE_OP(btst, 32, s, d)
{
- FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
+ FLAG_Z = DY & (1 << (OPER_I_8(state) & 0x1f));
}
M68KMAKE_OP(btst, 8, s, .)
{
- uint bit = OPER_I_8() & 7;
+ uint bit = OPER_I_8(state) & 7;
FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_8;
uint dest = m68ki_read_8(ea);
uint* compare = ®_D[word2 & 7];
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint dest = m68ki_read_16(ea);
uint* compare = ®_D[word2 & 7];
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint dest = m68ki_read_32(ea);
uint* compare = ®_D[word2 & 7];
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_32();
+ uint word2 = OPER_I_32(state);
uint* compare1 = ®_D[(word2 >> 16) & 7];
uint ea1 = REG_DA[(word2 >> 28) & 15];
uint dest1 = m68ki_read_16(ea1);
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_32();
+ uint word2 = OPER_I_32(state);
uint* compare1 = ®_D[(word2 >> 16) & 7];
uint ea1 = REG_DA[(word2 >> 28) & 15];
uint dest1 = m68ki_read_32(ea1);
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xff;
return;
}
-
+
m68ki_exception_illegal();
}
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xff;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xff;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xffff;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xffff;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
sint compare = REG_DA[(word2 >> 12) & 15];
if(!BIT_F(word2))
compare &= 0xffff;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint32 word2 = OPER_I_16();
+ uint32 word2 = OPER_I_16(state);
sint64 compare = REG_DA[(word2 >> 12) & 15];
uint32 ea = EA_PCDI_32();
sint64 lower_bound = m68ki_read_pcrel_32(ea);
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint32 word2 = OPER_I_16();
+ uint32 word2 = OPER_I_16(state);
sint64 compare = REG_DA[(word2 >> 12) & 15];
uint32 ea = EA_PCIX_32();
sint64 lower_bound = m68ki_read_32(ea);
M68KMAKE_OP(chk2cmp2, 32, ., .)
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
- {
- uint32 word2 = OPER_I_16();
+ {
+ uint32 word2 = OPER_I_16(state);
sint64 compare = REG_DA[(word2 >> 12) & 15];
uint32 ea = M68KMAKE_GET_EA_AY_32;
sint64 lower_bound = m68ki_read_32(ea);
M68KMAKE_OP(cmpi, 8, ., d)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint dst = MASK_OUT_ABOVE_8(DY);
uint res = dst - src;
M68KMAKE_OP(cmpi, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint dst = M68KMAKE_GET_OPER_AY_8;
uint res = dst - src;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_8();
- uint dst = OPER_PCDI_8();
+ uint src = OPER_I_8(state);
+ uint dst = OPER_PCDI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_8();
- uint dst = OPER_PCIX_8();
+ uint src = OPER_I_8(state);
+ uint dst = OPER_PCIX_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
M68KMAKE_OP(cmpi, 16, ., d)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint dst = MASK_OUT_ABOVE_16(DY);
uint res = dst - src;
M68KMAKE_OP(cmpi, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint dst = M68KMAKE_GET_OPER_AY_16;
uint res = dst - src;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_16();
- uint dst = OPER_PCDI_16();
+ uint src = OPER_I_16(state);
+ uint dst = OPER_PCDI_16(state);
uint res = dst - src;
FLAG_N = NFLAG_16(res);
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_16();
- uint dst = OPER_PCIX_16();
+ uint src = OPER_I_16(state);
+ uint dst = OPER_PCIX_16(state);
uint res = dst - src;
FLAG_N = NFLAG_16(res);
M68KMAKE_OP(cmpi, 32, ., d)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint dst = DY;
uint res = dst - src;
M68KMAKE_OP(cmpi, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint dst = M68KMAKE_GET_OPER_AY_32;
uint res = dst - src;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_32();
- uint dst = OPER_PCDI_32();
+ uint src = OPER_I_32(state);
+ uint dst = OPER_PCDI_32(state);
uint res = dst - src;
FLAG_N = NFLAG_32(res);
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_I_32();
- uint dst = OPER_PCIX_32();
+ uint src = OPER_I_32(state);
+ uint dst = OPER_PCIX_32(state);
uint res = dst - src;
FLAG_N = NFLAG_32(res);
M68KMAKE_OP(cmpm, 8, ., ax7)
{
- uint src = OPER_AY_PI_8();
- uint dst = OPER_A7_PI_8();
+ uint src = OPER_AY_PI_8(state);
+ uint dst = OPER_A7_PI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
M68KMAKE_OP(cmpm, 8, ., ay7)
{
- uint src = OPER_A7_PI_8();
- uint dst = OPER_AX_PI_8();
+ uint src = OPER_A7_PI_8(state);
+ uint dst = OPER_AX_PI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
M68KMAKE_OP(cmpm, 8, ., axy7)
{
- uint src = OPER_A7_PI_8();
- uint dst = OPER_A7_PI_8();
+ uint src = OPER_A7_PI_8(state);
+ uint dst = OPER_A7_PI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
M68KMAKE_OP(cmpm, 8, ., .)
{
- uint src = OPER_AY_PI_8();
- uint dst = OPER_AX_PI_8();
+ uint src = OPER_AY_PI_8(state);
+ uint dst = OPER_AX_PI_8(state);
uint res = dst - src;
FLAG_N = NFLAG_8(res);
M68KMAKE_OP(cmpm, 16, ., .)
{
- uint src = OPER_AY_PI_16();
- uint dst = OPER_AX_PI_16();
+ uint src = OPER_AY_PI_16(state);
+ uint dst = OPER_AX_PI_16(state);
uint res = dst - src;
FLAG_N = NFLAG_16(res);
M68KMAKE_OP(cmpm, 32, ., .)
{
- uint src = OPER_AY_PI_32();
- uint dst = OPER_AX_PI_32();
+ uint src = OPER_AY_PI_32(state);
+ uint dst = OPER_AX_PI_32(state);
uint res = dst - src;
FLAG_N = NFLAG_32(res);
m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE)));
// JFF: unsupported, but at least if the trap doesn't occur, app should still work, so at least PC increase is correct
- REG_PC += 4;
+ REG_PC += 4;
return;
}
m68ki_exception_1111();
{
if(HAS_FPU)
{
- m68881_ftrap();
+ m68881_ftrap(state);
} else {
m68ki_exception_1111();
}
*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
if(res != 0xffff)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
REG_PC -= 2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_branch_16(offset);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
if(res != 0xffff)
{
- uint offset = OPER_I_16();
+ uint offset = OPER_I_16(state);
REG_PC -= 2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_branch_16(offset);
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint64 divisor = DY;
uint64 dividend = 0;
uint64 quotient = 0;
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint divisor = DY;
uint dividend_hi = REG_D[word2 & 7];
uint dividend_lo = REG_D[(word2 >> 12) & 7];
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint64 divisor = M68KMAKE_GET_OPER_AY_32;
uint64 dividend = 0;
uint64 quotient = 0;
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint divisor = M68KMAKE_GET_OPER_AY_32;
uint dividend_hi = REG_D[word2 & 7];
uint dividend_lo = REG_D[(word2 >> 12) & 7];
M68KMAKE_OP(eori, 8, ., d)
{
- uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
+ uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8(state));
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
uint res = src ^ m68ki_read_8(ea);
M68KMAKE_OP(eori, 16, ., d)
{
- uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
+ uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16(state));
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint res = src ^ m68ki_read_16(ea);
M68KMAKE_OP(eori, 32, ., d)
{
- uint res = DY ^= OPER_I_32();
+ uint res = DY ^= OPER_I_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
M68KMAKE_OP(eori, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint res = src ^ m68ki_read_32(ea);
M68KMAKE_OP(eori, 16, toc, .)
{
- m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8());
+ m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8(state));
}
{
if(FLAG_S)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_set_sr(m68ki_get_sr() ^ src);
+ m68ki_set_sr(state, m68ki_get_sr() ^ src);
return;
}
m68ki_exception_privilege_violation();
{
REG_A[7] -= 4;
m68ki_write_32(REG_A[7], REG_A[7]);
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state)));
}
m68ki_push_32(*r_dst);
*r_dst = REG_A[7];
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state)));
}
{
REG_A[7] -= 4;
m68ki_write_32(REG_A[7], REG_A[7]);
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(state));
return;
}
m68ki_exception_illegal();
m68ki_push_32(*r_dst);
*r_dst = REG_A[7];
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(state));
return;
}
m68ki_exception_illegal();
{
if(FLAG_S)
{
- m68ki_set_sr(DY);
+ m68ki_set_sr(state, DY);
return;
}
m68ki_exception_privilege_violation();
{
uint new_sr = M68KMAKE_GET_OPER_AY_16;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
return;
}
m68ki_exception_privilege_violation();
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
switch (word2 & 0xfff)
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
switch (word2 & 0xfff)
M68KMAKE_OP(movem, 16, re, pd)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = AY;
uint count = 0;
M68KMAKE_OP(movem, 16, re, .)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint count = 0;
M68KMAKE_OP(movem, 32, re, pd)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = AY;
uint count = 0;
M68KMAKE_OP(movem, 32, re, .)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint count = 0;
M68KMAKE_OP(movem, 16, er, pi)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = AY;
uint count = 0;
M68KMAKE_OP(movem, 16, er, pcdi)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = EA_PCDI_16();
uint count = 0;
M68KMAKE_OP(movem, 16, er, pcix)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = EA_PCIX_16();
uint count = 0;
M68KMAKE_OP(movem, 16, er, .)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint count = 0;
M68KMAKE_OP(movem, 32, er, pi)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = AY;
uint count = 0;
M68KMAKE_OP(movem, 32, er, pcdi)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = EA_PCDI_32();
uint count = 0;
M68KMAKE_OP(movem, 32, er, pcix)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = EA_PCIX_32();
uint count = 0;
M68KMAKE_OP(movem, 32, er, .)
{
uint i = 0;
- uint register_list = OPER_I_16();
+ uint register_list = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint count = 0;
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_8;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
{
if(FLAG_S)
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_32;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
M68KMAKE_OP(move16, 32, ., .)
{
- uint16 w2 = OPER_I_16();
+ uint16 w2 = OPER_I_16(state);
int ax = REG_IR & 7;
int ay = (w2 >> 12) & 7;
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint64 src = DY;
uint64 dst = REG_D[(word2 >> 12) & 7];
uint64 res;
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint src = DY;
uint dst = REG_D[(word2 >> 12) & 7];
uint neg = GET_MSB_32(src ^ dst);
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint64 src = M68KMAKE_GET_OPER_AY_32;
uint64 dst = REG_D[(word2 >> 12) & 7];
uint64 res;
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint word2 = OPER_I_16();
+ uint word2 = OPER_I_16(state);
uint src = M68KMAKE_GET_OPER_AY_32;
uint dst = REG_D[(word2 >> 12) & 7];
uint neg = GET_MSB_32(src ^ dst);
M68KMAKE_OP(ori, 8, ., d)
{
- uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
+ uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8(state)));
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
M68KMAKE_OP(ori, 16, ., d)
{
- uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
+ uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16(state));
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
M68KMAKE_OP(ori, 32, ., d)
{
- uint res = DY |= OPER_I_32();
+ uint res = DY |= OPER_I_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
M68KMAKE_OP(ori, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint res = src | m68ki_read_32(ea);
M68KMAKE_OP(ori, 16, toc, .)
{
- m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8());
+ m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8(state));
}
{
if(FLAG_S)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- m68ki_set_sr(m68ki_get_sr() | src);
+ m68ki_set_sr(state, m68ki_get_sr() | src);
return;
}
m68ki_exception_privilege_violation();
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
/* Note: DX and DY are reversed in Motorola's docs */
- uint src = DY + OPER_I_16();
+ uint src = DY + OPER_I_16(state);
uint* r_dst = &DX;
*r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
uint ea_src = EA_AY_PD_8();
uint src = m68ki_read_8(ea_src);
ea_src = EA_AY_PD_8();
- src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+ src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(state);
m68ki_write_8(EA_A7_PD_8(), ((src >> 8) & 0x000f) | ((src<<4) & 0x00f0));
return;
uint ea_src = EA_A7_PD_8();
uint src = m68ki_read_8(ea_src);
ea_src = EA_A7_PD_8();
- src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16();
+ src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16(state);
m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
return;
uint ea_src = EA_A7_PD_8();
uint src = m68ki_read_8(ea_src);
ea_src = EA_A7_PD_8();
- src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16();
+ src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16(state);
m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
return;
uint ea_src = EA_AY_PD_8();
uint src = m68ki_read_8(ea_src);
ea_src = EA_AY_PD_8();
- src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16();
+ src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16(state);
m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
return;
{
if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU))
{
- m68851_mmu_ops();
+ void m68851_mmu_ops(m68ki_cpu_core *state);
}
else
{
uint new_pc = m68ki_pull_32();
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
- REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state)));
m68ki_jump(new_pc);
return;
}
new_sr = m68ki_pull_16();
new_pc = m68ki_pull_32();
m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
new_pc = m68ki_pull_32();
m68ki_fake_pull_16(); /* format word */
m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
new_pc = m68ki_pull_32();
m68ki_fake_pull_16(); /* format word */
m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
m68ki_fake_pull_16(); /* special status */
new_pc = m68ki_pull_32();
m68ki_fake_pull_16(); /* format word */
m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
new_sr = m68ki_pull_16();
m68ki_fake_pull_32(); /* program counter */
m68ki_fake_pull_16(); /* format word */
- m68ki_set_sr_noint(new_sr);
+ m68ki_set_sr_noint(state, new_sr);
goto rte_loop;
case 2: /* Trap */
new_sr = m68ki_pull_16();
m68ki_fake_pull_16(); /* format word */
m68ki_fake_pull_32(); /* address */
m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
m68ki_fake_pull_32(); /* $34: pd2 */
m68ki_fake_pull_32(); /* $38: pd3 */
m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
m68ki_fake_pull_32(); /* $1c: internal registers */
m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
m68ki_fake_pull_32(); /* $58: */
m68ki_jump(new_pc);
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
CPU_INSTR_MODE = INSTRUCTION_YES;
CPU_RUN_MODE = RUN_MODE_NORMAL;
return;
M68KMAKE_OP(sbcd, 8, mm, ax7)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_A7_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
M68KMAKE_OP(sbcd, 8, mm, ay7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_AX_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
M68KMAKE_OP(sbcd, 8, mm, axy7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_A7_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
M68KMAKE_OP(sbcd, 8, mm, .)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_AX_PD_8();
uint dst = m68ki_read_8(ea);
uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
{
if(FLAG_S)
{
- uint new_sr = OPER_I_16();
+ uint new_sr = OPER_I_16(state);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
CPU_STOPPED |= STOP_LEVEL_STOP;
- m68ki_set_sr(new_sr);
+ m68ki_set_sr(state, new_sr);
if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR])
m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR];
else
M68KMAKE_OP(subi, 8, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint dst = MASK_OUT_ABOVE_8(*r_dst);
uint res = dst - src;
M68KMAKE_OP(subi, 8, ., .)
{
- uint src = OPER_I_8();
+ uint src = OPER_I_8(state);
uint ea = M68KMAKE_GET_EA_AY_8;
uint dst = m68ki_read_8(ea);
uint res = dst - src;
M68KMAKE_OP(subi, 16, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint dst = MASK_OUT_ABOVE_16(*r_dst);
uint res = dst - src;
M68KMAKE_OP(subi, 16, ., .)
{
- uint src = OPER_I_16();
+ uint src = OPER_I_16(state);
uint ea = M68KMAKE_GET_EA_AY_16;
uint dst = m68ki_read_16(ea);
uint res = dst - src;
M68KMAKE_OP(subi, 32, ., d)
{
uint* r_dst = &DY;
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint dst = *r_dst;
uint res = dst - src;
M68KMAKE_OP(subi, 32, ., .)
{
- uint src = OPER_I_32();
+ uint src = OPER_I_32(state);
uint ea = M68KMAKE_GET_EA_AY_32;
uint dst = m68ki_read_32(ea);
uint res = dst - src;
M68KMAKE_OP(subx, 8, mm, ax7)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_A7_PD_8();
uint dst = m68ki_read_8(ea);
uint res = dst - src - XFLAG_AS_1();
M68KMAKE_OP(subx, 8, mm, ay7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_AX_PD_8();
uint dst = m68ki_read_8(ea);
uint res = dst - src - XFLAG_AS_1();
M68KMAKE_OP(subx, 8, mm, axy7)
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea = EA_A7_PD_8();
uint dst = m68ki_read_8(ea);
uint res = dst - src - XFLAG_AS_1();
M68KMAKE_OP(subx, 8, mm, .)
{
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea = EA_AX_PD_8();
uint dst = m68ki_read_8(ea);
uint res = dst - src - XFLAG_AS_1();
M68KMAKE_OP(subx, 16, mm, .)
{
- uint src = OPER_AY_PD_16();
+ uint src = OPER_AY_PD_16(state);
uint ea = EA_AX_PD_16();
uint dst = m68ki_read_16(ea);
uint res = dst - src - XFLAG_AS_1();
M68KMAKE_OP(subx, 32, mm, .)
{
- uint src = OPER_AY_PD_32();
+ uint src = OPER_AY_PD_32(state);
uint ea = EA_AX_PD_32();
uint dst = m68ki_read_32(ea);
uint res = dst - src - XFLAG_AS_1();
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCDI_8();
+ uint res = OPER_PCDI_8(state);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCIX_8();
+ uint res = OPER_PCIX_8(state);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_I_8();
+ uint res = OPER_I_8(state);
FLAG_N = NFLAG_8(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCDI_16();
+ uint res = OPER_PCDI_16(state);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCIX_16();
+ uint res = OPER_PCIX_16(state);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_I_16();
+ uint res = OPER_I_16(state);
FLAG_N = NFLAG_16(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCDI_32();
+ uint res = OPER_PCDI_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_PCIX_32();
+ uint res = OPER_PCIX_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint res = OPER_I_32();
+ uint res = OPER_I_32(state);
FLAG_N = NFLAG_32(res);
FLAG_Z = res;
uint src = DY;
uint* r_dst = &DX;
- *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state)) & 0xffff);
return;
}
m68ki_exception_illegal();
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
/* Note: AX and AY are reversed in Motorola's docs */
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea_dst;
- src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
ea_dst = EA_A7_PD_8();
m68ki_write_8(ea_dst, src & 0xff);
ea_dst = EA_A7_PD_8();
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
/* Note: AX and AY are reversed in Motorola's docs */
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea_dst;
- src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
ea_dst = EA_AX_PD_8();
m68ki_write_8(ea_dst, src & 0xff);
ea_dst = EA_AX_PD_8();
{
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
- uint src = OPER_A7_PD_8();
+ uint src = OPER_A7_PD_8(state);
uint ea_dst;
- src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
ea_dst = EA_A7_PD_8();
m68ki_write_8(ea_dst, src & 0xff);
ea_dst = EA_A7_PD_8();
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
/* Note: AX and AY are reversed in Motorola's docs */
- uint src = OPER_AY_PD_8();
+ uint src = OPER_AY_PD_8(state);
uint ea_dst;
- src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state);
ea_dst = EA_AX_PD_8();
m68ki_write_8(ea_dst, src & 0xff);
ea_dst = EA_AX_PD_8();
/* ======================================================================== */
/* ================================ INCLUDES ============================== */
/* ======================================================================== */
-
-extern void m68040_fpu_op0(void);
-extern void m68040_fpu_op1(void);
-extern void m68851_mmu_ops();
+struct m68ki_cpu_core;
+extern void m68040_fpu_op0(struct m68ki_cpu_core *state);
+extern void m68040_fpu_op1(struct m68ki_cpu_core *state);
+extern void m68851_mmu_ops(struct m68ki_cpu_core *state);
extern unsigned char m68ki_cycles[][0x10000];
extern void m68ki_build_opcode_table(void);
m68ki_initial_cycles = num_cycles;
/* See if interrupts came in */
- m68ki_check_interrupts();
+ m68ki_check_interrupts(state);
/* Make sure we're not stopped */
if(!CPU_STOPPED)
/* Main loop. Keep going until we run out of clock cycles */
do
{
- /* Set tracing accodring to T1. (T0 is done inside instruction) */
+ /* Set tracing according to T1. (T0 is done inside instruction) */
m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */
/* Set the address space for reads */
#endif
/* Read an instruction and call its handler */
- REG_IR = m68ki_read_imm_16();
- m68ki_instruction_jump_table[REG_IR](&m68ki_cpu);
+ REG_IR = m68ki_read_imm_16(state);
+ m68ki_instruction_jump_table[REG_IR](state);
USE_CYCLES(CYC_INSTRUCTION[REG_IR]);
/* Trace m68k_exception, if necessary */
/* Read the initial stack pointer and program counter */
m68ki_jump(0);
- REG_SP = m68ki_read_imm_32();
- REG_PC = m68ki_read_imm_32();
+ REG_SP = m68ki_read_imm_32(state);
+ REG_PC = m68ki_read_imm_32(state);
m68ki_jump(REG_PC);
CPU_RUN_MODE = RUN_MODE_NORMAL;
RESET_CYCLES = CYC_EXCEPTION[EXCEPTION_RESET];
/* flush the MMU's cache */
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
{
#define EA_AY_PD_8() (--AY) /* predecrement (size = byte) */
#define EA_AY_PD_16() (AY-=2) /* predecrement (size = word) */
#define EA_AY_PD_32() (AY-=4) /* predecrement (size = long) */
-#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */
+#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16(state))) /* displacement */
#define EA_AY_DI_16() EA_AY_DI_8()
#define EA_AY_DI_32() EA_AY_DI_8()
-#define EA_AY_IX_8() m68ki_get_ea_ix(AY) /* indirect + index */
+#define EA_AY_IX_8() m68ki_get_ea_ix(state, AY) /* indirect + index */
#define EA_AY_IX_16() EA_AY_IX_8()
#define EA_AY_IX_32() EA_AY_IX_8()
#define EA_AX_PD_8() (--AX)
#define EA_AX_PD_16() (AX-=2)
#define EA_AX_PD_32() (AX-=4)
-#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16()))
+#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16(state)))
#define EA_AX_DI_16() EA_AX_DI_8()
#define EA_AX_DI_32() EA_AX_DI_8()
-#define EA_AX_IX_8() m68ki_get_ea_ix(AX)
+#define EA_AX_IX_8() m68ki_get_ea_ix(state, AX)
#define EA_AX_IX_16() EA_AX_IX_8()
#define EA_AX_IX_32() EA_AX_IX_8()
#define EA_A7_PI_8() ((REG_A[7]+=2)-2)
#define EA_A7_PD_8() (REG_A[7]-=2)
-#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16()) /* absolute word */
+#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16(state)) /* absolute word */
#define EA_AW_16() EA_AW_8()
#define EA_AW_32() EA_AW_8()
-#define EA_AL_8() m68ki_read_imm_32() /* absolute long */
+#define EA_AL_8() m68ki_read_imm_32(state) /* absolute long */
#define EA_AL_16() EA_AL_8()
#define EA_AL_32() EA_AL_8()
-#define EA_PCDI_8() m68ki_get_ea_pcdi() /* pc indirect + displacement */
+#define EA_PCDI_8() m68ki_get_ea_pcdi(state) /* pc indirect + displacement */
#define EA_PCDI_16() EA_PCDI_8()
#define EA_PCDI_32() EA_PCDI_8()
-#define EA_PCIX_8() m68ki_get_ea_pcix() /* pc indirect + index */
+#define EA_PCIX_8() m68ki_get_ea_pcix(state) /* pc indirect + index */
#define EA_PCIX_16() EA_PCIX_8()
#define EA_PCIX_32() EA_PCIX_8()
-#define OPER_I_8() m68ki_read_imm_8()
-#define OPER_I_16() m68ki_read_imm_16()
-#define OPER_I_32() m68ki_read_imm_32()
+#define OPER_I_8(state) m68ki_read_imm_8(state)
+#define OPER_I_16(state) m68ki_read_imm_16(state)
+#define OPER_I_32(state) m68ki_read_imm_32(state)
/* Forward declarations to keep some of the macros happy */
static inline uint m68ki_read_16_fc (uint address, uint fc);
static inline uint m68ki_read_32_fc (uint address, uint fc);
-static inline uint m68ki_get_ea_ix(uint An);
-static inline void m68ki_check_interrupts(void); /* ASG: check for interrupts */
+static inline uint m68ki_get_ea_ix(m68ki_cpu_core *state, uint An);
+static inline void m68ki_check_interrupts(m68ki_cpu_core *state); /* ASG: check for interrupts */
/* quick disassembly (used for logging) */
char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type);
}
}
-extern uint32 pmmu_translate_addr(uint32 addr_in, const uint16 rw);
+extern uint32 pmmu_translate_addr(m68ki_cpu_core *state, uint32 addr_in, uint16 rw);
// read immediate word using the instruction cache
-static inline uint m68ki_read_imm_16(void)
+static inline uint m68ki_read_imm_16(m68ki_cpu_core *state)
{
uint32_t pc = REG_PC;
return m68ki_read_imm6_addr_slowpath(pc, cache);
}
-static inline uint m68ki_read_imm_8(void)
+static inline uint m68ki_read_imm_8(m68ki_cpu_core *state)
{
/* map read immediate 8 to read immediate 16 */
- return MASK_OUT_ABOVE_8(m68ki_read_imm_16());
+ return MASK_OUT_ABOVE_8(m68ki_read_imm_16(state));
}
-static inline uint m68ki_read_imm_32(void)
+static inline uint m68ki_read_imm_32(m68ki_cpu_core *state)
{
#if M68K_SEPARATE_READS
#if M68K_EMULATE_PMMU
/* The program counter relative addressing modes cause operands to be
* retrieved from program space, not data space.
*/
-static inline uint m68ki_get_ea_pcdi(void)
+static inline uint m68ki_get_ea_pcdi(m68ki_cpu_core *state)
{
uint old_pc = REG_PC;
m68ki_use_program_space(); /* auto-disable */
- return old_pc + MAKE_INT_16(m68ki_read_imm_16());
+ return old_pc + MAKE_INT_16(m68ki_read_imm_16(state));
}
-static inline uint m68ki_get_ea_pcix(void)
+static inline uint m68ki_get_ea_pcix(m68ki_cpu_core *state)
{
m68ki_use_program_space(); /* auto-disable */
- return m68ki_get_ea_ix(REG_PC);
+ return m68ki_get_ea_ix(state, REG_PC);
}
/* Indexed addressing modes are encoded as follows:
* 1 011 mem indir with long outer
* 1 100-111 reserved
*/
-static inline uint m68ki_get_ea_ix(uint An)
+static inline uint m68ki_get_ea_ix(m68ki_cpu_core *state, uint An)
{
/* An = base register */
- uint extension = m68ki_read_imm_16();
+ uint extension = m68ki_read_imm_16(state);
uint Xn = 0; /* Index register */
uint bd = 0; /* Base Displacement */
uint od = 0; /* Outer Displacement */
/* Check if base displacement is present */
if(BIT_5(extension)) /* BD SIZE */
- bd = BIT_4(extension) ? m68ki_read_imm_32() : (uint32)MAKE_INT_16(m68ki_read_imm_16());
+ bd = BIT_4(extension) ? m68ki_read_imm_32(state) : (uint32)MAKE_INT_16(m68ki_read_imm_16(state));
/* If no indirect action, we are done */
if(!(extension&7)) /* No Memory Indirect */
/* Check if outer displacement is present */
if(BIT_1(extension)) /* I/IS: od */
- od = BIT_0(extension) ? m68ki_read_imm_32() : (uint32)MAKE_INT_16(m68ki_read_imm_16());
+ od = BIT_0(extension) ? m68ki_read_imm_32(state) : (uint32)MAKE_INT_16(m68ki_read_imm_16(state));
/* Postindex */
if(BIT_2(extension)) /* I/IS: 0 = preindex, 1 = postindex */
/* Fetch operands */
-static inline uint OPER_AY_AI_8(void) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AY_PI_8(void) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AY_PD_8(void) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AY_DI_8(void) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AY_IX_8(void) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);}
-
-static inline uint OPER_AX_AI_8(void) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AX_PI_8(void) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AX_PD_8(void) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AX_DI_8(void) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AX_IX_8(void) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);}
-
-static inline uint OPER_A7_PI_8(void) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); }
-static inline uint OPER_A7_PD_8(void) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); }
-
-static inline uint OPER_AW_8(void) {uint ea = EA_AW_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AW_16(void) {uint ea = EA_AW_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AW_32(void) {uint ea = EA_AW_32(); return m68ki_read_32(ea);}
-static inline uint OPER_AL_8(void) {uint ea = EA_AL_8(); return m68ki_read_8(ea); }
-static inline uint OPER_AL_16(void) {uint ea = EA_AL_16(); return m68ki_read_16(ea);}
-static inline uint OPER_AL_32(void) {uint ea = EA_AL_32(); return m68ki_read_32(ea);}
-static inline uint OPER_PCDI_8(void) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); }
-static inline uint OPER_PCDI_16(void) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);}
-static inline uint OPER_PCDI_32(void) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);}
-static inline uint OPER_PCIX_8(void) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); }
-static inline uint OPER_PCIX_16(void) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);}
-static inline uint OPER_PCIX_32(void) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);}
+static inline uint OPER_AY_AI_8(m68ki_cpu_core *state) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AY_AI_16(m68ki_cpu_core *state) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AY_AI_32(m68ki_cpu_core *state) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);}
+static inline uint OPER_AY_PI_8(m68ki_cpu_core *state) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AY_PI_16(m68ki_cpu_core *state) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AY_PI_32(m68ki_cpu_core *state) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);}
+static inline uint OPER_AY_PD_8(m68ki_cpu_core *state) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AY_PD_16(m68ki_cpu_core *state) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AY_PD_32(m68ki_cpu_core *state) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);}
+static inline uint OPER_AY_DI_8(m68ki_cpu_core *state) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AY_DI_16(m68ki_cpu_core *state) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AY_DI_32(m68ki_cpu_core *state) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);}
+static inline uint OPER_AY_IX_8(m68ki_cpu_core *state) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AY_IX_16(m68ki_cpu_core *state) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AY_IX_32(m68ki_cpu_core *state) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);}
+
+static inline uint OPER_AX_AI_8(m68ki_cpu_core *state) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AX_AI_16(m68ki_cpu_core *state) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AX_AI_32(m68ki_cpu_core *state) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);}
+static inline uint OPER_AX_PI_8(m68ki_cpu_core *state) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AX_PI_16(m68ki_cpu_core *state) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AX_PI_32(m68ki_cpu_core *state) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);}
+static inline uint OPER_AX_PD_8(m68ki_cpu_core *state) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AX_PD_16(m68ki_cpu_core *state) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AX_PD_32(m68ki_cpu_core *state) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);}
+static inline uint OPER_AX_DI_8(m68ki_cpu_core *state) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AX_DI_16(m68ki_cpu_core *state) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AX_DI_32(m68ki_cpu_core *state) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);}
+static inline uint OPER_AX_IX_8(m68ki_cpu_core *state) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AX_IX_16(m68ki_cpu_core *state) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AX_IX_32(m68ki_cpu_core *state) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);}
+
+static inline uint OPER_A7_PI_8(m68ki_cpu_core *state) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); }
+static inline uint OPER_A7_PD_8(m68ki_cpu_core *state) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); }
+
+static inline uint OPER_AW_8(m68ki_cpu_core *state) {uint ea = EA_AW_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AW_16(m68ki_cpu_core *state) {uint ea = EA_AW_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AW_32(m68ki_cpu_core *state) {uint ea = EA_AW_32(); return m68ki_read_32(ea);}
+static inline uint OPER_AL_8(m68ki_cpu_core *state) {uint ea = EA_AL_8(); return m68ki_read_8(ea); }
+static inline uint OPER_AL_16(m68ki_cpu_core *state) {uint ea = EA_AL_16(); return m68ki_read_16(ea);}
+static inline uint OPER_AL_32(m68ki_cpu_core *state) {uint ea = EA_AL_32(); return m68ki_read_32(ea);}
+static inline uint OPER_PCDI_8(m68ki_cpu_core *state) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); }
+static inline uint OPER_PCDI_16(m68ki_cpu_core *state) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);}
+static inline uint OPER_PCDI_32(m68ki_cpu_core *state) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);}
+static inline uint OPER_PCIX_8(m68ki_cpu_core *state) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); }
+static inline uint OPER_PCIX_16(m68ki_cpu_core *state) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);}
+static inline uint OPER_PCIX_32(m68ki_cpu_core *state) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);}
}
/* Set the status register but don't check for interrupts */
-static inline void m68ki_set_sr_noint(uint value)
+static inline void m68ki_set_sr_noint(m68ki_cpu_core *state, uint value)
{
/* Mask out the "unimplemented" bits */
value &= CPU_SR_MASK;
}
/* Set the status register and check for interrupts */
-static inline void m68ki_set_sr(uint value)
+static inline void m68ki_set_sr(m68ki_cpu_core *state, uint value)
{
- m68ki_set_sr_noint(value);
- m68ki_check_interrupts();
+ m68ki_set_sr_noint(state, value);
+ m68ki_check_interrupts(state);
}
/* ASG: Check for interrupts */
-static inline void m68ki_check_interrupts(void)
+static inline void m68ki_check_interrupts(m68ki_cpu_core *state)
{
if(m68ki_cpu.nmi_pending)
{
#include <stdarg.h>
#include "softfloat/softfloat.h"
+
float_status status;
extern void exit(int);
return r;
}
-static uint8 READ_EA_8(int ea)
+static uint8 READ_EA_8(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 0: // (xxx).W
{
- uint32 ea = (uint32)OPER_I_16();
+ uint32 ea = (uint32) OPER_I_16(state);
return m68ki_read_8(ea);
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
return m68ki_read_8(ea);
}
}
case 3: // (PC) + (Xn) + d8
{
- uint32 ea = EA_PCIX_8();
+ uint32 ea = EA_PCIX_8();
return m68ki_read_8(ea);
}
case 4: // #<data>
{
- return OPER_I_8();
+ return OPER_I_8(state);
}
default: fatalerror("M68kFPU: READ_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
return 0;
}
-static uint16 READ_EA_16(int ea)
+static uint16 READ_EA_16(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 0: // (xxx).W
{
- uint32 ea = (uint32)OPER_I_16();
+ uint32 ea = (uint32) OPER_I_16(state);
return m68ki_read_16(ea);
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
return m68ki_read_16(ea);
}
}
case 4: // #<data>
{
- return OPER_I_16();
+ return OPER_I_16(state);
}
default: fatalerror("M68kFPU: READ_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
return 0;
}
-static uint32 READ_EA_32(int ea)
+static uint32 READ_EA_32(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 0: // (xxx).W
{
- uint32 ea = (uint32)OPER_I_16();
+ uint32 ea = (uint32) OPER_I_16(state);
return m68ki_read_32(ea);
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
return m68ki_read_32(ea);
}
}
case 4: // #<data>
{
- return OPER_I_32();
+ return OPER_I_32(state);
}
default: fatalerror("M68kFPU: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
return 0;
}
-static uint64 READ_EA_64(int ea)
+static uint64 READ_EA_64(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
return (uint64)(m68ki_read_32(ea)) << 32 | (uint64)(m68ki_read_32(ea+4));
}
}
case 4: // #<data>
{
- h1 = OPER_I_32();
- h2 = OPER_I_32();
+ h1 = OPER_I_32(state);
+ h2 = OPER_I_32(state);
return (uint64)(h1) << 32 | (uint64)(h2);
}
case 2: // (d16, PC)
}
-static floatx80 READ_EA_FPE(uint32 ea)
+static floatx80 READ_EA_FPE(m68ki_cpu_core *state, uint32 ea)
{
floatx80 fpr;
int mode = (ea >> 3) & 0x7;
{
case 1: // (xxx)
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
fpr = load_extended_float80(ea);
}
return fpr;
}
-static floatx80 READ_EA_PACK(int ea)
+static floatx80 READ_EA_PACK(m68ki_cpu_core *state, int ea)
{
floatx80 fpr;
int mode = (ea >> 3) & 0x7;
return fpr;
}
-static void WRITE_EA_8(int ea, uint8 data)
+static void WRITE_EA_8(m68ki_cpu_core *state, int ea, uint8 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 1: // (xxx).B
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
m68ki_write_8(ea, data);
break;
}
}
-static void WRITE_EA_16(int ea, uint16 data)
+static void WRITE_EA_16(m68ki_cpu_core *state, int ea, uint16 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 1: // (xxx).W
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
m68ki_write_16(ea, data);
break;
}
}
-static void WRITE_EA_32(int ea, uint32 data)
+static void WRITE_EA_32(m68ki_cpu_core *state, int ea, uint32 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 0: // (xxx).W
{
- uint32 ea = OPER_I_16();
+ uint32 ea = OPER_I_16(state);
m68ki_write_32(ea, data);
break;
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
m68ki_write_32(ea, data);
break;
}
}
-static void WRITE_EA_64(int ea, uint64 data)
+static void WRITE_EA_64(m68ki_cpu_core *state, int ea, uint64 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
m68ki_write_32(ea+0, (uint32)(data >> 32));
m68ki_write_32(ea+4, (uint32)(data));
}
}
-static void WRITE_EA_FPE(uint32 ea, floatx80 fpr)
+static void WRITE_EA_FPE(m68ki_cpu_core *state, uint32 ea, floatx80 fpr)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
}
}
-static void WRITE_EA_PACK(int ea, int k, floatx80 fpr)
+static void WRITE_EA_PACK(m68ki_cpu_core *state, int ea, int k, floatx80 fpr)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
}
-static void fpgen_rm_reg(uint16 w2)
+static void fpgen_rm_reg(m68ki_cpu_core *state, uint16 w2)
{
int ea = REG_IR & 0x3f;
int rm = (w2 >> 14) & 0x1;
{
case 0: // Long-Word Integer
{
- sint32 d = READ_EA_32(ea);
+ sint32 d = READ_EA_32(state, ea);
source = int32_to_floatx80(d);
break;
}
case 1: // Single-precision Real
{
- uint32 d = READ_EA_32(ea);
+ uint32 d = READ_EA_32(state, ea);
source = float32_to_floatx80(d, &status);
break;
}
case 2: // Extended-precision Real
{
- source = READ_EA_FPE(ea);
+ source = READ_EA_FPE(state, ea);
break;
}
case 3: // Packed-decimal Real
{
- source = READ_EA_PACK(ea);
+ source = READ_EA_PACK(state, ea);
break;
}
case 4: // Word Integer
{
- sint16 d = READ_EA_16(ea);
+ sint16 d = READ_EA_16(state, ea);
source = int32_to_floatx80((sint32)d);
break;
}
case 5: // Double-precision Real
{
- uint64 d = READ_EA_64(ea);
+ uint64 d = READ_EA_64(state, ea);
source = float64_to_floatx80(d, &status);
break;
}
case 6: // Byte Integer
{
- sint8 d = READ_EA_8(ea);
+ sint8 d = READ_EA_8(state, ea);
source = int32_to_floatx80((sint32)d);
break;
}
}
}
-static void fmove_reg_mem(uint16 w2)
+static void fmove_reg_mem(m68ki_cpu_core *state, uint16 w2)
{
int ea = REG_IR & 0x3f;
int src = (w2 >> 7) & 0x7;
case 0: // Long-Word Integer
{
sint32 d = (sint32)floatx80_to_int32(REG_FP[src], &status);
- WRITE_EA_32(ea, d);
+ WRITE_EA_32(state, ea, d);
break;
}
case 1: // Single-precision Real
{
uint32 d = floatx80_to_float32(REG_FP[src], &status);
- WRITE_EA_32(ea, d);
+ WRITE_EA_32(state, ea, d);
break;
}
case 2: // Extended-precision Real
{
- WRITE_EA_FPE(ea, REG_FP[src]);
+ WRITE_EA_FPE(state, ea, REG_FP[src]);
break;
}
case 3: // Packed-decimal Real with Static K-factor
{
// sign-extend k
k = (k & 0x40) ? (k | 0xffffff80) : (k & 0x7f);
- WRITE_EA_PACK(ea, k, REG_FP[src]);
+ WRITE_EA_PACK(state, ea, k, REG_FP[src]);
break;
}
case 4: // Word Integer
{
REG_FPSR |= FPES_OE | FPAE_IOP;
}
- WRITE_EA_16(ea, (sint16)value);
+ WRITE_EA_16(state, ea, (sint16) value);
break;
}
case 5: // Double-precision Real
d = floatx80_to_float64(REG_FP[src], &status);
- WRITE_EA_64(ea, d);
+ WRITE_EA_64(state, ea, d);
break;
}
case 6: // Byte Integer
{
REG_FPSR |= FPES_OE | FPAE_IOP;
}
- WRITE_EA_8(ea, (sint8)value);
+ WRITE_EA_8(state, ea, (sint8) value);
break;
}
case 7: // Packed-decimal Real with Dynamic K-factor
{
- WRITE_EA_PACK(ea, REG_D[k>>4], REG_FP[src]);
+ WRITE_EA_PACK(state, ea, REG_D[k >> 4], REG_FP[src]);
break;
}
}
USE_CYCLES(12);
}
-static void fmove_fpcr(uint16 w2)
+static void fmove_fpcr(m68ki_cpu_core *state, uint16 w2)
{
int ea = REG_IR & 0x3f;
int dir = (w2 >> 13) & 0x1;
{
if (dir) // From system control reg to <ea>
{
- if (regsel & 4) WRITE_EA_32(ea, REG_FPCR);
- if (regsel & 2) WRITE_EA_32(ea, REG_FPSR);
- if (regsel & 1) WRITE_EA_32(ea, REG_FPIAR);
+ if (regsel & 4) WRITE_EA_32(state, ea, REG_FPCR);
+ if (regsel & 2) WRITE_EA_32(state, ea, REG_FPSR);
+ if (regsel & 1) WRITE_EA_32(state, ea, REG_FPIAR);
}
else // From <ea> to system control reg
{
- if (regsel & 4) REG_FPCR = READ_EA_32(ea);
- if (regsel & 2) REG_FPSR = READ_EA_32(ea);
- if (regsel & 1) REG_FPIAR = READ_EA_32(ea);
+ if (regsel & 4) REG_FPCR = READ_EA_32(state, ea);
+ if (regsel & 2) REG_FPSR = READ_EA_32(state, ea);
+ if (regsel & 1) REG_FPIAR = READ_EA_32(state, ea);
}
}
USE_CYCLES(10);
}
-static void fmovem(uint16 w2)
+static void fmovem(m68ki_cpu_core *state, uint16 w2)
{
int i;
int ea = REG_IR & 0x3f;
mem_addr += 12;
break;
default:
- WRITE_EA_FPE(ea, REG_FP[i]);
+ WRITE_EA_FPE(state, ea, REG_FP[i]);
break;
}
mem_addr += 12;
break;
default:
- WRITE_EA_FPE(ea, REG_FP[7-i]);
+ WRITE_EA_FPE(state, ea, REG_FP[7 - i]);
break;
}
mem_addr += 12;
break;
default:
- REG_FP[7-i] = READ_EA_FPE(ea);
+ REG_FP[7-i] = READ_EA_FPE(state, ea);
break;
}
USE_CYCLES(2);
}
}
-static void fscc()
+static void fscc(m68ki_cpu_core *state)
{
int ea = REG_IR & 0x3f;
- int condition = (sint16)(OPER_I_16());
+ int condition = (sint16)(OPER_I_16(state));
- WRITE_EA_8(ea, TEST_CONDITION(condition) ? 0xff : 0);
+ WRITE_EA_8(state, ea, TEST_CONDITION(condition) ? 0xff : 0);
USE_CYCLES(7); // ???
}
-static void fbcc16(void)
+static void fbcc16(m68ki_cpu_core *state)
{
sint32 offset;
int condition = REG_IR & 0x3f;
- offset = (sint16)(OPER_I_16());
+ offset = (sint16)(OPER_I_16(state));
// TODO: condition and jump!!!
if (TEST_CONDITION(condition))
USE_CYCLES(7);
}
-static void fbcc32(void)
+static void fbcc32(m68ki_cpu_core *state)
{
sint32 offset;
int condition = REG_IR & 0x3f;
- offset = OPER_I_32();
+ offset = OPER_I_32(state);
// TODO: condition and jump!!!
if (TEST_CONDITION(condition))
}
-void m68040_fpu_op0()
+void m68040_fpu_op0(m68ki_cpu_core *state)
{
m68ki_cpu.fpu_just_reset = 0;
{
case 0:
{
- uint16 w2 = OPER_I_16();
+ uint16 w2 = OPER_I_16(state);
switch ((w2 >> 13) & 0x7)
{
case 0x0: // FPU ALU FP, FP
case 0x2: // FPU ALU ea, FP
{
- fpgen_rm_reg(w2);
+ fpgen_rm_reg(state, w2);
break;
}
case 0x3: // FMOVE FP, ea
{
- fmove_reg_mem(w2);
+ fmove_reg_mem(state, w2);
break;
}
case 0x4: // FMOVEM ea, FPCR
case 0x5: // FMOVEM FPCR, ea
{
- fmove_fpcr(w2);
+ fmove_fpcr(state, w2);
break;
}
case 0x6: // FMOVEM ea, list
case 0x7: // FMOVEM list, ea
{
- fmovem(w2);
+ fmovem(state, w2);
break;
}
printf("M68kFPU: unimplemented FDBcc main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4);
break;
default: // FScc (?)
- fscc();
+ fscc(state);
return;
}
fatalerror("M68kFPU: unimplemented main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4);
}
case 2: // FBcc disp16
{
- fbcc16();
+ fbcc16(state);
break;
}
case 3: // FBcc disp32
{
- fbcc32();
+ fbcc32(state);
break;
}
}
}
-static int perform_fsave(uint32 addr, int inc)
+static int perform_fsave(m68ki_cpu_core *state, uint32 addr, int inc)
{
if(m68ki_cpu.cpu_type & CPU_TYPE_040)
{
}
// FRESTORE on a NULL frame reboots the FPU - all registers to NaN, the 3 status regs to 0
-static void do_frestore_null(void)
+static void do_frestore_null(m68ki_cpu_core *state)
{
int i;
m68ki_cpu.fpu_just_reset = 1;
}
-void m68040_do_fsave(uint32 addr, int reg, int inc)
+void m68040_do_fsave(m68ki_cpu_core *state, uint32 addr, int reg, int inc)
{
if (m68ki_cpu.fpu_just_reset)
{
else
{
// we normally generate an IDLE frame
- int delta = perform_fsave(addr, inc);
+ int delta = perform_fsave(state, addr, inc);
if(reg != -1)
REG_A[reg] += delta;
}
}
-void m68040_do_frestore(uint32 addr, int reg)
+void m68040_do_frestore(m68ki_cpu_core *state, uint32 addr, int reg)
{
uint32 temp = m68ki_read_32(addr);
// check for nullptr frame
}
else
{
- do_frestore_null();
+ do_frestore_null(state);
}
}
-void m68040_fpu_op1()
+void m68040_fpu_op1(m68ki_cpu_core *state)
{
int ea = REG_IR & 0x3f;
int mode = (ea >> 3) & 0x7;
{
case 2: // (An)
addr = REG_A[reg];
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
case 3: // (An)+
addr = EA_AY_PI_32();
printf("FSAVE mode %d, reg A%d=0x%08x\n",mode,reg,REG_A[reg]);
- m68040_do_fsave(addr, -1, 1); // FIXME: -1 was reg
+ m68040_do_fsave(state, addr, -1, 1); // FIXME: -1 was reg
break;
case 4: // -(An)
addr = EA_AY_PD_32();
- m68040_do_fsave(addr, reg, 0); // FIXME: -1 was reg
+ m68040_do_fsave(state, addr, reg, 0); // FIXME: -1 was reg
break;
case 5: // (D16, An)
addr = EA_AY_DI_16();
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
case 6: // (An) + (Xn) + d8
addr = EA_AY_IX_16();
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
case 7: //
case 1: // (abs32)
{
addr = EA_AL_32();
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
}
case 2: // (d16, PC)
{
addr = EA_PCDI_16();
- m68040_do_fsave(addr, -1, 1);
+ m68040_do_fsave(state, addr, -1, 1);
break;
}
default:
{
case 2: // (An)
addr = REG_A[reg];
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
case 3: // (An)+
addr = EA_AY_PI_32();
- m68040_do_frestore(addr, reg);
+ m68040_do_frestore(state, addr, reg);
break;
case 5: // (D16, An)
addr = EA_AY_DI_16();
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
case 6: // (An) + (Xn) + d8
addr = EA_AY_IX_16();
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
case 7: //
case 1: // (abs32)
{
addr = EA_AL_32();
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
}
case 2: // (d16, PC)
{
addr = EA_PCDI_16();
- m68040_do_frestore(addr, -1);
+ m68040_do_frestore(state, addr, -1);
break;
}
default:
}
}
-void m68881_ftrap()
+void m68881_ftrap(m68ki_cpu_core *state)
{
- uint16 w2 = OPER_I_16();
+ uint16 w2 = OPER_I_16(state);
// now check the condition
if (TEST_CONDITION(w2 & 0x3f))
switch (REG_IR & 0x7)
{
case 2: // word operand
- OPER_I_16();
+ OPER_I_16(state);
break;
case 3: // long word operand
- OPER_I_32();
+ OPER_I_32(state);
break;
case 4: // no operand
add_replace_string(replace, ID_OPHANDLER_EA_AY_16, str);
sprintf(str, "EA_%s_32()", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_EA_AY_32, str);
- sprintf(str, "OPER_%s_8()", g_ea_info_table[ea_mode].ea_add);
+ sprintf(str, "OPER_%s_8(state)", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_OPER_AY_8, str);
- sprintf(str, "OPER_%s_16()", g_ea_info_table[ea_mode].ea_add);
+ sprintf(str, "OPER_%s_16(state)", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_OPER_AY_16, str);
- sprintf(str, "OPER_%s_32()", g_ea_info_table[ea_mode].ea_add);
+ sprintf(str, "OPER_%s_32(state)", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_OPER_AY_32, str);
}
// MMU status register bit definitions
+
+
+struct m68ki_cpu_core;
#if 0
#define MMULOG(A) printf A
#else
#define m_side_effects_disabled 0
/* decodes the effective address */
-uint32 DECODE_EA_32(int ea)
+uint32 DECODE_EA_32(m68ki_cpu_core *state, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
{
case 0: // (xxx).W
{
- uint32 ea = OPER_I_16();
+ uint32 ea = OPER_I_16(state);
return ea;
}
case 1: // (xxx).L
{
- uint32 d1 = OPER_I_16();
- uint32 d2 = OPER_I_16();
+ uint32 d1 = OPER_I_16(state);
+ uint32 d2 = OPER_I_16(state);
uint32 ea = (d1 << 16) | d2;
return ea;
}
return 0;
}
-void pmmu_set_buserror(uint32 addr_in)
+void pmmu_set_buserror(m68ki_cpu_core *state, uint32 addr_in)
{
if (!m_side_effects_disabled && ++m68ki_cpu.mmu_tmp_buserror_occurred == 1)
{
// pmmu_atc_add: adds this address to the ATC
-void pmmu_atc_add(uint32 logical, uint32 physical, int fc, int rw)
+void pmmu_atc_add(m68ki_cpu_core *state, uint32 logical, uint32 physical, int fc, int rw)
{
// get page size (i.e. # of bits to ignore); is 10 for Apollo
int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
// pmmu_atc_flush: flush entire ATC
// 7fff0003 001ffd10 80f05750 is what should load
-void pmmu_atc_flush()
+void pmmu_atc_flush(m68ki_cpu_core *state)
{
MMULOG(("ATC flush: pc=%08x\n", m68ki_cpu.ppc));
// std::fill(std::begin(m68ki_cpu.mmu_atc_tag), std::end(m68ki_cpu.mmu_atc_tag), 0);
int fc_from_modes(uint16 modes);
-void pmmu_atc_flush_fc_ea(uint16 modes)
+void pmmu_atc_flush_fc_ea(m68ki_cpu_core *state, uint16 modes)
{
unsigned int fcmask = (modes >> 5) & 7;
unsigned int fc = fc_from_modes(modes) & fcmask;
{
case 1: // PFLUSHA
MMULOG(("PFLUSHA: mode %d\n", mode));
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
break;
case 4: // flush by fc
case 6: // flush by fc + ea
- ea = DECODE_EA_32(m68ki_cpu.ir);
+ ea = DECODE_EA_32(state, m68ki_cpu.ir);
MMULOG(("flush by fc/ea: fc %d, mask %d, ea %08x\n", fc, fcmask, ea));
for(unsigned int i=0,e;i<MMU_ATC_ENTRIES;i++)
{
}
//template<bool ptest>
-uint16 pmmu_atc_lookup(uint32 addr_in, int fc, uint16 rw,
- uint32 *addr_out,int ptest)
+uint16 pmmu_atc_lookup(m68ki_cpu_core *state, uint32 addr_in, int fc, uint16 rw, uint32 *addr_out, int ptest)
{
MMULOG(("%s: LOOKUP addr_in=%08x, fc=%d, ptest=%d, rw=%d\n", __func__, addr_in, fc, ptest,rw));
unsigned int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
return 0;
}
-uint16 pmmu_match_tt(uint32 addr_in, int fc, uint32 tt, uint16 rw)
+uint16 pmmu_match_tt(m68ki_cpu_core *state, uint32 addr_in, int fc, uint32 tt, uint16 rw)
{
if (!(tt & M68K_MMU_TT_ENABLE))
{
return 1;
}
-void update_descriptor(uint32 tptr, int type, uint32 entry, int16 rw)
+void update_descriptor(m68ki_cpu_core *state, uint32 tptr, int type, uint32 entry, int16 rw)
{
if (type == M68K_MMU_DF_DT_PAGE && !rw &&
!(entry & M68K_MMU_DF_MODIFIED) &&
//template<bool _long>
-void update_sr(int type, uint32 tbl_entry, int fc,uint16 _long)
+void update_sr(m68ki_cpu_core *state, int type, uint32 tbl_entry, int fc, uint16 _long)
{
if (m_side_effects_disabled)
{
}
//template<bool ptest>
-uint16 pmmu_walk_tables(uint32 addr_in, int type, uint32 table, uint8 fc,
- int limit, uint16 rw, uint32 *addr_out, int ptest)
+uint16 pmmu_walk_tables(m68ki_cpu_core *state, uint32 addr_in, int type, uint32 table, uint8 fc, int limit, uint16 rw,
+ uint32 *addr_out, int ptest)
{
int level = 0;
uint32 bits = m68ki_cpu.mmu_tc & 0xffff;
table = tbl_entry & M68K_MMU_DF_ADDR_MASK;
if (!m_side_effects_disabled)
{
- update_sr(type, tbl_entry, fc,0);
+ update_sr(state, type, tbl_entry, fc, 0);
if (!ptest)
{
- update_descriptor(*addr_out, type, tbl_entry, rw);
+ update_descriptor(state, *addr_out, type, tbl_entry, rw);
}
}
break;
table = tbl_entry2 & M68K_MMU_DF_ADDR_MASK;
if (!m_side_effects_disabled)
{
- update_sr(type, tbl_entry, fc,1);
+ update_sr(state, type, tbl_entry, fc, 1);
if (!ptest)
{
- update_descriptor(*addr_out, type, tbl_entry, rw);
+ update_descriptor(state, *addr_out, type, tbl_entry, rw);
}
}
break;
// pmmu_translate_addr_with_fc: perform 68851/68030-style PMMU address translation
//template<bool ptest, bool pload>
-uint32 pmmu_translate_addr_with_fc(uint32 addr_in, uint8 fc, uint16 rw, int limit,int ptest,int pload)
+uint32 pmmu_translate_addr_with_fc(m68ki_cpu_core *state, uint32 addr_in, uint8 fc, uint16 rw, int limit, int ptest,
+ int pload)
{
uint32 addr_out = 0;
m68ki_cpu.mmu_last_logical_addr = addr_in;
- if (pmmu_match_tt(addr_in, fc, m68ki_cpu.mmu_tt0, rw) ||
- pmmu_match_tt(addr_in, fc, m68ki_cpu.mmu_tt1, rw) ||
+ if (pmmu_match_tt(state, addr_in, fc, m68ki_cpu.mmu_tt0, rw) ||
+ pmmu_match_tt(state, addr_in, fc, m68ki_cpu.mmu_tt1, rw) ||
fc == 7)
{
return addr_in;
if (ptest && limit == 0)
{
- pmmu_atc_lookup(addr_in, fc, rw, &addr_out, 1);
+ pmmu_atc_lookup(state, addr_in, fc, rw, &addr_out, 1);
return addr_out;
}
- if (!ptest && !pload && pmmu_atc_lookup(addr_in, fc, rw, &addr_out, 0))
+ if (!ptest && !pload && pmmu_atc_lookup(state, addr_in, fc, rw, &addr_out, 0))
{
if ((m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR) || (!rw && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)))
{
MMULOG(("set atc hit buserror: addr_in=%08x, addr_out=%x, rw=%x, fc=%d, sz=%d\n",
addr_in, addr_out, m68ki_cpu.mmu_tmp_rw, m68ki_cpu.mmu_tmp_fc, m68ki_cpu.mmu_tmp_sz));
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
return addr_out;
}
type = m68ki_cpu.mmu_crp_limit & M68K_MMU_DF_DT;
}
- if (!pmmu_walk_tables(addr_in, type, tbl_addr, fc, limit, rw, &addr_out, ptest))
+ if (!pmmu_walk_tables(state, addr_in, type, tbl_addr, fc, limit, rw, &addr_out, ptest))
{
MMULOG(("%s: addr_in=%08x, type=%x, tbl_addr=%x, fc=%d, limit=%x, rw=%x, addr_out=%x, ptest=%d\n",
__func__, addr_in, type, tbl_addr, fc, limit, rw, addr_out, ptest));
if (!pload)
{
MMULOG(("%s: set buserror (SR %04X)\n", __func__, m68ki_cpu.mmu_tmp_sr));
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
}
// between RW and the root type
if (!m_side_effects_disabled)
{
- pmmu_atc_add(addr_in, addr_out, fc, rw && type != 1);
+ pmmu_atc_add(state, addr_in, addr_out, fc, rw && type != 1);
}
MMULOG(("PMMU: [%08x] => [%08x] (SR %04x)\n", addr_in, addr_out, m68ki_cpu.mmu_tmp_sr));
return addr_out;
// FC bits: 2 = supervisor, 1 = program, 0 = data
// the 68040 is a subset of the 68851 and 68030 PMMUs - the page table sizes are fixed, there is no early termination, etc, etc.
-uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest)
+uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, uint8 fc, uint8 ptest)
{
uint32 addr_out, tt0, tt1;
MMULOG(("TT0 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt0, mask));
if ((tt0 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect?
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
return addr_in;
MMULOG(("TT1 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt1, mask));
if ((tt1 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect?
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
return addr_in;
// write protected by the root or pointer entries?
if ((((root_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((pointer_entry & 4) && !m68ki_cpu.mmu_tmp_rw)) && !ptest)
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
return addr_in;
}
if (!(pointer_entry & 2) && !ptest)
{
logerror("Invalid pointer entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in);
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
return addr_in;
}
if (!ptest)
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
return addr_in;
// is the page write protected or supervisor protected?
if ((((page_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((page_entry & 0x80) && !(fc & 4))) && !ptest)
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
return addr_in;
}
MMULOG(("Invalid page entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in));
if (!ptest)
{
- pmmu_set_buserror(addr_in);
+ pmmu_set_buserror(state, addr_in);
}
return addr_in;
}
// pmmu_translate_addr: perform 68851/68030-style PMMU address translation
-uint32 pmmu_translate_addr(uint32 addr_in, uint16 rw)
+uint32 pmmu_translate_addr(m68ki_cpu_core *state, uint32 addr_in, uint16 rw)
{
uint32 addr_out;
if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
{
- addr_out = pmmu_translate_addr_with_fc_040(addr_in, m68ki_cpu.mmu_tmp_fc, 0);
+ addr_out = pmmu_translate_addr_with_fc_040(state, addr_in, m68ki_cpu.mmu_tmp_fc, 0);
}
else
{
- addr_out = pmmu_translate_addr_with_fc(addr_in, m68ki_cpu.mmu_tmp_fc, rw,7,0,0);
+ addr_out = pmmu_translate_addr_with_fc(state, addr_in, m68ki_cpu.mmu_tmp_fc, rw, 7, 0, 0);
MMULOG(("ADDRIN %08X, ADDROUT %08X\n", addr_in, addr_out));
}
return addr_out;
return 0;
}
-void m68851_pload(uint32 ea, uint16 modes)
+void m68851_pload(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
- uint32 ltmp = DECODE_EA_32(ea);
+ uint32 ltmp = DECODE_EA_32(state, ea);
int fc = fc_from_modes(modes);
uint16 rw = !!(modes & 0x200);
{
if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
{
- pmmu_translate_addr_with_fc_040(ltmp, fc, 0);
+ pmmu_translate_addr_with_fc_040(state, ltmp, fc, 0);
}
else
{
- pmmu_translate_addr_with_fc(ltmp, fc, rw , 7, 0, 1);
+ pmmu_translate_addr_with_fc(state, ltmp, fc, rw, 7, 0, 1);
}
}
else
}
}
-void m68851_ptest(uint32 ea, uint16 modes)
+void m68851_ptest(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
- uint32 v_addr = DECODE_EA_32(ea);
+ uint32 v_addr = DECODE_EA_32(state, ea);
uint32 p_addr;
int level = (modes >> 10) & 7;
if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
{
- p_addr = pmmu_translate_addr_with_fc_040(v_addr, fc, 1);
+ p_addr = pmmu_translate_addr_with_fc_040(state, v_addr, fc, 1);
}
else
{
- p_addr = pmmu_translate_addr_with_fc(v_addr, fc, rw, level, 1, 0);
+ p_addr = pmmu_translate_addr_with_fc(state, v_addr, fc, rw, level, 1, 0);
}
m68ki_cpu.mmu_sr = m68ki_cpu.mmu_tmp_sr;
if (modes & 0x100)
{
int areg = (modes >> 5) & 7;
- WRITE_EA_32(0x08 | areg, p_addr);
+ WRITE_EA_32(state, 0x08 | areg, p_addr);
}
}
-void m68851_pmove_get(uint32 ea, uint16 modes)
+void m68851_pmove_get(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
switch ((modes>>10) & 0x3f)
{
case 0x02: // transparent translation register 0
- WRITE_EA_32(ea, m68ki_cpu.mmu_tt0);
+ WRITE_EA_32(state, ea, m68ki_cpu.mmu_tt0);
MMULOG(("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt0));
break;
case 0x03: // transparent translation register 1
- WRITE_EA_32(ea, m68ki_cpu.mmu_tt1);
+ WRITE_EA_32(state, ea, m68ki_cpu.mmu_tt1);
MMULOG(("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt1));
break;
case 0x10: // translation control register
- WRITE_EA_32(ea, m68ki_cpu.mmu_tc);
+ WRITE_EA_32(state, ea, m68ki_cpu.mmu_tc);
MMULOG(("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tc));
break;
case 0x12: // supervisor root pointer
- WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_srp_limit<<32 | (uint64)m68ki_cpu.mmu_srp_aptr);
+ WRITE_EA_64(state, ea, (uint64)m68ki_cpu.mmu_srp_limit<<32 | (uint64)m68ki_cpu.mmu_srp_aptr);
MMULOG(("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr));
break;
case 0x13: // CPU root pointer
- WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_crp_limit<<32 | (uint64)m68ki_cpu.mmu_crp_aptr);
+ WRITE_EA_64(state, ea, (uint64)m68ki_cpu.mmu_crp_limit<<32 | (uint64)m68ki_cpu.mmu_crp_aptr);
MMULOG(("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr));
break;
if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP, TT with FD bit clear
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
}
-void m68851_pmove_put(uint32 ea, uint16 modes)
+void m68851_pmove_put(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
uint64 temp64;
switch ((modes>>13) & 7)
{
case 0:
{
- uint32 temp = READ_EA_32(ea);
+ uint32 temp = READ_EA_32(state, ea);
if (((modes >> 10) & 7) == 2)
{
// FIXME: unreachable
if (!(modes & 0x100))
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
}
/* fall through */
switch ((modes >> 10) & 7)
{
case 0: // translation control register
- m68ki_cpu.mmu_tc = READ_EA_32(ea);
+ m68ki_cpu.mmu_tc = READ_EA_32(state, ea);
MMULOG(("PMMU: TC = %08x\n", m68ki_cpu.mmu_tc));
if (m68ki_cpu.mmu_tc & 0x80000000)
if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP with FD bit clear
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
break;
case 2: // supervisor root pointer
- temp64 = READ_EA_64(ea);
+ temp64 = READ_EA_64(state, ea);
m68ki_cpu.mmu_srp_limit = (temp64 >> 32) & 0xffffffff;
m68ki_cpu.mmu_srp_aptr = temp64 & 0xffffffff;
MMULOG(("PMMU: SRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr));
if (!(modes & 0x100))
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
break;
case 3: // CPU root pointer
- temp64 = READ_EA_64(ea);
+ temp64 = READ_EA_64(state, ea);
m68ki_cpu.mmu_crp_limit = (temp64 >> 32) & 0xffffffff;
m68ki_cpu.mmu_crp_aptr = temp64 & 0xffffffff;
MMULOG(("PMMU: CRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr));
if (!(modes & 0x100))
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
break;
if (m68ki_cpu.cpu_type == CPU_TYPE_020)
{
// DomainOS on Apollo DN3000 will only reset this to 0
- uint16 mmu_ac = READ_EA_16(ea);
+ uint16 mmu_ac = READ_EA_16(state, ea);
if (mmu_ac != 0)
{
MMULOG(("680x0 PMMU: pc=%x PMOVE to mmu_ac=%08x\n",
break;
case 3: // MMU status
{
- uint32 temp = READ_EA_32(ea);
+ uint32 temp = READ_EA_32(state, ea);
logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68ki_cpu.pc);
}
break;
}
-void m68851_pmove(uint32 ea, uint16 modes)
+void m68851_pmove(m68ki_cpu_core *state, uint32 ea, uint16 modes)
{
switch ((modes>>13) & 0x7)
{
case 2: // MC68851 form, FD never set
if (modes & 0x200)
{
- m68851_pmove_get(ea, modes);
+ m68851_pmove_get(state, ea, modes);
break;
}
else // top 3 bits of modes: 010 for this, 011 for status, 000 for transparent translation regs
{
- m68851_pmove_put(ea, modes);
+ m68851_pmove_put(state, ea, modes);
break;
}
case 3: // MC68030 to/from status reg
if (modes & 0x200)
{
MMULOG(("%s: read SR = %04x\n", __func__, m68ki_cpu.mmu_sr));
- WRITE_EA_16(ea, m68ki_cpu.mmu_sr);
+ WRITE_EA_16(state, ea, m68ki_cpu.mmu_sr);
}
else
{
- m68ki_cpu.mmu_sr = READ_EA_16(ea);
+ m68ki_cpu.mmu_sr = READ_EA_16(state, ea);
MMULOG(("%s: write SR = %04X\n", __func__, m68ki_cpu.mmu_sr));
}
break;
}
-void m68851_mmu_ops()
+void m68851_mmu_ops(m68ki_cpu_core *state)
{
uint16 modes;
uint32 ea = m68ki_cpu.ir & 0x3f;
else if ((m68ki_cpu.ir & 0xffe0) == 0xf500)
{
MMULOG(("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", REG_PC-4, m68ki_cpu.ir, (m68ki_cpu.ir >> 3) & 3, m68ki_cpu.ir & 7));
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
}
else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
{
switch ((m68ki_cpu.ir>>9) & 0x7)
{
case 0:
- modes = OPER_I_16();
+ modes = OPER_I_16(state);
if ((modes & 0xfde0) == 0x2000) // PLOAD
{
- m68851_pload(ea, modes);
+ m68851_pload(state, ea, modes);
return;
}
else if ((modes & 0xe200) == 0x2000) // PFLUSH
{
- pmmu_atc_flush_fc_ea(modes);
+ pmmu_atc_flush_fc_ea(state, modes);
return;
}
else if (modes == 0xa000) // PFLUSHR
{
- pmmu_atc_flush();
+ pmmu_atc_flush(state);
return;
}
else if (modes == 0x2800) // PVALID (FORMAT 1)
}
else if ((modes & 0xe000) == 0x8000) // PTEST
{
- m68851_ptest(ea, modes);
+ m68851_ptest(state, ea, modes);
return;
}
else
{
- m68851_pmove(ea, modes);
+ m68851_pmove(state, ea, modes);
}
break;
projects / pistorm / commitdiff