void pmmu_set_buserror(m68ki_cpu_core *state, uint32 addr_in)
{
- if (!m_side_effects_disabled && ++m68ki_cpu.mmu_tmp_buserror_occurred == 1)
+ if (!m_side_effects_disabled && ++state->mmu_tmp_buserror_occurred == 1)
{
- m68ki_cpu.mmu_tmp_buserror_address = addr_in;
- m68ki_cpu.mmu_tmp_buserror_rw = m68ki_cpu.mmu_tmp_rw;
- m68ki_cpu.mmu_tmp_buserror_fc = m68ki_cpu.mmu_tmp_fc;
- m68ki_cpu.mmu_tmp_buserror_sz = m68ki_cpu.mmu_tmp_sz;
+ state->mmu_tmp_buserror_address = addr_in;
+ state->mmu_tmp_buserror_rw = state->mmu_tmp_rw;
+ state->mmu_tmp_buserror_fc = state->mmu_tmp_fc;
+ state->mmu_tmp_buserror_sz = state->mmu_tmp_sz;
}
}
void pmmu_atc_add(m68ki_cpu_core *state, uint32 logical, uint32 physical, int fc, int rw)
{
// get page size (i.e. # of bits to ignore); is 10 for Apollo
- int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
+ int ps = (state->mmu_tc >> 20) & 0xf;
uint32 atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | ((logical >> ps) << (ps - 8));
uint32 atc_data = (physical >> ps) << (ps - 8);
- if (m68ki_cpu.mmu_tmp_sr & (M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY))
+ if (state->mmu_tmp_sr & (M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY))
{
atc_data |= M68K_MMU_ATC_BUSERROR;
}
- if (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)
+ if (state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)
{
atc_data |= M68K_MMU_ATC_WRITE_PR;
}
- if (!rw && !(m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
+ if (!rw && !(state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
{
atc_data |= M68K_MMU_ATC_MODIFIED;
}
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
// if tag bits and function code match, don't add
- if (m68ki_cpu.mmu_atc_tag[i] == atc_tag)
+ if (state->mmu_atc_tag[i] == atc_tag)
{
- MMULOG(("%s: hit, old %08x new %08x\n", __func__, m68ki_cpu.mmu_atc_data[i], atc_data));
- m68ki_cpu.mmu_atc_data[i] = atc_data;
+ MMULOG(("%s: hit, old %08x new %08x\n", __func__, state->mmu_atc_data[i], atc_data));
+ state->mmu_atc_data[i] = atc_data;
return;
}
}
int found = -1;
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
- if (!(m68ki_cpu.mmu_atc_tag[i] & M68K_MMU_ATC_VALID))
+ if (!(state->mmu_atc_tag[i] & M68K_MMU_ATC_VALID))
{
found = i;
break;
// did we find an entry? steal one by round-robin then
if (found == -1)
{
- found = m68ki_cpu.mmu_atc_rr++;
+ found = state->mmu_atc_rr++;
- if (m68ki_cpu.mmu_atc_rr >= MMU_ATC_ENTRIES)
+ if (state->mmu_atc_rr >= MMU_ATC_ENTRIES)
{
- m68ki_cpu.mmu_atc_rr = 0;
+ state->mmu_atc_rr = 0;
}
}
// add the entry
MMULOG(("ATC[%2d] add: log %08x -> phys %08x (fc=%d) data=%08x\n",
found, (logical >> ps) << ps, (physical >> ps) << ps, fc, atc_data));
- m68ki_cpu.mmu_atc_tag[found] = atc_tag;
- m68ki_cpu.mmu_atc_data[found] = atc_data;
+ state->mmu_atc_tag[found] = atc_tag;
+ state->mmu_atc_data[found] = atc_data;
}
// pmmu_atc_flush: flush entire ATC
// 7fff0003 001ffd10 80f05750 is what should load
void pmmu_atc_flush(m68ki_cpu_core *state)
{
- MMULOG(("ATC flush: pc=%08x\n", m68ki_cpu.ppc));
-// std::fill(std::begin(m68ki_cpu.mmu_atc_tag), std::end(m68ki_cpu.mmu_atc_tag), 0);
+ MMULOG(("ATC flush: pc=%08x\n", state->ppc));
+// std::fill(std::begin(state->mmu_atc_tag), std::end(state->mmu_atc_tag), 0);
for(int i=0;i<MMU_ATC_ENTRIES;i++)
- m68ki_cpu.mmu_atc_tag[i]=0;
- m68ki_cpu.mmu_atc_rr = 0;
+ state->mmu_atc_tag[i]=0;
+ state->mmu_atc_rr = 0;
}
int fc_from_modes(m68ki_cpu_core *state, uint16 modes);
{
unsigned int fcmask = (modes >> 5) & 7;
unsigned int fc = fc_from_modes(state, modes) & fcmask;
- unsigned int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
+ unsigned int ps = (state->mmu_tc >> 20) & 0xf;
unsigned int mode = (modes >> 10) & 7;
uint32 ea;
MMULOG(("flush by fc: %d, mask %d\n", fc, fcmask));
for(int i=0,e;i<MMU_ATC_ENTRIES;i++)
{
- e=m68ki_cpu.mmu_atc_tag[i];
+ e=state->mmu_atc_tag[i];
if ((e & M68K_MMU_ATC_VALID) && ((e >> 24) & fcmask) == fc)
{
MMULOG(("flushing entry %08x\n", e));
- m68ki_cpu.mmu_atc_tag[i] = 0;
+ state->mmu_atc_tag[i] = 0;
}
}
break;
case 6: // flush by fc + ea
- ea = DECODE_EA_32(state, m68ki_cpu.ir);
+ ea = DECODE_EA_32(state, state->ir);
MMULOG(("flush by fc/ea: fc %d, mask %d, ea %08x\n", fc, fcmask, ea));
for(unsigned int i=0,e;i<MMU_ATC_ENTRIES;i++)
{
- e=m68ki_cpu.mmu_atc_tag[i];
+ e=state->mmu_atc_tag[i];
if ((e & M68K_MMU_ATC_VALID) &&
(((e >> 24) & fcmask) == fc) &&
// (((e >> ps) << (ps - 8)) == ((ea >> ps) << (ps - 8))))
( (e << ps) == (ea >> 8 << ps) ))
{
MMULOG(("flushing entry %08x\n", e));
- m68ki_cpu.mmu_atc_tag[i] = 0;
+ state->mmu_atc_tag[i] = 0;
}
}
break;
uint16 pmmu_atc_lookup(m68ki_cpu_core *state, uint32 addr_in, int fc, uint16 rw, uint32 *addr_out, int ptest)
{
MMULOG(("%s: LOOKUP addr_in=%08x, fc=%d, ptest=%d, rw=%d\n", __func__, addr_in, fc, ptest,rw));
- unsigned int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
+ unsigned int ps = (state->mmu_tc >> 20) & 0xf;
uint32 atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | ((addr_in >> ps) << (ps - 8));
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
- if (m68ki_cpu.mmu_atc_tag[i] != atc_tag)
+ if (state->mmu_atc_tag[i] != atc_tag)
{
continue;
}
- uint32 atc_data = m68ki_cpu.mmu_atc_data[i];
+ uint32 atc_data = state->mmu_atc_data[i];
if (!ptest && !rw)
{
// entry, and creating a new entry with the M bit set.
if (!(atc_data & M68K_MMU_ATC_MODIFIED))
{
- m68ki_cpu.mmu_atc_tag[i] = 0;
+ state->mmu_atc_tag[i] = 0;
continue;
}
}
- m68ki_cpu.mmu_tmp_sr = 0;
+ state->mmu_tmp_sr = 0;
if (atc_data & M68K_MMU_ATC_MODIFIED)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
+ state->mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
}
if (atc_data & M68K_MMU_ATC_WRITE_PR)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
+ state->mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
}
if (atc_data & M68K_MMU_ATC_BUSERROR)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
+ state->mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
}
*addr_out = (atc_data << 8) | (addr_in & ~(((uint32)~0) << ps));
MMULOG(("%s: addr_in=%08x, addr_out=%08x, MMU SR %04x\n",
- __func__, addr_in, *addr_out, m68ki_cpu.mmu_tmp_sr));
+ __func__, addr_in, *addr_out, state->mmu_tmp_sr));
return 1;
}
MMULOG(("%s: lookup failed\n", __func__));
if (ptest)
{
- m68ki_cpu.mmu_tmp_sr = M68K_MMU_SR_INVALID;
+ state->mmu_tmp_sr = M68K_MMU_SR_INVALID;
}
return 0;
}
return 0;
}
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_TRANSPARENT;
+ state->mmu_tmp_sr |= M68K_MMU_SR_TRANSPARENT;
return 1;
}
case M68K_MMU_DF_DT_PAGE:
if (tbl_entry & M68K_MMU_DF_MODIFIED)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
+ state->mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
}
/* FALLTHROUGH */
if (tbl_entry & M68K_MMU_DF_WP)
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
+ state->mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
}
if (_long && !(fc & 4) && (tbl_entry & M68K_MMU_DF_SUPERVISOR))
{
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_SUPERVISOR_ONLY;
+ state->mmu_tmp_sr |= M68K_MMU_SR_SUPERVISOR_ONLY;
}
break;
default:
uint32 *addr_out, int ptest)
{
int level = 0;
- uint32 bits = m68ki_cpu.mmu_tc & 0xffff;
- int pagesize = (m68ki_cpu.mmu_tc >> 20) & 0xf;
- int is = (m68ki_cpu.mmu_tc >> 16) & 0xf;
+ uint32 bits = state->mmu_tc & 0xffff;
+ int pagesize = (state->mmu_tc >> 20) & 0xf;
+ int is = (state->mmu_tc >> 16) & 0xf;
int bitpos = 12;
int resolved = 0;
int pageshift = is;
addr_in <<= is;
- m68ki_cpu.mmu_tablewalk = 1;
+ state->mmu_tablewalk = 1;
- if (m68ki_cpu.mmu_tc & M68K_MMU_TC_FCL)
+ if (state->mmu_tc & M68K_MMU_TC_FCL)
{
bitpos = 16;
}
switch(type)
{
case M68K_MMU_DF_DT_INVALID: // invalid, will cause MMU exception
- m68ki_cpu.mmu_tmp_sr = M68K_MMU_SR_INVALID;
- MMULOG(("PMMU: DT0 PC=%x (addr_in %08x -> %08x)\n", m68ki_cpu.ppc, addr_in, *addr_out));
+ state->mmu_tmp_sr = M68K_MMU_SR_INVALID;
+ MMULOG(("PMMU: DT0 PC=%x (addr_in %08x -> %08x)\n", state->ppc, addr_in, *addr_out));
resolved = 1;
break;
break;
}
- if (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR)
+ if (state->mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR)
{
// Bus error during page table walking is always fatal
resolved = 1;
if (!ptest && !m_side_effects_disabled)
{
- if (!rw && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
+ if (!rw && (state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
{
resolved = 1;
break;
}
- if (!(fc & 4) && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY))
+ if (!(fc & 4) && (state->mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY))
{
resolved = 1;
break;
} while(level < limit && !resolved);
- m68ki_cpu.mmu_tmp_sr &= 0xfff0;
- m68ki_cpu.mmu_tmp_sr |= level;
- MMULOG(("MMU SR after walk: %04X\n", m68ki_cpu.mmu_tmp_sr));
- m68ki_cpu.mmu_tablewalk = 0;
+ state->mmu_tmp_sr &= 0xfff0;
+ state->mmu_tmp_sr |= level;
+ MMULOG(("MMU SR after walk: %04X\n", state->mmu_tmp_sr));
+ state->mmu_tablewalk = 0;
return resolved;
}
MMULOG(("%s: addr_in=%08x, fc=%d, ptest=%d, rw=%d, limit=%d, pload=%d\n",
__func__, addr_in, fc, ptest, rw, limit, pload));
- m68ki_cpu.mmu_tmp_sr = 0;
+ state->mmu_tmp_sr = 0;
- m68ki_cpu.mmu_last_logical_addr = addr_in;
+ state->mmu_last_logical_addr = addr_in;
- if (pmmu_match_tt(state, addr_in, fc, m68ki_cpu.mmu_tt0, rw) ||
- pmmu_match_tt(state, addr_in, fc, m68ki_cpu.mmu_tt1, rw) ||
+ if (pmmu_match_tt(state, addr_in, fc, state->mmu_tt0, rw) ||
+ pmmu_match_tt(state, addr_in, fc, state->mmu_tt1, rw) ||
fc == 7)
{
return addr_in;
if (!ptest && !pload && pmmu_atc_lookup(state, addr_in, fc, rw, &addr_out, 0))
{
- if ((m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR) || (!rw && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)))
+ if ((state->mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR) || (!rw && (state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)))
{
MMULOG(("set atc hit buserror: addr_in=%08x, addr_out=%x, rw=%x, fc=%d, sz=%d\n",
- addr_in, addr_out, m68ki_cpu.mmu_tmp_rw, m68ki_cpu.mmu_tmp_fc, m68ki_cpu.mmu_tmp_sz));
+ addr_in, addr_out, state->mmu_tmp_rw, state->mmu_tmp_fc, state->mmu_tmp_sz));
pmmu_set_buserror(state, addr_in);
}
return addr_out;
int type;
uint32 tbl_addr;
// if SRP is enabled and we're in supervisor mode, use it
- if ((m68ki_cpu.mmu_tc & M68K_MMU_TC_SRE) && (fc & 4))
+ if ((state->mmu_tc & M68K_MMU_TC_SRE) && (fc & 4))
{
- tbl_addr = m68ki_cpu.mmu_srp_aptr & M68K_MMU_DF_ADDR_MASK;
- type = m68ki_cpu.mmu_srp_limit & M68K_MMU_DF_DT;
+ tbl_addr = state->mmu_srp_aptr & M68K_MMU_DF_ADDR_MASK;
+ type = state->mmu_srp_limit & M68K_MMU_DF_DT;
}
else // else use the CRP
{
- tbl_addr = m68ki_cpu.mmu_crp_aptr & M68K_MMU_DF_ADDR_MASK;
- type = m68ki_cpu.mmu_crp_limit & M68K_MMU_DF_DT;
+ tbl_addr = state->mmu_crp_aptr & M68K_MMU_DF_ADDR_MASK;
+ type = state->mmu_crp_limit & M68K_MMU_DF_DT;
}
if (!pmmu_walk_tables(state, addr_in, type, tbl_addr, fc, limit, rw, &addr_out, ptest))
return addr_out;
}
- if ((m68ki_cpu.mmu_tmp_sr & (M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY)) ||
- ((m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT) && !rw))
+ if ((state->mmu_tmp_sr & (M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY)) ||
+ ((state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT) && !rw))
{
if (!pload)
{
- MMULOG(("%s: set buserror (SR %04X)\n", __func__, m68ki_cpu.mmu_tmp_sr));
+ MMULOG(("%s: set buserror (SR %04X)\n", __func__, state->mmu_tmp_sr));
pmmu_set_buserror(state, addr_in);
}
}
{
pmmu_atc_add(state, addr_in, addr_out, fc, rw && type != 1);
}
- MMULOG(("PMMU: [%08x] => [%08x] (SR %04x)\n", addr_in, addr_out, m68ki_cpu.mmu_tmp_sr));
+ MMULOG(("PMMU: [%08x] => [%08x] (SR %04x)\n", addr_in, addr_out, state->mmu_tmp_sr));
return addr_out;
}
uint32 addr_out, tt0, tt1;
addr_out = addr_in;
- m68ki_cpu.mmu_tmp_sr = 0;
+ state->mmu_tmp_sr = 0;
// transparent translation registers are always in force even if the PMMU itself is disabled
// they don't do much in emulation because we never write out of order, but the write-protect and cache control features
// are emulatable, and apparently transparent translation regions skip the page table lookup.
if (fc & 1) // data, use DTT0/DTT1
{
- tt0 = m68ki_cpu.mmu_dtt0;
- tt1 = m68ki_cpu.mmu_dtt1;
+ tt0 = state->mmu_dtt0;
+ tt1 = state->mmu_dtt1;
}
else if (fc & 2) // program, use ITT0/ITT1
{
- tt0 = m68ki_cpu.mmu_itt0;
- tt1 = m68ki_cpu.mmu_itt1;
+ tt0 = state->mmu_itt0;
+ tt1 = state->mmu_itt1;
}
else
{
if ((addr_in & mask) == (tt0 & mask) && (fc & fcmask[(tt0 >> 13) & 3]) == fcmatch[(tt0 >> 13) & 3])
{
MMULOG(("TT0 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt0, mask));
- if ((tt0 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect?
+ if ((tt0 & 4) && !state->mmu_tmp_rw && !ptest) // write protect?
{
pmmu_set_buserror(state, addr_in);
}
if ((addr_in & mask) == (tt1 & mask) && (fc & fcmask[(tt1 >> 13) & 3]) == fcmatch[(tt1 >> 13) & 3])
{
MMULOG(("TT1 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt1, mask));
- if ((tt1 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect?
+ if ((tt1 & 4) && !state->mmu_tmp_rw && !ptest) // write protect?
{
pmmu_set_buserror(state, addr_in);
}
}
}
- if (m68ki_cpu.pmmu_enabled)
+ if (state->pmmu_enabled)
{
uint32 root_idx = (addr_in >> 25) & 0x7f;
uint32 ptr_idx = (addr_in >> 18) & 0x7f;
// select supervisor or user root pointer
if (fc & 4)
{
- root_ptr = m68ki_cpu.mmu_srp_aptr + (root_idx<<2);
+ root_ptr = state->mmu_srp_aptr + (root_idx<<2);
}
else
{
- root_ptr = m68ki_cpu.mmu_urp_aptr + (root_idx<<2);
+ root_ptr = state->mmu_urp_aptr + (root_idx<<2);
}
// get the root entry
// PTEST: any write protect bits set in the search tree will set W in SR
if ((ptest) && (root_entry & 4))
{
- m68ki_cpu.mmu_tmp_sr |= 4;
+ state->mmu_tmp_sr |= 4;
}
pointer_ptr = (root_entry & ~0x1ff) + (ptr_idx<<2);
// PTEST: any write protect bits set in the search tree will set W in SR
if ((ptest) && (pointer_entry & 4))
{
- m68ki_cpu.mmu_tmp_sr |= 4;
+ state->mmu_tmp_sr |= 4;
}
// update U bit on this pointer entry too
MMULOG(("pointer entry = %08x\n", pointer_entry));
// write protected by the root or pointer entries?
- if ((((root_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((pointer_entry & 4) && !m68ki_cpu.mmu_tmp_rw)) && !ptest)
+ if ((((root_entry & 4) && !state->mmu_tmp_rw) || ((pointer_entry & 4) && !state->mmu_tmp_rw)) && !ptest)
{
pmmu_set_buserror(state, addr_in);
return addr_in;
// is UDT valid on the pointer entry?
if (!(pointer_entry & 2) && !ptest)
{
- logerror("Invalid pointer entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in);
+ logerror("Invalid pointer entry! PC=%x, addr=%x\n", state->ppc, addr_in);
pmmu_set_buserror(state, addr_in);
return addr_in;
}
}
else // throw an error
{
- logerror("Invalid root entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in);
+ logerror("Invalid root entry! PC=%x, addr=%x\n", state->ppc, addr_in);
if (!ptest)
{
}
// now do the page lookup
- if (m68ki_cpu.mmu_tc & 0x4000) // 8k pages?
+ if (state->mmu_tc & 0x4000) // 8k pages?
{
page_idx = (addr_in >> 13) & 0x1f;
page = addr_in & 0x1fff;
page_ptr = pointer_entry + (page_idx<<2);
page_entry = m68k_read_memory_32(page_ptr);
- m68ki_cpu.mmu_last_page_entry_addr = page_ptr;
+ state->mmu_last_page_entry_addr = page_ptr;
MMULOG(("page_entry = %08x\n", page_entry));
while ((page_entry & 3) == 2)
{
page_entry = m68k_read_memory_32(page_entry & ~0x3);
- m68ki_cpu.mmu_last_page_entry_addr = (page_entry & ~0x3);
+ state->mmu_last_page_entry_addr = (page_entry & ~0x3);
}
- m68ki_cpu.mmu_last_page_entry = page_entry;
+ state->mmu_last_page_entry = page_entry;
// is the page write protected or supervisor protected?
- if ((((page_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((page_entry & 0x80) && !(fc & 4))) && !ptest)
+ if ((((page_entry & 4) && !state->mmu_tmp_rw) || ((page_entry & 0x80) && !(fc & 4))) && !ptest)
{
pmmu_set_buserror(state, addr_in);
return addr_in;
switch (page_entry & 3)
{
case 0: // invalid
- MMULOG(("Invalid page entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in));
+ MMULOG(("Invalid page entry! PC=%x, addr=%x\n", state->ppc, addr_in));
if (!ptest)
{
pmmu_set_buserror(state, addr_in);
case 1:
case 3: // normal
- if (m68ki_cpu.mmu_tc & 0x4000) // 8k pages?
+ if (state->mmu_tc & 0x4000) // 8k pages?
{
addr_out = (page_entry & ~0x1fff) | page;
}
page_entry |= 0x8; // always set the U bit
// if we're writing, the M bit comes into play
- if (!m68ki_cpu.mmu_tmp_rw)
+ if (!state->mmu_tmp_rw)
{
page_entry |= 0x10; // set Modified
}
// if these updates resulted in a change, write the entry back where we found it
- if (page_entry != m68ki_cpu.mmu_last_page_entry && !m_side_effects_disabled)
+ if (page_entry != state->mmu_last_page_entry && !m_side_effects_disabled)
{
- m68ki_cpu.mmu_last_page_entry = page_entry;
- m68k_write_memory_32(m68ki_cpu.mmu_last_page_entry_addr, m68ki_cpu.mmu_last_page_entry);
+ state->mmu_last_page_entry = page_entry;
+ m68k_write_memory_32(state->mmu_last_page_entry_addr, state->mmu_last_page_entry);
}
}
else
{
// page entry: UR G U1 U0 S CM CM M U W PDT
// SR: B G U1 U0 S CM CM M 0 W T R
- m68ki_cpu.mmu_tmp_sr |= ((addr_out & ~0xfff) || (page_entry & 0x7f4));
+ state->mmu_tmp_sr |= ((addr_out & ~0xfff) || (page_entry & 0x7f4));
}
break;
{
uint32 addr_out;
- if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
+ if (CPU_TYPE_IS_040_PLUS(state->cpu_type))
{
- addr_out = pmmu_translate_addr_with_fc_040(state, addr_in, m68ki_cpu.mmu_tmp_fc, 0);
+ addr_out = pmmu_translate_addr_with_fc_040(state, addr_in, state->mmu_tmp_fc, 0);
}
else
{
- addr_out = pmmu_translate_addr_with_fc(state, addr_in, m68ki_cpu.mmu_tmp_fc, rw, 7, 0, 0);
+ addr_out = pmmu_translate_addr_with_fc(state, addr_in, state->mmu_tmp_fc, rw, 7, 0, 0);
MMULOG(("ADDRIN %08X, ADDROUT %08X\n", addr_in, addr_out));
}
return addr_out;
{
if ((modes & 0x1f) == 0)
{
- return m68ki_cpu.sfc;
+ return state->sfc;
}
if ((modes & 0x1f) == 1)
{
- return m68ki_cpu.dfc;
+ return state->dfc;
}
- if (m68ki_cpu.cpu_type & CPU_TYPE_030)
+ if (state->cpu_type & CPU_TYPE_030)
{
// 68030 has 3 bits fc, but 68851 4 bits
if (((modes >> 3) & 3) == 1)
MMULOG(("%s: PLOAD%c addr=%08x, fc=%d\n", __func__, rw ? 'R' : 'W', ltmp, fc));
// MC68851 traps if MMU is not enabled, 030 not
- if (m68ki_cpu.pmmu_enabled || (m68ki_cpu.cpu_type & CPU_TYPE_030))
+ if (state->pmmu_enabled || (state->cpu_type & CPU_TYPE_030))
{
- if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
+ if (CPU_TYPE_IS_040_PLUS(state->cpu_type))
{
pmmu_translate_addr_with_fc_040(state, ltmp, fc, 0);
}
int fc = fc_from_modes(state, modes);
MMULOG(("PMMU: PTEST%c (%04X) pc=%08x sp=%08x va=%08x fc=%x level=%x a=%d, areg=%d\n",
- rw ? 'R' : 'W', modes, m68ki_cpu.ppc, REG_A[7], v_addr, fc, level,
+ rw ? 'R' : 'W', modes, state->ppc, REG_A[7], v_addr, fc, level,
(modes & 0x100) ? 1 : 0, (modes >> 5) & 7));
- if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
+ if (CPU_TYPE_IS_040_PLUS(state->cpu_type))
{
p_addr = pmmu_translate_addr_with_fc_040(state, v_addr, fc, 1);
}
p_addr = pmmu_translate_addr_with_fc(state, v_addr, fc, rw, level, 1, 0);
}
- m68ki_cpu.mmu_sr = m68ki_cpu.mmu_tmp_sr;
+ state->mmu_sr = state->mmu_tmp_sr;
- MMULOG(("PMMU: PTEST result: %04x pa=%08x\n", m68ki_cpu.mmu_sr, p_addr));
+ MMULOG(("PMMU: PTEST result: %04x pa=%08x\n", state->mmu_sr, p_addr));
if (modes & 0x100)
{
int areg = (modes >> 5) & 7;
switch ((modes>>10) & 0x3f)
{
case 0x02: // transparent translation register 0
- WRITE_EA_32(state, ea, m68ki_cpu.mmu_tt0);
- MMULOG(("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt0));
+ WRITE_EA_32(state, ea, state->mmu_tt0);
+ MMULOG(("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", state->ppc, state->mmu_tt0));
break;
case 0x03: // transparent translation register 1
- WRITE_EA_32(state, ea, m68ki_cpu.mmu_tt1);
- MMULOG(("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt1));
+ WRITE_EA_32(state, ea, state->mmu_tt1);
+ MMULOG(("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", state->ppc, state->mmu_tt1));
break;
case 0x10: // translation control register
- WRITE_EA_32(state, ea, m68ki_cpu.mmu_tc);
- MMULOG(("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tc));
+ WRITE_EA_32(state, ea, state->mmu_tc);
+ MMULOG(("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", state->ppc, state->mmu_tc));
break;
case 0x12: // supervisor root pointer
- WRITE_EA_64(state, ea, (uint64)m68ki_cpu.mmu_srp_limit<<32 | (uint64)m68ki_cpu.mmu_srp_aptr);
- MMULOG(("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr));
+ WRITE_EA_64(state, ea, (uint64)state->mmu_srp_limit<<32 | (uint64)state->mmu_srp_aptr);
+ MMULOG(("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", state->ppc, state->mmu_srp_limit, state->mmu_srp_aptr));
break;
case 0x13: // CPU root pointer
- WRITE_EA_64(state, ea, (uint64)m68ki_cpu.mmu_crp_limit<<32 | (uint64)m68ki_cpu.mmu_crp_aptr);
- MMULOG(("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr));
+ WRITE_EA_64(state, ea, (uint64)state->mmu_crp_limit<<32 | (uint64)state->mmu_crp_aptr);
+ MMULOG(("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", state->ppc, state->mmu_crp_limit, state->mmu_crp_aptr));
break;
default:
- logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68ki_cpu.pc);
+ logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, state->pc);
return;
}
if (((modes >> 10) & 7) == 2)
{
- MMULOG(("WRITE TT0 = 0x%08x\n", m68ki_cpu.mmu_tt0));
- m68ki_cpu.mmu_tt0 = temp;
+ MMULOG(("WRITE TT0 = 0x%08x\n", state->mmu_tt0));
+ state->mmu_tt0 = temp;
}
else if (((modes >> 10) & 7) == 3)
{
- MMULOG(("WRITE TT1 = 0x%08x\n", m68ki_cpu.mmu_tt1));
- m68ki_cpu.mmu_tt1 = temp;
+ MMULOG(("WRITE TT1 = 0x%08x\n", state->mmu_tt1));
+ state->mmu_tt1 = temp;
}
break;
/* no break */
case 1:
- logerror("680x0: unknown PMOVE case 1, PC %x\n", m68ki_cpu.pc);
+ logerror("680x0: unknown PMOVE case 1, PC %x\n", state->pc);
break;
case 2:
switch ((modes >> 10) & 7)
{
case 0: // translation control register
- m68ki_cpu.mmu_tc = READ_EA_32(state, ea);
- MMULOG(("PMMU: TC = %08x\n", m68ki_cpu.mmu_tc));
+ state->mmu_tc = READ_EA_32(state, ea);
+ MMULOG(("PMMU: TC = %08x\n", state->mmu_tc));
- if (m68ki_cpu.mmu_tc & 0x80000000)
+ if (state->mmu_tc & 0x80000000)
{
int bits = 0;
for (int shift = 20; shift >= 0; shift -= 4)
{
- bits += (m68ki_cpu.mmu_tc >> shift) & 0x0f;
+ bits += (state->mmu_tc >> shift) & 0x0f;
}
- if (bits != 32 || !((m68ki_cpu.mmu_tc >> 23) & 1))
+ if (bits != 32 || !((state->mmu_tc >> 23) & 1))
{
logerror("MMU: TC invalid!\n");
- m68ki_cpu.mmu_tc &= ~0x80000000;
+ state->mmu_tc &= ~0x80000000;
m68ki_exception_trap(state, EXCEPTION_MMU_CONFIGURATION);
} else {
- m68ki_cpu.pmmu_enabled = 1;
+ state->pmmu_enabled = 1;
}
MMULOG(("PMMU enabled\n"));
}
else
{
- m68ki_cpu.pmmu_enabled = 0;
+ state->pmmu_enabled = 0;
MMULOG(("PMMU disabled\n"));
}
case 2: // supervisor root pointer
temp64 = READ_EA_64(state, ea);
- m68ki_cpu.mmu_srp_limit = (temp64 >> 32) & 0xffffffff;
- m68ki_cpu.mmu_srp_aptr = temp64 & 0xffffffff;
- MMULOG(("PMMU: SRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr));
+ state->mmu_srp_limit = (temp64 >> 32) & 0xffffffff;
+ state->mmu_srp_aptr = temp64 & 0xffffffff;
+ MMULOG(("PMMU: SRP limit = %08x aptr = %08x\n", state->mmu_srp_limit, state->mmu_srp_aptr));
// SRP type 0 is not allowed
- if ((m68ki_cpu.mmu_srp_limit & 3) == 0)
+ if ((state->mmu_srp_limit & 3) == 0)
{
m68ki_exception_trap(state, EXCEPTION_MMU_CONFIGURATION);
return;
case 3: // CPU root pointer
temp64 = READ_EA_64(state, ea);
- m68ki_cpu.mmu_crp_limit = (temp64 >> 32) & 0xffffffff;
- m68ki_cpu.mmu_crp_aptr = temp64 & 0xffffffff;
- MMULOG(("PMMU: CRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr));
+ state->mmu_crp_limit = (temp64 >> 32) & 0xffffffff;
+ state->mmu_crp_aptr = temp64 & 0xffffffff;
+ MMULOG(("PMMU: CRP limit = %08x aptr = %08x\n", state->mmu_crp_limit, state->mmu_crp_aptr));
// CRP type 0 is not allowed
- if ((m68ki_cpu.mmu_crp_limit & 3) == 0)
+ if ((state->mmu_crp_limit & 3) == 0)
{
m68ki_exception_trap(state, EXCEPTION_MMU_CONFIGURATION);
return;
break;
case 7: // MC68851 Access Control Register
- if (m68ki_cpu.cpu_type == CPU_TYPE_020)
+ if (state->cpu_type == CPU_TYPE_020)
{
// DomainOS on Apollo DN3000 will only reset this to 0
uint16 mmu_ac = READ_EA_16(state, ea);
if (mmu_ac != 0)
{
MMULOG(("680x0 PMMU: pc=%x PMOVE to mmu_ac=%08x\n",
- m68ki_cpu.ppc, mmu_ac));
+ state->ppc, mmu_ac));
}
break;
}
/* fall through */
/* no break */
default:
- logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68ki_cpu.pc);
+ logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, state->pc);
break;
}
break;
case 3: // MMU status
{
uint32 temp = READ_EA_32(state, ea);
- logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68ki_cpu.pc);
+ logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, state->pc);
}
break;
}
case 3: // MC68030 to/from status reg
if (modes & 0x200)
{
- MMULOG(("%s: read SR = %04x\n", __func__, m68ki_cpu.mmu_sr));
- WRITE_EA_16(state, ea, m68ki_cpu.mmu_sr);
+ MMULOG(("%s: read SR = %04x\n", __func__, state->mmu_sr));
+ WRITE_EA_16(state, ea, state->mmu_sr);
}
else
{
- m68ki_cpu.mmu_sr = READ_EA_16(state, ea);
- MMULOG(("%s: write SR = %04X\n", __func__, m68ki_cpu.mmu_sr));
+ state->mmu_sr = READ_EA_16(state, ea);
+ MMULOG(("%s: write SR = %04X\n", __func__, state->mmu_sr));
}
break;
default:
- logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes >> 13) & 0x7, modes, m68ki_cpu.pc);
+ logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes >> 13) & 0x7, modes, state->pc);
break;
}
void m68851_mmu_ops(m68ki_cpu_core *state)
{
uint16 modes;
- uint32 ea = m68ki_cpu.ir & 0x3f;
+ uint32 ea = state->ir & 0x3f;
// catch the 2 "weird" encodings up front (PBcc)
- if ((m68ki_cpu.ir & 0xffc0) == 0xf0c0)
+ if ((state->ir & 0xffc0) == 0xf0c0)
{
logerror("680x0: unhandled PBcc\n");
return;
}
- else if ((m68ki_cpu.ir & 0xffc0) == 0xf080)
+ else if ((state->ir & 0xffc0) == 0xf080)
{
logerror("680x0: unhandled PBcc\n");
return;
}
- else if ((m68ki_cpu.ir & 0xffe0) == 0xf500)
+ else if ((state->ir & 0xffe0) == 0xf500)
{
- MMULOG(("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", REG_PC-4, m68ki_cpu.ir, (m68ki_cpu.ir >> 3) & 3, m68ki_cpu.ir & 7));
+ MMULOG(("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", REG_PC-4, state->ir, (state->ir >> 3) & 3, state->ir & 7));
pmmu_atc_flush(state);
}
else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
{
- switch ((m68ki_cpu.ir>>9) & 0x7)
+ switch ((state->ir>>9) & 0x7)
{
case 0:
modes = OPER_I_16(state);
break;
default:
- logerror("680x0: unknown PMMU instruction group %d\n", (m68ki_cpu.ir>>9) & 0x7);
+ logerror("680x0: unknown PMMU instruction group %d\n", (state->ir>>9) & 0x7);
break;
}
}
addr_out = addr_in;
// check if LC 24-bit mode is enabled - this simply blanks out A31, the V8 ignores A30-24 always
- if (m68ki_cpu.hmmu_enabled == M68K_HMMU_ENABLE_LC)
+ if (state->hmmu_enabled == M68K_HMMU_ENABLE_LC)
{
addr_out = addr_in & 0xffffff;
}
- else if (m68ki_cpu.hmmu_enabled == M68K_HMMU_ENABLE_II) // the original II does a more complex translation
+ else if (state->hmmu_enabled == M68K_HMMU_ENABLE_II) // the original II does a more complex translation
{
addr_out = addr_in & 0xffffff;
int m68851_buserror(u32& addr)
{
- if (!m68ki_cpu.pmmu_enabled)
+ if (!state->pmmu_enabled)
{
return false;
}
- if (m68ki_cpu.mmu_tablewalk)
+ if (state->mmu_tablewalk)
{
MMULOG(("buserror during table walk\n"));
- m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
+ state->mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
return true;
}
- addr = m68ki_cpu.mmu_last_logical_addr;
+ addr = state->mmu_last_logical_addr;
return false;
}
*/
projects / pistorm / commitdiff