2 Stockfish, a UCI chess playing engine derived from Glaurung 2.1
3 Copyright (C) 2004-2022 The Stockfish developers (see AUTHORS file)
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13 GNU General Public License for more details.
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19 // Definition of layer AffineTransform of NNUE evaluation function
21 #ifndef NNUE_LAYERS_AFFINE_TRANSFORM_H_INCLUDED
22 #define NNUE_LAYERS_AFFINE_TRANSFORM_H_INCLUDED
26 #include <type_traits>
27 #include "../nnue_common.h"
28 #include "../../simd.h"
31 This file contains the definition for a fully connected layer (aka affine transform).
32 Two approaches are employed, depending on the sizes of the transform.
35 - used when the PaddedInputDimensions >= 128
36 - uses AVX512 if possible
37 - processes inputs in batches of 2*InputSimdWidth
38 - so in batches of 128 for AVX512
39 - the weight blocks of size InputSimdWidth are transposed such that
41 - N columns of the weight matrix are processed a time, where N
42 depends on the architecture (the amount of registers)
43 - accumulate + hadd is used
46 - used when the PaddedInputDimensions < 128
48 - expected use-case is for when PaddedInputDimensions == 32 and InputDimensions <= 32.
49 - that's why AVX512 is hard to implement
50 - expected use-case is small layers
51 - not optimized as well as the approach 1
52 - inputs are processed in chunks of 4, weights are respectively transposed
53 - accumulation happens directly to int32s
56 namespace Stockfish::Eval::NNUE::Layers {
58 // Fallback implementation for older/other architectures.
59 // Identical for both approaches. Requires the input to be padded to at least 16 values.
60 #if !defined(USE_SSSE3)
61 template <IndexType InputDimensions, IndexType PaddedInputDimensions, IndexType OutputDimensions>
62 static void affine_transform_non_ssse3(std::int32_t* output, const std::int8_t* weights, const std::int32_t* biases, const std::uint8_t* input)
64 # if defined(USE_SSE2)
65 // At least a multiple of 16, with SSE2.
66 constexpr IndexType NumChunks = ceil_to_multiple<IndexType>(InputDimensions, 16) / 16;
67 const __m128i Zeros = _mm_setzero_si128();
68 const auto inputVector = reinterpret_cast<const __m128i*>(input);
70 # elif defined(USE_MMX)
71 constexpr IndexType NumChunks = ceil_to_multiple<IndexType>(InputDimensions, 8) / 8;
72 const __m64 Zeros = _mm_setzero_si64();
73 const auto inputVector = reinterpret_cast<const __m64*>(input);
75 # elif defined(USE_NEON)
76 constexpr IndexType NumChunks = ceil_to_multiple<IndexType>(InputDimensions, 16) / 16;
77 const auto inputVector = reinterpret_cast<const int8x8_t*>(input);
80 for (IndexType i = 0; i < OutputDimensions; ++i) {
81 const IndexType offset = i * PaddedInputDimensions;
83 # if defined(USE_SSE2)
84 __m128i sumLo = _mm_cvtsi32_si128(biases[i]);
85 __m128i sumHi = Zeros;
86 const auto row = reinterpret_cast<const __m128i*>(&weights[offset]);
87 for (IndexType j = 0; j < NumChunks; ++j) {
88 __m128i row_j = _mm_load_si128(&row[j]);
89 __m128i input_j = _mm_load_si128(&inputVector[j]);
90 __m128i extendedRowLo = _mm_srai_epi16(_mm_unpacklo_epi8(row_j, row_j), 8);
91 __m128i extendedRowHi = _mm_srai_epi16(_mm_unpackhi_epi8(row_j, row_j), 8);
92 __m128i extendedInputLo = _mm_unpacklo_epi8(input_j, Zeros);
93 __m128i extendedInputHi = _mm_unpackhi_epi8(input_j, Zeros);
94 __m128i productLo = _mm_madd_epi16(extendedRowLo, extendedInputLo);
95 __m128i productHi = _mm_madd_epi16(extendedRowHi, extendedInputHi);
96 sumLo = _mm_add_epi32(sumLo, productLo);
97 sumHi = _mm_add_epi32(sumHi, productHi);
99 __m128i sum = _mm_add_epi32(sumLo, sumHi);
100 __m128i sumHigh_64 = _mm_shuffle_epi32(sum, _MM_SHUFFLE(1, 0, 3, 2));
101 sum = _mm_add_epi32(sum, sumHigh_64);
102 __m128i sum_second_32 = _mm_shufflelo_epi16(sum, _MM_SHUFFLE(1, 0, 3, 2));
103 sum = _mm_add_epi32(sum, sum_second_32);
104 output[i] = _mm_cvtsi128_si32(sum);
106 # elif defined(USE_MMX)
107 __m64 sumLo = _mm_cvtsi32_si64(biases[i]);
109 const auto row = reinterpret_cast<const __m64*>(&weights[offset]);
110 for (IndexType j = 0; j < NumChunks; ++j) {
111 __m64 row_j = row[j];
112 __m64 input_j = inputVector[j];
113 __m64 extendedRowLo = _mm_srai_pi16(_mm_unpacklo_pi8(row_j, row_j), 8);
114 __m64 extendedRowHi = _mm_srai_pi16(_mm_unpackhi_pi8(row_j, row_j), 8);
115 __m64 extendedInputLo = _mm_unpacklo_pi8(input_j, Zeros);
116 __m64 extendedInputHi = _mm_unpackhi_pi8(input_j, Zeros);
117 __m64 productLo = _mm_madd_pi16(extendedRowLo, extendedInputLo);
118 __m64 productHi = _mm_madd_pi16(extendedRowHi, extendedInputHi);
119 sumLo = _mm_add_pi32(sumLo, productLo);
120 sumHi = _mm_add_pi32(sumHi, productHi);
122 __m64 sum = _mm_add_pi32(sumLo, sumHi);
123 sum = _mm_add_pi32(sum, _mm_unpackhi_pi32(sum, sum));
124 output[i] = _mm_cvtsi64_si32(sum);
126 # elif defined(USE_NEON)
127 int32x4_t sum = {biases[i]};
128 const auto row = reinterpret_cast<const int8x8_t*>(&weights[offset]);
129 for (IndexType j = 0; j < NumChunks; ++j) {
130 int16x8_t product = vmull_s8(inputVector[j * 2], row[j * 2]);
131 product = vmlal_s8(product, inputVector[j * 2 + 1], row[j * 2 + 1]);
132 sum = vpadalq_s16(sum, product);
134 output[i] = sum[0] + sum[1] + sum[2] + sum[3];
137 std::int32_t sum = biases[i];
138 for (IndexType j = 0; j < InputDimensions; ++j) {
139 sum += weights[offset + j] * input[j];
145 # if defined(USE_MMX)
151 template <IndexType InDims, IndexType OutDims, typename Enabled = void>
152 class AffineTransform;
154 // A specialization for large inputs.
155 template <IndexType InDims, IndexType OutDims>
156 class AffineTransform<InDims, OutDims, std::enable_if_t<(ceil_to_multiple<IndexType>(InDims, MaxSimdWidth) >= 2*64)>> {
159 using InputType = std::uint8_t;
160 using OutputType = std::int32_t;
162 // Number of input/output dimensions
163 static constexpr IndexType InputDimensions = InDims;
164 static constexpr IndexType OutputDimensions = OutDims;
166 static constexpr IndexType PaddedInputDimensions =
167 ceil_to_multiple<IndexType>(InputDimensions, MaxSimdWidth);
168 static constexpr IndexType PaddedOutputDimensions =
169 ceil_to_multiple<IndexType>(OutputDimensions, MaxSimdWidth);
171 using OutputBuffer = OutputType[PaddedOutputDimensions];
173 static_assert(PaddedInputDimensions >= 128, "Something went wrong. This specialization should not have been chosen.");
175 #if defined (USE_AVX512)
176 static constexpr const IndexType InputSimdWidth = 64;
177 static constexpr const IndexType MaxNumOutputRegs = 16;
178 #elif defined (USE_AVX2)
179 static constexpr const IndexType InputSimdWidth = 32;
180 static constexpr const IndexType MaxNumOutputRegs = 8;
181 #elif defined (USE_SSSE3)
182 static constexpr const IndexType InputSimdWidth = 16;
183 static constexpr const IndexType MaxNumOutputRegs = 8;
184 #elif defined (USE_NEON)
185 static constexpr const IndexType InputSimdWidth = 8;
186 static constexpr const IndexType MaxNumOutputRegs = 8;
188 // The fallback implementation will not have permuted weights.
189 // We define these to avoid a lot of ifdefs later.
190 static constexpr const IndexType InputSimdWidth = 1;
191 static constexpr const IndexType MaxNumOutputRegs = 1;
194 // A big block is a region in the weight matrix of the size [PaddedInputDimensions, NumOutputRegs].
195 // A small block is a region of size [InputSimdWidth, 1]
197 static constexpr const IndexType NumOutputRegs = std::min(MaxNumOutputRegs, OutputDimensions);
198 static constexpr const IndexType SmallBlockSize = InputSimdWidth;
199 static constexpr const IndexType BigBlockSize = NumOutputRegs * PaddedInputDimensions;
200 static constexpr const IndexType NumSmallBlocksInBigBlock = BigBlockSize / SmallBlockSize;
201 static constexpr const IndexType NumSmallBlocksPerOutput = PaddedInputDimensions / SmallBlockSize;
202 static constexpr const IndexType NumBigBlocks = OutputDimensions / NumOutputRegs;
204 static_assert(OutputDimensions % NumOutputRegs == 0);
206 // Hash value embedded in the evaluation file
207 static constexpr std::uint32_t get_hash_value(std::uint32_t prevHash) {
208 std::uint32_t hashValue = 0xCC03DAE4u;
209 hashValue += OutputDimensions;
210 hashValue ^= prevHash >> 1;
211 hashValue ^= prevHash << 31;
216 Transposes the small blocks within a block.
217 Effectively means that weights can be traversed sequentially during inference.
219 static IndexType get_weight_index(IndexType i)
221 const IndexType smallBlock = (i / SmallBlockSize) % NumSmallBlocksInBigBlock;
222 const IndexType smallBlockCol = smallBlock / NumSmallBlocksPerOutput;
223 const IndexType smallBlockRow = smallBlock % NumSmallBlocksPerOutput;
224 const IndexType bigBlock = i / BigBlockSize;
225 const IndexType rest = i % SmallBlockSize;
227 const IndexType idx =
228 bigBlock * BigBlockSize
229 + smallBlockRow * SmallBlockSize * NumOutputRegs
230 + smallBlockCol * SmallBlockSize
236 // Read network parameters
237 bool read_parameters(std::istream& stream) {
238 for (std::size_t i = 0; i < OutputDimensions; ++i)
239 biases[i] = read_little_endian<BiasType>(stream);
241 for (std::size_t i = 0; i < OutputDimensions * PaddedInputDimensions; ++i)
242 weights[get_weight_index(i)] = read_little_endian<WeightType>(stream);
244 return !stream.fail();
247 // Write network parameters
248 bool write_parameters(std::ostream& stream) const {
249 for (std::size_t i = 0; i < OutputDimensions; ++i)
250 write_little_endian<BiasType>(stream, biases[i]);
252 for (std::size_t i = 0; i < OutputDimensions * PaddedInputDimensions; ++i)
253 write_little_endian<WeightType>(stream, weights[get_weight_index(i)]);
255 return !stream.fail();
258 // Forward propagation
259 const OutputType* propagate(
260 const InputType* input, OutputType* output) const {
262 #if defined (USE_AVX512)
263 using acc_vec_t = __m512i;
264 using bias_vec_t = __m128i;
265 using weight_vec_t = __m512i;
266 using in_vec_t = __m512i;
267 #define vec_zero _mm512_setzero_si512()
268 #define vec_add_dpbusd_32x2 Simd::m512_add_dpbusd_epi32x2
269 #define vec_hadd Simd::m512_hadd
270 #define vec_haddx4 Simd::m512_haddx4
271 #elif defined (USE_AVX2)
272 using acc_vec_t = __m256i;
273 using bias_vec_t = __m128i;
274 using weight_vec_t = __m256i;
275 using in_vec_t = __m256i;
276 #define vec_zero _mm256_setzero_si256()
277 #define vec_add_dpbusd_32x2 Simd::m256_add_dpbusd_epi32x2
278 #define vec_hadd Simd::m256_hadd
279 #define vec_haddx4 Simd::m256_haddx4
280 #elif defined (USE_SSSE3)
281 using acc_vec_t = __m128i;
282 using bias_vec_t = __m128i;
283 using weight_vec_t = __m128i;
284 using in_vec_t = __m128i;
285 #define vec_zero _mm_setzero_si128()
286 #define vec_add_dpbusd_32x2 Simd::m128_add_dpbusd_epi32x2
287 #define vec_hadd Simd::m128_hadd
288 #define vec_haddx4 Simd::m128_haddx4
289 #elif defined (USE_NEON)
290 using acc_vec_t = int32x4_t;
291 using bias_vec_t = int32x4_t;
292 using weight_vec_t = int8x8_t;
293 using in_vec_t = int8x8_t;
295 #define vec_add_dpbusd_32x2 Simd::neon_m128_add_dpbusd_epi32x2
296 #define vec_hadd Simd::neon_m128_hadd
297 #define vec_haddx4 Simd::neon_m128_haddx4
300 #if defined (USE_SSSE3) || defined (USE_NEON)
301 const in_vec_t* invec = reinterpret_cast<const in_vec_t*>(input);
303 // Perform accumulation to registers for each big block
304 for (IndexType bigBlock = 0; bigBlock < NumBigBlocks; ++bigBlock)
306 acc_vec_t acc[NumOutputRegs] = { vec_zero };
308 // Each big block has NumOutputRegs small blocks in each "row", one per register.
309 // We process two small blocks at a time to save on one addition without VNNI.
310 for (IndexType smallBlock = 0; smallBlock < NumSmallBlocksPerOutput; smallBlock += 2)
312 const weight_vec_t* weightvec =
313 reinterpret_cast<const weight_vec_t*>(
315 + bigBlock * BigBlockSize
316 + smallBlock * SmallBlockSize * NumOutputRegs);
318 const in_vec_t in0 = invec[smallBlock + 0];
319 const in_vec_t in1 = invec[smallBlock + 1];
321 for (IndexType k = 0; k < NumOutputRegs; ++k)
322 vec_add_dpbusd_32x2(acc[k], in0, weightvec[k], in1, weightvec[k + NumOutputRegs]);
325 // Horizontally add all accumulators.
326 if constexpr (NumOutputRegs % 4 == 0)
328 bias_vec_t* outputvec = reinterpret_cast<bias_vec_t*>(output);
329 const bias_vec_t* biasvec = reinterpret_cast<const bias_vec_t*>(biases);
331 for (IndexType k = 0; k < NumOutputRegs; k += 4)
333 const IndexType idx = (bigBlock * NumOutputRegs + k) / 4;
334 outputvec[idx] = vec_haddx4(acc[k+0], acc[k+1], acc[k+2], acc[k+3], biasvec[idx]);
339 for (IndexType k = 0; k < NumOutputRegs; ++k)
341 const IndexType idx = (bigBlock * NumOutputRegs + k);
342 output[idx] = vec_hadd(acc[k], biases[idx]);
348 # undef vec_add_dpbusd_32x2
352 // Use old implementation for the other architectures.
353 affine_transform_non_ssse3<
355 PaddedInputDimensions,
356 OutputDimensions>(output, weights, biases, input);
364 using BiasType = OutputType;
365 using WeightType = std::int8_t;
367 alignas(CacheLineSize) BiasType biases[OutputDimensions];
368 alignas(CacheLineSize) WeightType weights[OutputDimensions * PaddedInputDimensions];
371 template <IndexType InDims, IndexType OutDims>
372 class AffineTransform<InDims, OutDims, std::enable_if_t<(ceil_to_multiple<IndexType>(InDims, MaxSimdWidth) < 2*64)>> {
376 using InputType = std::uint8_t;
377 using OutputType = std::int32_t;
379 // Number of input/output dimensions
380 static constexpr IndexType InputDimensions = InDims;
381 static constexpr IndexType OutputDimensions = OutDims;
383 static constexpr IndexType PaddedInputDimensions =
384 ceil_to_multiple<IndexType>(InputDimensions, MaxSimdWidth);
385 static constexpr IndexType PaddedOutputDimensions =
386 ceil_to_multiple<IndexType>(OutputDimensions, MaxSimdWidth);
388 using OutputBuffer = OutputType[PaddedOutputDimensions];
390 static_assert(PaddedInputDimensions < 128, "Something went wrong. This specialization should not have been chosen.");
392 #if defined (USE_SSSE3)
393 static constexpr const IndexType OutputSimdWidth = SimdWidth / 4;
394 static constexpr const IndexType InputSimdWidth = SimdWidth;
397 // Hash value embedded in the evaluation file
398 static constexpr std::uint32_t get_hash_value(std::uint32_t prevHash) {
399 std::uint32_t hashValue = 0xCC03DAE4u;
400 hashValue += OutputDimensions;
401 hashValue ^= prevHash >> 1;
402 hashValue ^= prevHash << 31;
406 static IndexType get_weight_index_scrambled(IndexType i)
409 (i / 4) % (PaddedInputDimensions / 4) * OutputDimensions * 4 +
410 i / PaddedInputDimensions * 4 +
414 static IndexType get_weight_index(IndexType i)
416 #if defined (USE_SSSE3)
417 return get_weight_index_scrambled(i);
423 // Read network parameters
424 bool read_parameters(std::istream& stream) {
425 for (std::size_t i = 0; i < OutputDimensions; ++i)
426 biases[i] = read_little_endian<BiasType>(stream);
427 for (std::size_t i = 0; i < OutputDimensions * PaddedInputDimensions; ++i)
428 weights[get_weight_index(i)] = read_little_endian<WeightType>(stream);
430 return !stream.fail();
433 // Write network parameters
434 bool write_parameters(std::ostream& stream) const {
435 for (std::size_t i = 0; i < OutputDimensions; ++i)
436 write_little_endian<BiasType>(stream, biases[i]);
438 for (std::size_t i = 0; i < OutputDimensions * PaddedInputDimensions; ++i)
439 write_little_endian<WeightType>(stream, weights[get_weight_index(i)]);
441 return !stream.fail();
443 // Forward propagation
444 const OutputType* propagate(
445 const InputType* input, OutputType* output) const {
447 #if defined (USE_AVX2)
448 using vec_t = __m256i;
449 #define vec_setzero _mm256_setzero_si256
450 #define vec_set_32 _mm256_set1_epi32
451 #define vec_add_dpbusd_32 Simd::m256_add_dpbusd_epi32
452 #define vec_add_dpbusd_32x2 Simd::m256_add_dpbusd_epi32x2
453 #define vec_add_dpbusd_32x4 Simd::m256_add_dpbusd_epi32x4
454 #define vec_hadd Simd::m256_hadd
455 #define vec_haddx4 Simd::m256_haddx4
456 #elif defined (USE_SSSE3)
457 using vec_t = __m128i;
458 #define vec_setzero _mm_setzero_si128
459 #define vec_set_32 _mm_set1_epi32
460 #define vec_add_dpbusd_32 Simd::m128_add_dpbusd_epi32
461 #define vec_add_dpbusd_32x2 Simd::m128_add_dpbusd_epi32x2
462 #define vec_add_dpbusd_32x4 Simd::m128_add_dpbusd_epi32x4
463 #define vec_hadd Simd::m128_hadd
464 #define vec_haddx4 Simd::m128_haddx4
467 #if defined (USE_SSSE3)
468 const auto inputVector = reinterpret_cast<const vec_t*>(input);
470 static_assert(OutputDimensions % OutputSimdWidth == 0 || OutputDimensions == 1);
472 if constexpr (OutputDimensions % OutputSimdWidth == 0)
474 constexpr IndexType NumChunks = ceil_to_multiple<IndexType>(InputDimensions, 8) / 4;
475 constexpr IndexType NumRegs = OutputDimensions / OutputSimdWidth;
477 const auto input32 = reinterpret_cast<const std::int32_t*>(input);
478 const vec_t* biasvec = reinterpret_cast<const vec_t*>(biases);
480 for (IndexType k = 0; k < NumRegs; ++k)
483 for (IndexType i = 0; i < NumChunks; i += 2)
485 const vec_t in0 = vec_set_32(input32[i + 0]);
486 const vec_t in1 = vec_set_32(input32[i + 1]);
487 const auto col0 = reinterpret_cast<const vec_t*>(&weights[(i + 0) * OutputDimensions * 4]);
488 const auto col1 = reinterpret_cast<const vec_t*>(&weights[(i + 1) * OutputDimensions * 4]);
489 for (IndexType k = 0; k < NumRegs; ++k)
490 vec_add_dpbusd_32x2(acc[k], in0, col0[k], in1, col1[k]);
493 vec_t* outptr = reinterpret_cast<vec_t*>(output);
494 for (IndexType k = 0; k < NumRegs; ++k)
497 else if constexpr (OutputDimensions == 1)
499 constexpr IndexType NumChunks = PaddedInputDimensions / SimdWidth;
500 vec_t sum0 = vec_setzero();
501 const auto row0 = reinterpret_cast<const vec_t*>(&weights[0]);
503 for (int j = 0; j < (int)NumChunks; ++j)
505 const vec_t in = inputVector[j];
506 vec_add_dpbusd_32(sum0, in, row0[j]);
508 output[0] = vec_hadd(sum0, biases[0]);
513 # undef vec_add_dpbusd_32
514 # undef vec_add_dpbusd_32x2
515 # undef vec_add_dpbusd_32x4
519 // Use old implementation for the other architectures.
520 affine_transform_non_ssse3<
522 PaddedInputDimensions,
523 OutputDimensions>(output, weights, biases, input);
530 using BiasType = OutputType;
531 using WeightType = std::int8_t;
533 alignas(CacheLineSize) BiasType biases[OutputDimensions];
534 alignas(CacheLineSize) WeightType weights[OutputDimensions * PaddedInputDimensions];
537 } // namespace Stockfish::Eval::NNUE::Layers
539 #endif // #ifndef NNUE_LAYERS_AFFINE_TRANSFORM_H_INCLUDED